Attention is currently required from: Eric Lai, Jan Samek, Mario Scheithauer, Sean Rhodes, Werner Zeh.
Hello Eric Lai, Felix Singer, Jan Samek, Sean Rhodes, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75820?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+1 by Jan Samek, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion ......................................................................
soc/intel/apollolake: Fix FSP SATA speed limit configuraion
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit configurable") came the expansion to adjust the SATA speed. Unfortunately, APL FSP-S sets only the default value, so Gen 3, and ignores the passing parameter value. Since the corresponding register entry can only be changed once, the setting must be made on coreboot side before FSP-S is called. This patch fixes the SATA speed configuration for Apollo Lake CPUs.
Link to Intel Pentium and Celeron N- and J- series datasheet volume 2: https://web.archive.org/web/20230614130311/https://www.intel.com/content/www...
BUG=none TEST=Boot into Linux and check SATA configuration via dmesg
ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA mode ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126 ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/ahci.c M src/soc/intel/apollolake/chip.c A src/soc/intel/apollolake/include/soc/ahci.h 4 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/75820/8