Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41690 )
Change subject: mb/ocp/deltalake: Config PCH PCIe ports in devicetree ......................................................................
Patch Set 18: Code-Review+2
(4 comments)
Thanks. This is my last comment
https://review.coreboot.org/c/coreboot/+/41690/18/src/soc/intel/xeon_sp/cpx/... File src/soc/intel/xeon_sp/cpx/chip.h:
https://review.coreboot.org/c/coreboot/+/41690/18/src/soc/intel/xeon_sp/cpx/... PS18, Line 17: UPD_PCH_PCIE_PORT pch_pcie_port
since it is outside of the src/vendorcode/intel/... directory now, there is no need to use the edk2-style of the struct names.
https://review.coreboot.org/c/coreboot/+/41690/18/src/soc/intel/xeon_sp/cpx/... PS18, Line 30: PCIE_LINK_SPEED pcie_link_speed
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... PS17, Line 49: #define MAX_PCH_PCIE_PORT 20
see comment below
Done
https://review.coreboot.org/c/coreboot/+/41690/17/src/vendorcode/intel/fsp/f... PS17, Line 145: /** : UPD_PCH_PCIE_PORT: : ForceEnable - Enable/Disable PCH PCIe port : PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set : **/ : struct UPD_PCH_PCIE_PORT { : UINT8 ForceEnable; : UINT8 PortLinkSpeed; : }; : : /** : PCIe Link Speed Selection : **/ : typedef enum { : PcieAuto = 0, : PcieGen1, : PcieGen2, : PcieGen3 : } PCIE_LINK_SPEED;
Any reason to add this structure and enum to FspmUpd.h? […]
Ack