[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_common_mtrrs()

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34809 )

Change subject: arch/x86: Add postcar_frame_common_mtrrs()
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34809/2/src/arch/x86/postcar_loader... 
File src/arch/x86/postcar_loader.c:

https://review.coreboot.org/c/coreboot/+/34809/2/src/arch/x86/postcar_loader... 
PS2, Line 125: 	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
> Well currently we do. […]

I believe the final BSP MTRR's are already set up before the SIPI call. Besides does it even make much sense to want to cache the SIPI vector? The AP's MTRR's are not synced at that point or does it speed up setting up that stub?

Maybe this a vague remainder of non-relocatable ramstage?