[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update chip files

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )

Change subject: soc/intel/tigerlake: Update chip files
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... 
PS6, Line 180: 		ProbeTypeDisable	= 0x00,
> This is in sync with FSP settings where is 0x01 is not used.

What version of FSP headers?