Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59845 )
Change subject: soc/block/systemagent: Do more fine grained resource allocation ......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/59845/comment/8ada0417_880060be PS1, Line 191: reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB);
IIRC, the cacheability of TSEG is ultimately decided by SMRRs, which override MTRR settings. With this patch, I'd expect MTRR usage to increase.
Not quite. Often TOLUD is a multiple of 1G, so marking TSEG, which is below TOLUD, as WB instead of UC improves the solution.