[coreboot-gerrit] Change in coreboot[master]: vc/amd/fsp/picasso: add logical to lane number in port descriptor struct

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43660 )

Change subject: vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43660/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43660/4//COMMIT_MSG@11 
PS4, Line 11: fsp_pcie_descriptor struct.
> for Picasso and Dali there is some documentation in the PPR on that; the mapping on Pollock is diffe […]

https://b.corp.google.com/issues/162423378 has all the many pieces of confusion and lack of clarity in the documentation. Those phy sharing tables don't appear correct for the actual combinations even for dali/picasso. And, as you noted, Pollock has *no documentation* that I can access.