Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56310 )
Change subject: include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR ......................................................................
include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/cpu/amd/pi/00730F01/update_microcode.c M src/include/cpu/amd/msr.h M src/soc/amd/common/block/cpu/update_microcode.c 3 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/56310/1
diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index ccf6468..8942f01 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -78,7 +78,7 @@ printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
- msr = rdmsr(MSR_PATCH_LEVEL); + msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo;
if (new_patch_id == m->patch_id) diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index f9d20ef..aaecfde 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -80,7 +80,6 @@ #define S3_RESUME_EIP_MSR 0xC00110E0 #define PSP_ADDR_MSR 0xc00110a2
-#define MSR_PATCH_LEVEL 0x0000008B #define CORE_PERF_BOOST_CTRL 0x15c
#endif /* CPU_AMD_MSR_H */ diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 2822d2f..6d910e7 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -49,7 +49,7 @@ printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
- msr = rdmsr(MSR_PATCH_LEVEL); + msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo;
if (new_patch_id == m->patch_id)