[coreboot-gerrit] Change in coreboot[master]: mb/google/asurada: Init dram in romstage

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44568 )

Change subject: mb/google/asurada: Init dram in romstage
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Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44568/11/src/mainboard/google/asura... 
File src/mainboard/google/asurada/romstage.c:

https://review.coreboot.org/c/coreboot/+/44568/11/src/mainboard/google/asura... 
PS11, Line 17: static bool read_calibration_data_from_flash(struct dramc_param *dparam)
             : {
             : 	const size_t length = sizeof(*dparam);
             : 	size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length);
             : 	printk(BIOS_DEBUG, "read data from flash, ret=%#zx, length=%#zx\n", ret, length);
             : 
             : 	return ret == length;
             : }
             : 
             : static bool write_calibration_data_to_flash(const struct dramc_param *dparam)
             : {
             : 	const size_t length = sizeof(*dparam);
             : 	size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length);
             : 	printk(BIOS_DEBUG, "write data from flash, ret=%#zx, length=%#zx\n", ret, length);
             : 
             : 	return ret == length;
             : }
Why can’t these be SoC functions?