Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44717 )
Change subject: soc/mediatek/mt8192: Do write leveling training ......................................................................
Patch Set 45:
(9 comments)
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4104: {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 16}, Move to its own line.
reg_transfer ui_regs[] = { {...}, {...}, };
Same below.
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4115: u8 int
Same below.
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4121: u8 int
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4220: dqs_final_dly[RANK_MAX][DQS_NUMBER] Since only dqs_final_dly[cali->rank] is referenced, how about passing dqs_final_delay[rank] from the caller?
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4240: ( No parentheses
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4258: size_t int
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4271: size_t int
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 4275: d u
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44717/45/src/soc/mediatek/mt8192/dr... PS45, Line 271: should disable the auto refresh before do write leveling Disable auto refresh before doing write leveling