Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37229 )
Change subject: hatch: Create stryke variant ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 13: SPD_SOURCES = 4G_2400 # 0b000 : SPD_SOURCES += empty_ddr4 # 0b001 : SPD_SOURCES += 8G_2400 # 0b010 : SPD_SOURCES += 8G_2666 # 0b011 : SPD_SOURCES += 16G_2400 # 0b100 : SPD_SOURCES += 16G_2666 # 0b101 : SPD_SOURCES += 8G_3200 # 0b110 The build scripts generate a single file by concatenating the SPD files specified here, in order. That file is treated like an array of SPD data: coreboot reads the memory config GPIOs and uses the numeric value as the index. This assumes that all SPD files have the same length.
So, to make this work, this has to match a table in the schematics, which has the "RAM index" and the corresponding memory configuration.
As I don't have the schematics of this board, I don't know if this is accurate.
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 20: /* Copied from baseboard and may need to change for the new variant. */ Very likely that this needs to be changed. I don't have access to any schematics, so I can't check.
Note that the order is important: the values on these pins represent an index number.
Additionally, the current code uses `GPP_F2` to detect single/dual channel (0: dual channel, 1: single channel)
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 3: register "SerialIoDevMode" = "{ Some of these seem to be unused and could be "PchSerialIoDisabled"
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 46: .i2c[3] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 150, : .fall_time_ns = 150, : }, Looks like I2C3 is disabled in the devicetree?
device pci 15.3 off end # I2C #3