Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35649 )
Change subject: cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ use ......................................................................
cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ use
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/arch/x86/include/arch/cpu.h M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/cpu.h M src/include/device/pci.h 4 files changed, 12 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 263b734..ffa532b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -214,7 +214,8 @@ return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); }
-#ifndef __SIMPLE_DEVICE__ +#ifndef __ROMCC__ +/* romcc does not support anonymous structs. */
struct device;
@@ -258,9 +259,8 @@ ); return ci; } -#endif
-#ifndef __ROMCC__ // romcc is segfaulting in some cases +/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 5d7ff2c..02dfbdc 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -38,9 +38,6 @@ return -1; }
-#ifdef __ROMCC__ -static -#endif void set_var_mtrr( unsigned int reg, unsigned int base, unsigned int size, unsigned int type) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9a28373..cdb6817 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,7 +3,6 @@
#include <arch/cpu.h>
-#if !defined(__ROMCC__) void cpu_initialize(unsigned int cpu_index); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ int cpu_get_apic_id(int logical_cpu); @@ -14,13 +13,15 @@ asmlinkage void secondary_cpu_init(unsigned int cpu_index); int cpu_phys_address_size(void);
+#if ENV_RAMSTAGE #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver"))) -#ifndef __SIMPLE_DEVICE__ +#else +#define __cpu_driver __attribute__((unused)) +#endif + /** start of compile time generated pci driver array */ extern struct cpu_driver _cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver _ecpu_drivers[]; -#endif -#endif /* !__ROMCC__ */
#endif /* CPU_CPU_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index fa695d4..8d6a9ae 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -55,11 +55,12 @@ u32 vec_control; };
-#ifdef __SIMPLE_DEVICE__ -#define __pci_driver __attribute__((unused)) -#else +#if ENV_RAMSTAGE #define __pci_driver __attribute__((used, __section__(".rodata.pci_driver"))) +#else +#define __pci_driver __attribute__((unused)) #endif + /** start of compile time generated pci driver array */ extern struct pci_driver _pci_drivers[]; /** end of compile time generated pci driver array */ @@ -119,12 +120,10 @@ u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);
-#ifndef __ROMCC__ static inline int pci_base_address_is_memory_space(unsigned int attr) { return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; } -#endif
#endif /* CONFIG_PCI */