Patrick Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56895 )
Change subject: src/mainboard/google/guybrush/variants/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device. ......................................................................
src/mainboard/google/guybrush/variants/baseboard: Set Clk request for WLAN/SD/WWAN/SSD device.
Set the clock source deponds on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. Currently in guybeush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256 BRANCH=none TEST:Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang patrick.huang@amd.corp-partner.google.com Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56895/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index f9a1201..689634e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -58,6 +58,15 @@ register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC
+ # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_BALANCED"
register "usb_phy_custom" = "1"