Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81926?usp=email )
Change subject: sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN ......................................................................
sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN
According to datasheet, the enable bit for direct I/O access to GPIO lines is at CR30[3] of LDN 8, not [0] as currently coded.
Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2 Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926 Reviewed-by: Eric Lai ericllai@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/superio/nuvoton/nct6779d/nct6779d.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h index 85f4081..30694ea 100644 --- a/src/superio/nuvoton/nct6779d/nct6779d.h +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -22,7 +22,7 @@
/* virtual LDN for GPIO */
-#define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V) +#define NCT6779D_GPIOBASE ((3 << 8) | NCT6779D_WDT1_GPIO01_V)
#define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V) #define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V)