David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44806 )
Change subject: mb/google/duffy: Override power limits configuration ......................................................................
mb/google/duffy: Override power limits configuration
Override SysPl2, SysPl3 and Pl4 values, based on our experiment results.
BUG=b:160676773 TEST=Built and check firmware log.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: If5385f58cd8a7a89f4e78c79c21573e897e27072 --- M src/mainboard/google/hatch/variants/duffy/Makefile.inc A src/mainboard/google/hatch/variants/duffy/mainboard.c 2 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44806/1
diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc index 3b5b7d0..2afd494 100644 --- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc +++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc @@ -1,4 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c +ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c new file mode 100644 index 0000000..9b0089b --- /dev/null +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> +#include <soc/pci_devs.h> + +/* + * For type-C chargers, set PSYSPL2 to 97% of max power. + */ +#define SET_PSYSPL2(w) (97 * (w) / 100) + +/* + * mainboard_override_power_limits + * + * Override SysPl2, SysPl3 and Pl4 values. + * n = max value of power adapter. + * For USB C charger: + * +-------------+---------+---------+-------+ + * | Max Power(W)| PsysPL2 | PsysPL3 | PL4 | + * +-------------+---------+---------+-------+ + * | n | 0.97n | 0.97n | 0.97n | + * +-------------+---------+---------+-------+ + */ + +static void mainboard_override_power_limits(struct soc_power_limits_config *conf) +{ + enum usb_chg_type type; + u32 watts; + u16 volts_mv, current_ma; + u32 psyspl2; + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(watts); + + conf->tdp_psyspl2 = psyspl2; + conf->tdp_psyspl3 = psyspl2; + conf->tdp_pl4 = psyspl2; + } +} + +void variant_mainboard_enable(struct device *dev) +{ + struct soc_power_limits_config *soc_config; + config_t *conf = config_of_soc(); + + soc_config = &conf->power_limits_config; + mainboard_override_power_limits(soc_config); +}