Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21704
Change subject: google/cyan: fix variant memory/silicon init params overrride ......................................................................
google/cyan: fix variant memory/silicon init params overrride
The mainboard_memory_init_params() and mainboard_silicon_init_params() methods already have weak declarations in drivers/intel/fsp1_1, so having them declared as weak in the cyan baseboard has the effect of them not being called at all unless overriden at the variant level. Therefore, remove the weak declarations in the baseboard and ensure that each variant has its own init functions if needed.
TEST: build/boot google/cyan
Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/cyan/ramstage.c M src/mainboard/google/cyan/romstage.c M src/mainboard/google/cyan/variants/celes/Makefile.inc A src/mainboard/google/cyan/variants/celes/romstage.c M src/mainboard/google/cyan/variants/cyan/Makefile.inc A src/mainboard/google/cyan/variants/cyan/romstage.c M src/mainboard/google/cyan/variants/edgar/Makefile.inc A src/mainboard/google/cyan/variants/edgar/romstage.c M src/mainboard/google/cyan/variants/reks/Makefile.inc A src/mainboard/google/cyan/variants/reks/romstage.c 10 files changed, 112 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/21704/1
diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index 093a49b..1da5b44 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -12,10 +12,3 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include <soc/ramstage.h> - -__attribute__ ((weak)) -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ -} diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 57c40e0..39088bb 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -15,7 +15,6 @@ */
#include <soc/romstage.h> -#include <chip.h>
/* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) @@ -26,17 +25,4 @@
/* Call back into chipset code with platform values updated. */ romstage_common(rp); -} - -__attribute__ ((weak)) -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - /* Update SPD data */ - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - } - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; } diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 0fcc9ad..23d2c72 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ##
+romstage-y += romstage.c romstage-y += spd_util.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/celes/romstage.c b/src/mainboard/google/cyan/variants/celes/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/celes/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index ea80446..76de7be 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ##
+romstage-y += romstage.c romstage-y += spd_util.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/cyan/romstage.c b/src/mainboard/google/cyan/variants/cyan/romstage.c new file mode 100644 index 0000000..717db35 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index e553c88..d9a7c7b 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ##
+romstage-y += romstage.c romstage-y += spd_util.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index 6577124..db2eea3 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ##
+romstage-y += romstage.c romstage-y += spd_util.c
ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +}