Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84112?usp=email )
Change subject: mb/google/brox/jubilant: Update GPE0 routing ......................................................................
mb/google/brox/jubilant: Update GPE0 routing
Update GPE0 routing for FP wake source.
BUG=None TEST= Build jubilant firmware Check eventlog of FP wake up
Change-Id: Ia1ad27786e0e3bd9c2110c8a28ab962c5567e16d Signed-off-by: Ren Kuo ren.kuo@quanta.corp-partner.google.com --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/84112/1
diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 9599769..755acdd 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -18,6 +18,12 @@ end
chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + register "platform_pmax" = "208"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 @@ -393,7 +399,7 @@ register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" + register "wake" = "GPE0_DW1_15" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"