Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83938?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins)
Change subject: mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi ......................................................................
mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi
Details: - This patch adds soc acpi file entry in mainboard dsdt.asl - PTL replaces DMI3 with SAF, to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE gaurd check is added in northbridge.asl
BUG=b:348678529 TEST=Able to build the google/fatcat and boot to bootblock stage using Intel® Simics® Pre Silicon Simulation platform for PTL.
Change-Id: I284a1eba19c03008f3e57f1427a72affb2129a8b Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/mainboard/google/fatcat/dsdt.asl M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/pantherlake/include/soc/iomap.h 4 files changed, 38 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83938/2