[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
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soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct

This patch makes correct address bit value for CONFIG_CPU_ADDR_BITS.
> cat /proc/cpuinfo

address sizes	: 39 bits physical, 48 bits virtual

Also this change helps to generate correct MTRR mask value while
using set_var_mtrr().

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 6dbf35f..d23cdf9 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -111,6 +111,10 @@
    select FSP_T_XIP if FSP_CAR
    select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE

+config CPU_ADDR_BITS
+	int
+	default 39
+
 config DCACHE_RAM_BASE
    default 0xfef00000

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 99000bb..de2b4e7 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -62,6 +62,10 @@
    select DISPLAY_FSP_VERSION_INFO
    select HECI_DISABLE_USING_SMM

+config CPU_ADDR_BITS
+	int
+	default 39
+
 config DCACHE_RAM_BASE
    default 0xfef00000