Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25668
Change subject: soc/intel/cannonlake: Force LPC IO decode settings ......................................................................
soc/intel/cannonlake: Force LPC IO decode settings
Force PCH LPC generic IO ranges are identical between PCH LPC pci config space and DMI PCR registers. Reference documentation from 570374 chapter 2.4.1.
Bug=77944335 TEST=Boot up in OS in meowth board, using iotools to read LPC pci config space offset 0x84~0x90 and compare with values read from DMI PCR private register offset 0x2730~0x273c are identical.
Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/lpc.c 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25668/1
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c02d66e..9d3488a 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -30,6 +30,7 @@ #include <intelblocks/pcr.h> #include <reg_script.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h>
@@ -68,6 +69,19 @@ }
#if ENV_RAMSTAGE +static void soc_mirror_dmi_pcr_io_dec(void) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, + pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, + pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, + pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC)); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, + pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC)); +} + static void pch_enable_ioapic(const struct device *dev) { u32 reg32; @@ -202,6 +216,7 @@ setup_i8259(); i8259_configure_irq_trigger(9, 1); clock_gate_8254(dev); + soc_mirror_dmi_pcr_io_dec(); }
/* Fill up LPC IO resource structure inside SoC directory */