[coreboot-gerrit] Change in coreboot[master]: WIP: Testing coreboot callbacks from FSP

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58991 )

Change subject: WIP: Testing coreboot callbacks from FSP
......................................................................

WIP: Testing coreboot callbacks from FSP

Signed-off-by: Raul E Rangel 
Change-Id: I02818987a574f14f790d34f4f0af6b993c520727
---
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/cezanne/fsp_s_params.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
M src/vendorcode/amd/fsp/cezanne/FspsUpd.h
4 files changed, 23 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58991/1

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index a220ab0..ccd5435 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -11,6 +11,7 @@
 #include <soc/platform_descriptors.h>
 #include <soc/pci_devs.h>
 #include <string.h>
+#include <thread.h>
 #include <types.h>
 #include "chip.h"

@@ -64,6 +65,12 @@
    mcfg->fch_ioapic_id = FCH_IOAPIC_ID;
 }

+static void my_yield(void)
+{
+	printk(BIOS_ERR, "Got called from FSP-M!\n");
+	thread_yield();
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
@@ -158,6 +165,8 @@
    else
    	mcfg->usb_phy = NULL;

+	mcfg->void_function = (uintptr_t)my_yield;
+
    fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);
    mb_pre_fspm();
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 60f3942..9550f7e 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -5,16 +5,24 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
+#include <thread.h>

static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
    scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }

+static void my_yield(void)
+{
+	thread_yield();
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
    FSP_S_CONFIG *scfg = &supd->FspsConfig;

+	scfg->void_function = (uintptr_t)my_yield;
+
    fsp_assign_vbios_upds(scfg);

/*
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index f21ca42..294e896 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -27,7 +27,8 @@
    /** Offset 0x007C**/	uint32_t                    serial_reserved;
    /** Offset 0x0080**/	uint8_t                     dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
    /** Offset 0x0358**/	uint8_t                     fsp_owns_pcie_resets;
-	/** Offset 0x0359**/	uint8_t                     pcie_reserved[51];
+	/** Offset 0x0359**/	uint32_t                    void_function;
+	/** Offset 0x035D**/	uint8_t                     pcie_reserved2[47];
    /** Offset 0x038C**/	uint32_t                    ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
    /** Offset 0x03A0**/	uint8_t                     ddi_reserved[6];
    /** Offset 0x03A6**/	uint8_t                     ccx_down_core_mode;
diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
index 3ac52c0..0bb3343 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
@@ -11,8 +11,10 @@

typedef struct __packed {
    /** Offset 0x0020**/	uint32_t                    vbios_buffer;
-	/** Offset 0x0024**/	uint64_t                    gop_reserved;
-	/** Offset 0x002C**/	uint32_t                    reserved1;
+	/** Offset 0x0024**/	uint16_t                    gop_edp_init_delay;
+	/** Offset 0x0026**/	uint16_t                    gop_reserved1;
+	/** Offset 0x0028**/	uint32_t                    gop_reserved2;
+	/** Offset 0x002C**/	uint32_t                    void_function;
    /** Offset 0x0030**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;