[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29324

Change subject: soc/intel/cannonlake: Add additional UPD
......................................................................

soc/intel/cannonlake: Add additional UPD

* Add CleanMemory option

Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27
Signed-off-by: Philipp Deppenwiese 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29324/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index abe029a..ddd5382 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -262,6 +262,11 @@

endchoice

+config USE_CANNONLAKE_CLEAN_MEMORY
+	bool "Use Clean Memory"
+	help
+	  Ask MRC to clear memory content.
+
 config FSP_HEADER_PATH
    string
    default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 6167346..43eb153 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -205,6 +205,11 @@
    params->Device4Enable = config->Device4Enable;
    params->SkipMpInit = !chip_get_fsp_mp_init();

+	if (IS_ENABLED(CONFIG_USE_CANNONLAKE_CLEAN_MEMORY))
+		params->CleanMemory = 1;
+	else
+		params->CleanMemory = 0;
+
    /* VrConfig Settings for 5 domains
     * 0 = System Agent, 1 = IA Core, 2 = Ring,
     * 3 = GT unsliced,  4 = GT sliced */