[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )

Change subject: soc/intel/tigerlake: Do initial SoC commit
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Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi/pci_irqs.asl:

https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/acp... 
PS8, Line 100: 11
> > didn't get ur thought ?
>
> In PICB IRQ16-23 (A-H) get mapped to 11 or 10 (IRQ17/B). Since you know the IRQ information at compile time you could easily generate this whole file in ssdt. See southbridge/intel/common/acpi_pirq_gen.c. I could work on implementing this on cannonlake or icelake if you want (and can test it).

Thanks, please feel free to chime in on dynamic generation of IRQ mapping