[coreboot-gerrit] New patch to review for coreboot: 38549d2 exynos5420: Set the CLK_DIV_CPERI1 value as per manual

[Isaac Christensen]

Isaac Christensen ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6512

-gerrit

commit 38549d20434692bc75bde7a3b54d5929c87d0080
Author: David Hendricks 
Date:   Thu Aug 22 16:52:38 2013 -0700

exynos5420: Set the CLK_DIV_CPERI1 value as per manual

Set the CLK_DIV_CPERI1 value as recommended by the
    0.02 UM section 7.9.1.25.
    This suggests to use 0x3F3F0000 as the value to be
    set to save power.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64905
    Signed-off-by: David Hendricks

Change-Id: I89a6a72d20374a513019a272628a05e139b31773
    Reviewed-on: https://gerrit.chromium.org/gerrit/66787
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    Reviewed-by: Ronald G. Minnich 
    (cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37)
    Signed-off-by: Isaac Christensen 
---
 src/cpu/samsung/exynos5420/clock_init.c | 2 ++
 src/cpu/samsung/exynos5420/setup.h      | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index eeeda90..15cd0c0 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -209,6 +209,8 @@ void system_clock_init(void)
    writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
    writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);

+	writel(CLK_DIV_CPERI1_VAL, &clk->clk_div_cperi1);
+
    writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
    writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
    writel(CLK_DIV_G2D, &clk->clk_div_g2d);
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 8f14a91..ca7281d 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -48,6 +48,8 @@ struct exynos5_phy_control;
 #define APLL_FOUT	(1 << 0)
 #define KPLL_FOUT	(1 << 0)

+#define CLK_DIV_CPERI1_VAL	0x3f3f0000
+
 /* APLL_CON1	*/
 #define APLL_CON1_VAL	(0x0020f300)