Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11011
-gerrit
commit 01231c3b3a4f98366e8a1b523a6a591415ad89d8 Author: Aaron Durbin adurbin@chromium.org Date: Fri Jul 17 16:52:10 2015 -0500
skylake: add global reset cause registers to power state
Log the global reset causes in the power state structure. While working in there pack the struct and use width-specific types as this struct crosses the romstate <-> ramstage boundary. Lastly, remove hsio version as it wasn't being written or read.
After global reset induced: PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 00000000 00000000 00000000 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: d8010200 00003808 GBLRST_CAUSE: 00000000 00040004 Previous Sleep State: S0
BUG=None BRANCH=None TEST=Induced global reset on glados using ETR3 register and write to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47 Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617 Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/286640 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/include/soc/pm.h | 7 +++---- src/soc/intel/skylake/include/soc/pmc.h | 2 ++ src/soc/intel/skylake/romstage/power_state.c | 12 ++++++++++-- 3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 2e722bf..6b75641 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -129,10 +129,9 @@ struct chipset_power_state { uint32_t gpe0_en[4]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; - int prev_sleep_state; - uint16_t hsio_version; - uint16_t hsio_checksum; -}; + uint32_t gblrst_cause[0]; + uint32_t prev_sleep_state; +} __attribute__ ((packed));
/* PM1_CNT */ void enable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 72c9a59..699e795 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -57,6 +57,8 @@ #define S5AC_GATE_SUS (1 << 14) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) +#define GBLRST_CAUSE0 0x124 +#define GBLRST_CAUSE1 0x128
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 5c94e89..68a11a4 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -54,10 +54,10 @@ static void migrate_power_state(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
/* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int prev_sleep_state(struct chipset_power_state *ps) +static uint32_t prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = SLEEP_STATE_S0; + uint32_t prev_sleep_state = SLEEP_STATE_S0;
if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { @@ -112,6 +112,9 @@ static void dump_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); + printk(BIOS_DEBUG, "Previous Sleep State: S%d\n", ps->prev_sleep_state); } @@ -120,6 +123,7 @@ static void dump_power_state(struct chipset_power_state *ps) struct chipset_power_state *fill_power_state(void) { uint16_t tcobase; + uint8_t *pmc; struct chipset_power_state *ps = car_get_var_ptr(&power_state);
tcobase = pmc_tco_regs(); @@ -141,6 +145,10 @@ struct chipset_power_state *fill_power_state(void) ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
+ pmc = pmc_mmio_regs(); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + ps->prev_sleep_state = prev_sleep_state(ps);
dump_power_state(ps);