[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.
......................................................................

src/soc/tigerlake: Define and use a Kconfig for no of USB ports.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/fsp_params_tgl.c
3 files changed, 14 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index cef1fd0..f50e40e 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -156,6 +156,16 @@
    default 3 if SOC_INTEL_JASPERLAKE
    default 4 if SOC_INTEL_TIGERLAKE

+config SOC_INTEL_USB2_DEV_MAX
+       int
+       default 8 if SOC_INTEL_JASPERLAKE
+       default 10 if SOC_INTEL_TIGERLAKE
+
+config SOC_INTEL_USB3_DEV_MAX
+       int
+       default 6 if SOC_INTEL_JASPERLAKE
+       default 4 if SOC_INTEL_TIGERLAKE
+
 config SOC_INTEL_I2C_DEV_MAX
    int
    default 6
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c
index 8046b2e..d5d623b 100644
--- a/src/soc/intel/tigerlake/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/fsp_params_jsl.c
@@ -106,7 +106,7 @@
    memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

/* USB configuration */
-	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+	for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {

params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
    	params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
@@ -116,7 +116,7 @@
    	params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
    }

-	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+	for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {

params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
    	params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..f027ee0 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -89,7 +89,7 @@
    	params->IomTypeCPortPadCfg[i] = 0x09000000;

/* USB */
-	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+	for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {
    	params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
    	params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
    	params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
@@ -98,7 +98,7 @@
    	params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
    }

-	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+	for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {
    	params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
    	params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
    	if (config->usb3_ports[i].tx_de_emp) {