[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()

[Furquan Shaikh (Code Review)]

Hello Raul Rangel, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41247

to look at the new patch set (#2).

Change subject: soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()
......................................................................

soc/amd/common/block/lpc: Add lpc_initialize_spi_bar()

This change adds helper function lpc_initialize_spi_bar() which sets
MMIO base for SPI controller and ROM enable bits. This is equivalent
to renaming of lpc_set_spibase() to
lpc_initialize_spi_bar(). Additionally, lpc_set_spibase() is updated
to just set the MMIO base for SPI controller. This split is done to
allow setting of MMIO base independent of ROM enable bits. On
platforms like Picasso, eSPI base is determined by the same register
and hence eSPI can set the BAR without having to touch the enable
bits.

Signed-off-by: Furquan Shaikh 
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
M src/soc/amd/picasso/southbridge.c
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 36 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/41247/2