Hello Aaron Durbin, Patrick Rudolph, Paul Menzel, Duncan Laurie, Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31614
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init ......................................................................
soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init
PMC initialization on Cannon Lake happens earlier in the boot sequence than other SoCs because FSP-Silicon init hides PMC from PCI bus. As ACPI disabling was done as part of PMC init, it was being called earlier than what other SoCs do. This resulted in a different order of events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it ended up clearing EC events (which happens as part of ACPI disabling in SMM) before logging any events of interest that happen during mainboard initialization.
This change moves the call to disable ACPI to pmc_soc_init just like other SoCs to keep the order of events more aligned.
BUG=b:126016602 TEST=Verified that EC panic event gets logged to eventlog correctly.
Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/pmc.c 1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31614/2