Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50624 )
Change subject: [WIP] soc/amd/cezanne: add partial data fabric setup ......................................................................
[WIP] soc/amd/cezanne: add partial data fabric setup
This isn't meant to be merged in the current state.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/chip.c A src/soc/amd/cezanne/data_fabric.c A src/soc/amd/cezanne/include/soc/data_fabric.h 4 files changed, 146 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/50624/1
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index e6bccc3..ab36028 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -26,6 +26,7 @@
ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index ffd56de..78a4e33 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -2,6 +2,7 @@
#include <device/device.h> #include <fsp/api.h> +#include <soc/data_fabric.h> #include <soc/southbridge.h> #include <types.h> #include "chip.h" @@ -53,6 +54,8 @@ { fsp_silicon_init();
+ data_fabric_set_mmio_np(); + fch_init(chip_info); }
diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c new file mode 100644 index 0000000..788bc6f --- /dev/null +++ b/src/soc/amd/cezanne/data_fabric.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/data_fabric.h> +#include <console/console.h> +#include <cpu/x86/lapic_def.h> +#include <soc/data_fabric.h> +#include <soc/iomap.h> +#include <types.h> + +static void disable_mmio_reg(unsigned int reg) +{ + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), + IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), 0); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), 0); +} + +static bool is_mmio_reg_disabled(unsigned int reg) +{ + uint32_t val = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(reg)); + return !(val & ((MMIO_WE | MMIO_RE))); +} + +static int find_unused_mmio_reg(void) +{ + unsigned int i; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + if (is_mmio_reg_disabled(i)) + return i; + } + return -1; +} + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + if (!(ctrl & (MMIO_WE | MMIO_RE))) + continue; /* not enabled */ + + base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + reg = find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, + "Error: Not enough NB MMIO routing registers\n"); + continue; + } + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + else + data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); + } + + reg = find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + return; + } + + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE + | MMIO_RE); +} diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h new file mode 100644 index 0000000..1a88bba --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H + +#include <types.h> + +/* D18F0 - Fabric Configuration registers */ +#define IOMS0_FABRIC_ID 9 + +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 +#define MMIO_NP BIT(12) +#define MMIO_DST_FABRIC_ID_SHIFT 4 +#define MMIO_WE BIT(1) +#define MMIO_RE BIT(0) +#define NUM_NB_MMIO_REGS 8 +#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) +#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) +#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) + +void data_fabric_set_mmio_np(void); + +#endif /* AMD_PICASSO_DATA_FABRIC_H */