[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83325?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................

soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs

TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos

TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20

Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/gnr/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
M src/soc/intel/xeon_sp/spr/romstage.c
5 files changed, 152 insertions(+), 169 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83325/5