[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Shaunak Saha (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42557

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
......................................................................

soc/intel/tigerlake: Disable CPU PCIE in FSP

In TGL soc we have PCH and CPU side Pcie support. For
Volteer and TGL RVP we are not using CPU side Pcie. This
patch disables the initialization of CPU Pcie and hence
saves  ~30ms in FspSiliconInit.

BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure
the boot time. FspSilicontInit time is reduced by ~30ms with
this patch.

Signed-off-by: Shaunak Saha 
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/2