Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41690 )
Change subject: mb/ocp/deltalake: Config PCH PCIe ports ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41690/8/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/41690/8/src/mainboard/ocp/deltalake... PS8, Line 72: for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { : mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = : dl_pch_pci_port[index].ForceEnable; : mupd->FspmConfig.PchPciePortLinkSpeed[dl_pch_pci_port[index].PortIndex] = : dl_pch_pci_port[index].PortLinkSpeed; : }
Hi Christian, for DeltaLake, the PCH PCIe configuration is same for all SKUs. […]
What you are doing here is setting the FspmConfig options in the mainboard folder. The "normal" way to do so is bringing this code to soc/intel/xeon_sp/{skx,cpx}/romstage.c where you parse the soc config and write the FSPM UPDs. Therefore you would need to add chip config options and the hand over the values via devicetree. Something like CB:42440 . I don't understand why this should belong into the mb code.