Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel: Add PchPmPwrCycDur to chip options ......................................................................
soc/intel: Add PchPmPwrCycDur to chip options
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur from devicetree. The UPD determines the minimum time a platform will stay in reset during host partition reset with power cycle or global reset.
TEST=Verified on hatch. Yet to verify on Puff
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42440/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4b48a21..dca9339 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -312,6 +312,15 @@ uint8_t PchPmSlpAMinAssert;
/* + * Reset Power Cycle Duration + * 1 = 1sec + * 2 = 2sec + * 3 = 3sec + * 4 = 4sec (default) + */ + uint8_t PchPmPwrCycDur; + + /* * SerialIO device mode selection: * * Device index: diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a3b5588..3eb0dfb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -411,6 +411,8 @@ params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; if (config->PchPmSlpAMinAssert) params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + if (config->PchPmPwrCycDur) + params->PchPmPwrCycDur = config->PchPmPwrCycDur;
/* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset;