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Change subject: mb/google/brya: Enable CSE telemetry for ADL-N
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79768/comment/751f6756_d4766746 :
PS1, Line 9: Enable CSE telemetry for ADL-N.
> redundant line. […]
Acknowledged
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Hello Eran Mitrani, Eric Lai, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Enable CSE telemetry for ADL-N
......................................................................
mb/google/brya: Enable CSE telemetry for ADL-N
BUG=none
TEST=Verify CSE telemetry data in boot time data on Yahiko.
Before:
```
yahiko-rev9 ~ # cbmem -t
71 entries total:
0:1st timestamp 197,583 (0)
```
After:
```
yahiko-rev9 ~ # cbmem -t
76 entries total:
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 49,000
945:CSE started to handle ICC configuration 49,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 51,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 168,000 (117,000)
0:1st timestamp 195,861 (27,861)
```
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I3f90d0462cb766655bf8e59a90bc550ceefb2256
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79768/2
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Change subject: soc/intel/xeon_sp: Locate PCI devices by Ven/Dev ID
......................................................................
soc/intel/xeon_sp: Locate PCI devices by Ven/Dev ID
Since the ACPI code is looking for VtdBars, that only appear on
Vtd devices, search for the Vtd device in devicetree.
With the previous commit the VtdBar is now exposed as a resource
on the Vtd device and thus can easily be accessed and used.
Drop the FSP HOB parsing and just use coreboot native functions.
Allows the code to work with multiple PCI segment groups.
Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 43 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/80551/1
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 75b281b..14dfb9e 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -10,7 +10,9 @@
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pciexp.h>
+#include <device/pci_ids.h>
#include <soc/acpi.h>
+#include <soc/chip_common.h>
#include <soc/hest.h>
#include <soc/iomap.h>
#include <soc/numa.h>
@@ -18,7 +20,6 @@
#include <soc/soc_util.h>
#include <soc/util.h>
#include <intelblocks/p2sb.h>
-
#include "chip.h"
/* NUMA related ACPI table generation. SRAT, SLIT, etc */
@@ -384,26 +385,39 @@
static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob)
{
+ struct device *child, *dev;
+ struct resource *resource;
+
+ /*
+ * The assumption made here is that the host bridges on a socket share the
+ * PCI segment group and thus only one ATSR header needs to be emitted for
+ * a single socket.
+ * This is easier than to sort the host bridges by PCI segment group first
+ * and then generate one ATSR header for every new segment.
+ */
for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
if (!soc_cpu_is_enabled(socket))
continue;
iio++;
-
- uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment;
unsigned long tmp = current;
bool first = true;
- IIO_RESOURCE_INSTANCE iio_resource =
- hob->PlatformData.IIO_resource[socket];
- for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) {
- uint32_t bus = iio_resource.StackRes[stack].BusBase;
- uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
- if (!vtd_base)
+ dev = NULL;
+ while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
+ /* Only add devices for the current socket */
+ if (iio_pci_domain_socket_from_dev(dev) != socket)
continue;
- uint64_t vtd_mmio_cap = read64p(vtd_base + VTD_EXT_CAP_LOW);
- printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, "
+ /* See if there is a resource with the appropriate index. */
+ resource = probe_resource(dev, VTD_BAR_CSR);
+ if (!resource)
+ continue;
+ int stack = iio_pci_domain_stack_from_dev(dev);
+
+ uint64_t vtd_mmio_cap = read64(res2mmio(resource, VTD_EXT_CAP_LOW, 0));
+ printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: %p, "
"vtd_mmio_cap: 0x%llx\n",
- __func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
+ __func__, socket, stack, dev->upstream->secondary,
+ res2mmio(resource, 0, 0), vtd_mmio_cap);
// ATSR is applicable only for platform supporting device IOTLBs
// through the VT-d extended capability register
@@ -411,17 +425,15 @@
if ((vtd_mmio_cap & 0x4) == 0) // BIT 2
continue;
- if (bus == 0)
+ if (dev->upstream->secondary == 0 && dev->upstream->segment_group == 0)
continue;
- struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0));
- while (dev) {
- if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
- current +=
+ for (child = dev->upstream->children; child; child = child->sibling) {
+ if ((child->hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
+ continue;
+ current +=
acpi_create_dmar_ds_pci_br_for_port(
- current, dev, pcie_seg, true, &first);
-
- dev = dev->sibling;
+ current, child, child->upstream->segment_group, true, &first);
}
}
if (tmp != current)
@@ -465,24 +477,21 @@
static unsigned long acpi_create_rhsa(unsigned long current)
{
- const IIO_UDS *hob = get_iio_uds();
+ struct device *dev = NULL;
+ struct resource *resource;
+ int socket;
- for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
- if (!soc_cpu_is_enabled(socket))
+ while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
+ /* See if there is a resource with the appropriate index. */
+ resource = probe_resource(dev, VTD_BAR_CSR);
+ if (!resource)
continue;
- iio++;
- IIO_RESOURCE_INSTANCE iio_resource =
- hob->PlatformData.IIO_resource[socket];
- for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) {
- uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
- if (!vtd_base)
- continue;
+ socket = iio_pci_domain_socket_from_dev(dev);
- printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, "
- "Proximity Domain: 0x%x\n", vtd_base, socket);
- current += acpi_create_dmar_rhsa(current, vtd_base, socket);
- }
+ printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: %p, "
+ "Proximity Domain: 0x%x\n", res2mmio(resource, 0, 0), socket);
+ current += acpi_create_dmar_rhsa(current, (uintptr_t)res2mmio(resource, 0, 0), socket);
}
return current;
--
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Change subject: soc/intel/xeon_sp: Print device path when reporting resources
......................................................................
soc/intel/xeon_sp: Print device path when reporting resources
As there are multiple Vtd devices, print the path of each when reporting
resource registers.
Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80549/1
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 96855ed..56c768d 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -111,8 +111,8 @@
if (!memory_map[i].description)
continue;
- printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
- memory_map[i].description, values[i]);
+ printk(BIOS_DEBUG, "%s: MC MAP: %s: 0x%llx\n",
+ dev_path(dev), memory_map[i].description, values[i]);
}
}
--
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The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add helper functions
......................................................................
soc/intel/xeon_sp: Add helper functions
Provide a helper function to locate PCI devices on a given socket
by their PCI vendor and device IDs and functions to return
information about the current device, like the corresponding stack
and socket.
This becomes handy when locating devices and generating ACPI code.
Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/80094/13
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Change subject: soc/intel/xeon_sp/spr: Don't leak memory
......................................................................
soc/intel/xeon_sp/spr: Don't leak memory
Only call fill_pds() once to prevent leaking memory. Previously it was
called for every active stack on every socket.
Only call dump_pds() once to prevent spamming the console with the same
information.
Drop the return value since it's always returning success.
Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/include/soc/numa.h
M src/soc/intel/xeon_sp/spr/numa.c
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/80547/1
diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h
index 6aaf172..aba3f09 100644
--- a/src/soc/intel/xeon_sp/include/soc/numa.h
+++ b/src/soc/intel/xeon_sp/include/soc/numa.h
@@ -54,7 +54,7 @@
extern struct proximity_domains pds;
void dump_pds(void);
-enum cb_err fill_pds(void);
+void fill_pds(void);
/*
* Return the total size of memory regions in generic initiator affinity
diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/spr/numa.c
index 169f4f8..23f52c6 100644
--- a/src/soc/intel/xeon_sp/spr/numa.c
+++ b/src/soc/intel/xeon_sp/spr/numa.c
@@ -25,7 +25,7 @@
}
}
-enum cb_err fill_pds(void)
+void fill_pds(void)
{
uint8_t num_sockets = soc_get_num_cpus();
uint8_t num_cxlnodes = get_cxl_node_count();
@@ -72,7 +72,7 @@
/* If there are no CXL nodes, we are done */
if (num_cxlnodes == 0)
- return CB_SUCCESS;
+ return;
/* There are CXL nodes, fill in generic initiator domain after the processors pds */
uint8_t skt_id, cxl_id;
@@ -98,8 +98,6 @@
}
}
}
-
- return CB_SUCCESS;
}
/*
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index de2d175..96855ed 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -329,11 +329,13 @@
int index = 0;
if (CONFIG(SOC_INTEL_HAS_CXL)) {
- /* Construct NUMA data structure. This is needed for CXL. */
- if (fill_pds() != CB_SUCCESS)
- pds.num_pds = 0;
-
- dump_pds();
+ static bool once;
+ if (!once) {
+ /* Construct NUMA data structure. This is needed for CXL. */
+ fill_pds();
+ dump_pds();
+ once = true;
+ }
}
/* Read standard PCI resources. */
--
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Change subject: soc/intel/xeon_sp/uncore: Don't print uninitialized memory
......................................................................
soc/intel/xeon_sp/uncore: Don't print uninitialized memory
The struct map_entry has two zero'd entries due to the ifdef
being used. Do not read those entries and do not print those
entries.
Fixes a NULL string being printed along as the vendor and device
ID of the PCI device.
Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80546/1
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index ddc6e82..de2d175 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -72,6 +72,11 @@
uint64_t value;
uint64_t mask;
+ if (!entry->reg) {
+ *result = 0;
+ return;
+ }
+
/* All registers are on a 1MiB granularity. */
mask = ((1ULL << entry->mask_bits) - 1);
mask = ~mask;
@@ -103,6 +108,9 @@
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+ if (!memory_map[i].description)
+ continue;
+
printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
memory_map[i].description, values[i]);
}
--
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80504?usp=email )
Change subject: soc/intel/alderlake: Remove CNVi assertions
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Patch Set 4: Code-Review-1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80504/comment/047ff5b4_a4fb74ea :
PS4, Line 12: This seems to make sense and allows us
: to enable CNVi bluetooth when necessary.
I'm confused about 'when necessary' here. Both enabling the CNVI device and cnvi_bt_core and cnvi_bt_audio_offload are done via devicetree configuration. Do you want to have some mechanism at runtime to change them? If not then this is a step in the wrong direction and I'd suggest using build-time assertions (static_assert) rather than runtime ones.
Patchset:
PS4:
I don't understand the rationale of weakening the asserts to just error message. Both config option and whether the device is enabled are known at compiletime, so making the assertion stronger, rather than weaker seems better?
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