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Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
@Arthur, i lost the CR+2 due to rebase, do you mind reviewing this CL once more.
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Hello Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80567?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.
This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.
Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/cpu.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/80567/3
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Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80567/comment/0d510aa5_f1c895c8 :
PS2, Line 10: indicate
> indicates
Acknowledged
https://review.coreboot.org/c/coreboot/+/80567/comment/993e1f1f_ecf35b02 :
PS2, Line 16: updated
> distributed/published
Acknowledged
https://review.coreboot.org/c/coreboot/+/80567/comment/4c4b55ad_9942d00e :
PS2, Line 9: This patch eliminates coreboot from loading microcode from
: RW CBFS (when the RO descriptor is locked, which indicate
: a fixed RO image) because the kernel can already patch the
: microcode on BSPs and APs while booting to OS.
:
: This may be a chance to lower the burden on the AP FW side
: because patching microcode on in-field devices is subject
: to firmware updates, which are rarely updated and, if
: required, must go through the firmware qualification testing
: procedure (which is costly, unlike kernel updates for ucode
: updates).
> Please use 72 characters per line.
Acknowledged
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Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80567/comment/b4a5ee5e_567667ce :
PS2, Line 10: indicate
indicates
https://review.coreboot.org/c/coreboot/+/80567/comment/32e09a25_ae0cf7b0 :
PS2, Line 16: updated
distributed/published
https://review.coreboot.org/c/coreboot/+/80567/comment/f62c7db2_227ac67c :
PS2, Line 9: This patch eliminates coreboot from loading microcode from
: RW CBFS (when the RO descriptor is locked, which indicate
: a fixed RO image) because the kernel can already patch the
: microcode on BSPs and APs while booting to OS.
:
: This may be a chance to lower the burden on the AP FW side
: because patching microcode on in-field devices is subject
: to firmware updates, which are rarely updated and, if
: required, must go through the firmware qualification testing
: procedure (which is costly, unlike kernel updates for ucode
: updates).
Please use 72 characters per line.
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Change subject: mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMER
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/purism/librem_cnl/var/librem_mini: Set RTC register defaults
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Patch Set 2: Code-Review+1
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Change subject: mb/purism_librem_cnl/var/*: Drop redundant entries in overridetrees
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Patch Set 2: Code-Review+2
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Change subject: mb/purism/librem_cnl: Drop devicetree entries identical to chipset.cb
......................................................................
Patch Set 1: Code-Review+2
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Change subject: device/pnp_device: Skip init on disabled functions
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80598/comment/0645c673_978ce285 :
PS1, Line 9: explcitly
typo: explicitly
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Change subject: mb/google/rex/variants/deku: correct GPIO F19 and F20 configuration
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80569/comment/b0f1671f_511715ae :
PS2, Line 7: correct GPIO F19 and F20 configuration
Maybe:
> Correct GPIO F19/F20 to not connected
https://review.coreboot.org/c/coreboot/+/80569/comment/c4dec3e8_5beb4237 :
PS2, Line 9: GPP_F19 and GPP_F20 were set incorrectly previously.
: Changed to not connected.
: This CL corrects these settings according to schematics.
Please do not wrap lines, just because the sentence ends.
This can be shortened:
> GPP_F19 and GPP_F20 are set incorrectly. Change them to not connected according to schematics.
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