coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[M] Change in coreboot[master]: [NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure I...
by Johnny Lin (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Tim Chu. Hello Arthur Heymans, Christian Walter, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76185?usp=email to look at the new patch set (#2). Change subject: [NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard ...................................................................... [NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard Attempt to deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now. Each mainboard needs to have a "include/sprsp_mb_iio.h" which defines its mb_iio_table and mb_iio_bifur for IIO configurations, and soc common code can configure IIO UPD from them. This change removes initializing below UPD default non zero values, so mainboard needs to make sure they are defined in its mb_iio_table: PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */ Not tested yet. Need to modfiy and verify other SPR mainboards, and use DISPLAY_UPD_IIO_DATA to compare the results. Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- R src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h M src/mainboard/intel/archercity_crb/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/romstage.c 4 files changed, 79 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76185/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Gerrit-Change-Number: 76185 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: {mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from...
by Johnny Lin (Code Review) 30 Jun '23

30 Jun '23

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76185?usp=email ) Change subject: {mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard ...................................................................... {mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard Attempt to deduplicate mainboard mainboard_config_iio since there are a few SPR-SP mainboards now. Each mainboard needs to have a "include/sprsp_mb_iio.h" which defines its mb_iio_table and mb_iio_bifur for IIO configurations, and soc common code can configure IIO UPD from them. This change removes initializing below UPD default non zero values, so mainboard needs to make sure they are defined in its mb_iio_table: PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */ Not thoroughly tested yet. Need to modfiy and verify other SPR mainboards, and use DISPLAY_UPD_IIO_DATA to compare the results. Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- R src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h M src/mainboard/intel/archercity_crb/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.inc M src/soc/intel/xeon_sp/spr/romstage.c 4 files changed, 79 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76185/1 diff --git a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h b/src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h similarity index 87% rename from src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h rename to src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h index 2dcf6c9..e10be76 100644 --- a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h +++ b/src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef _SPRSP_AC_IIO_H_ -#define _SPRSP_AC_IIO_H_ +#ifndef _SPRSP_MB_IIO_H_ +#define _SPRSP_MB_IIO_H_ #include <defs_iio.h> @@ -35,10 +35,13 @@ .DfxDnTxPresetGen3 = 0xFF \ } +#define IIO_PORT_SETTINGS (1 + 5 * 8) + /* * Standard ArcherCity IIO PCIe Port Table */ -static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = { +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { + { /* DMI port: array index 0 */ CFG_UPD_PCIE_PORT(0, 0, 0), /* IOU0 (PE0): array index 1 ~ 8 */ @@ -86,10 +89,8 @@ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */ CFG_UPD_PCIE_PORT(1, 0, 0), - /* ArcherCity doesn't use IOU5 ~ IOU6. */ -}; - -static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = { + }, + { /* DMI port: array index 0 */ CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU0 (PE0): array index 1 ~ 8 */ @@ -137,6 +138,23 @@ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */ CFG_UPD_PCIE_PORT(1, 0, 0), - /* ArcherCity doesn't use IOU5 ~ IOU6. */ + }, }; -#endif /* _SPRSP_CL_IIO_H_ */ + +static const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5] = { + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_x4x4x4x4, + IIO_BIFURCATE_x4x4x4x4, + }, + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_x4x4x4x4, + IIO_BIFURCATE_x4x4x4x4, + }, +}; +#endif /* _SPRSP_MB_IIO_H_ */ diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 582fa50..340af0d 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -7,7 +7,7 @@ #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> -#include <sprsp_ac_iio.h> +#include <sprsp_mb_iio.h> void mainboard_ewl_check(void) { @@ -16,59 +16,6 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { - int port; - - UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; - - /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ - for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) { - PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP; - PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP; - PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable; - PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE; - PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload; - PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed; - PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3; - } - /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ - for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[0].PEXPHIDE[port] = 1; - PciePortConfig[0].HidePEXPMenu[port] = 1; - } - PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; - PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; - - PciePortConfig[0].PcieGlobalAspm = 0x1; - PciePortConfig[0].PcieMaxReadRequestSize = 0x5; - - /* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ - for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) { - PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP; - PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP; - PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable; - PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE; - PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload; - PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed; - PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3; - } - /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ - for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[1].PEXPHIDE[port] = 1; - PciePortConfig[1].HidePEXPMenu[port] = 1; - } - PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; - PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; - PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; - - PciePortConfig[1].PcieGlobalAspm = 0x1; - PciePortConfig[1].PcieMaxReadRequestSize = 0x5; - /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); diff --git a/src/soc/intel/xeon_sp/spr/Makefile.inc b/src/soc/intel/xeon_sp/spr/Makefile.inc index 3e4f9cd..0703542 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.inc +++ b/src/soc/intel/xeon_sp/spr/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c -CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr \ + -I$(src)/mainboard/$(MAINBOARDDIR)/include endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 8004730..60b21ce 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -19,11 +19,11 @@ #include <string.h> #include <soc/soc_util.h> #include <soc/ddr.h> +#include <sprsp_mb_iio.h> #include "chip.h" /* Initialize to all zero first */ -static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET]; static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET]; void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -113,22 +113,55 @@ } } -/* Initialize non-zero default UPD values for IIO */ -static void initialize_iio_upd(FSPM_UPD *mupd) +static void soc_config_iio_from_mb(FSPM_UPD *mupd) { - unsigned int port, socket; + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig; + int port, socket; - mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; - mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; - UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)spr_iio_bifur_table; + PciePortConfig = + (UPD_IIO_PCIE_PORT_CONFIG *)(UINTN)mupd->FspmConfig.IioPcieConfigTablePtr; + mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET; /* Set by mainboard */ - /* Initialize non-zero default UPD values */ - for (socket = 0; socket < MAX_SOCKET; socket++) { - for (port = 0; port < MAX_IIO_PORTS_PER_SOCKET; port++) { - PciePortConfig[socket].PcieMaxPayload[port] = 0x7; /* Auto */ - PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */ + for (socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { + + /* Only configures DMI, IOU0 ~ IOU4, the rest will be + * left zero */ + for (port = 0; port < ARRAY_SIZE(mb_iio_table[socket]); port++) { + const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg = + &mb_iio_table[socket][port]; + PciePortConfig[socket].SLOTIMP[port] = port_cfg->SLOTIMP; + PciePortConfig[socket].SLOTPSP[port] = port_cfg->SLOTPSP; + PciePortConfig[socket].SLOTHPCAP[port] = port_cfg->SLOTHPCAP; + PciePortConfig[socket].SLOTHPSUP[port] = port_cfg->SLOTHPSUP; + PciePortConfig[socket].SLOTSPLS[port] = port_cfg->SLOTSPLS; + PciePortConfig[socket].SLOTSPLV[port] = port_cfg->SLOTSPLV; + PciePortConfig[socket].VppAddress[port] = port_cfg->VppAddress; + PciePortConfig[socket].SLOTPIP[port] = port_cfg->SLOTPIP; + PciePortConfig[socket].SLOTAIP[port] = port_cfg->SLOTAIP; + PciePortConfig[socket].SLOTMRLSP[port] = port_cfg->SLOTMRLSP; + PciePortConfig[socket].SLOTPCP[port] = port_cfg->SLOTPCP; + PciePortConfig[socket].SLOTABP[port] = port_cfg->SLOTABP; + PciePortConfig[socket].VppEnabled[port] = port_cfg->VppEnabled; + PciePortConfig[socket].VppPort[port] = port_cfg->VppPort; + PciePortConfig[socket].MuxAddress[port] = port_cfg->MuxAddress; + PciePortConfig[socket].PciePortEnable[port] = port_cfg->PciePortEnable; + PciePortConfig[socket].PEXPHIDE[port] = port_cfg->PEXPHIDE; + PciePortConfig[socket].PcieHotPlugOnPort[port] = port_cfg->PcieHotPlugOnPort; + PciePortConfig[socket].PcieMaxPayload[port] = port_cfg->PcieMaxPayload; + PciePortConfig[socket].PciePortLinkSpeed[port] = port_cfg->PciePortLinkSpeed; + PciePortConfig[socket].DfxDnTxPresetGen3[port] = port_cfg->DfxDnTxPresetGen3; } + + /* Socket IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(mb_iio_table[socket]); port < MAX_IIO_PORTS_PER_SOCKET; + port++) { + PciePortConfig[socket].PEXPHIDE[port] = 1; + PciePortConfig[socket].HidePEXPMenu[port] = 1; + } + /* Configure IOU0 ~ IOU4 bifurcation */ + for (port = 0; port < 5; port++) + PciePortConfig[socket].ConfigIOU[port] = mb_iio_bifur[socket][port]; + PciePortConfig[socket].PcieGlobalAspm = 0x1; /* Enable ASPM */ PciePortConfig[socket].PcieMaxReadRequestSize = 0x5; } @@ -136,7 +169,6 @@ mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list; mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list; - for (port = 0; port < MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; port++) DeEmphasisConfig[port] = 0x1; } @@ -198,7 +230,9 @@ /* Set some common UPDs from VPD, mainboard can still override them if needed */ if (CONFIG(VPD)) config_upd_from_vpd(mupd); - initialize_iio_upd(mupd); + /* soc configures IIO UPD from mainboard defined mb_iio_table and mb_iio_bifur, + mainboard can still furthur overwrite in its mainboard_config_iio. */ + soc_config_iio_from_mb(mupd); mainboard_memory_init_params(mupd); if (CONFIG(ENABLE_IO_MARGINING)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/76185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9 Gerrit-Change-Number: 76185 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: acpi/acpi.c: Reduce boilerplate
by Arthur Heymans (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Elyes Haouas, Felix Singer, Kyösti Mälkki, Lance Zhao, Tim Wawrzynczak. Hello Elyes Haouas, Felix Singer, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76127?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi/acpi.c: Reduce boilerplate ...................................................................... acpi/acpi.c: Reduce boilerplate Adding tables to R/XSDT, aligning current pointer, computing checksum is a lot of boilerplate that needs to be done for each table. TESTED on foxconn/g41. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d --- M src/acpi/acpi.c 1 file changed, 118 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/76127/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d Gerrit-Change-Number: 76127 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: acpi/acpi.c: Reduce boilerplate
by Arthur Heymans (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Elyes Haouas, Felix Singer, Kyösti Mälkki, Lance Zhao, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76127?usp=email ) Change subject: acpi/acpi.c: Reduce boilerplate ...................................................................... Patch Set 3: (3 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76127/comment/aa2df4b2_797ab0c2 : PS3, Line 1875: acpi_header_t *dsdt_file = (acpi_header_t *)(*(acpi_header_t **)(dsdt_file_arg)); > Is there a double cast? Done https://review.coreboot.org/c/coreboot/+/76127/comment/01e141fa_b1ac4fcb : PS3, Line 1904: * cbfs_unmap() uses mem_pool_free() which works correctly only > This reversed order is no longer honoured? Done https://review.coreboot.org/c/coreboot/+/76127/comment/fa204bf7_2dfd413b : PS3, Line 1914: acpi_header_t *slic_file = (acpi_header_t *)(*(acpi_header_t **)slic_file_arg); > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d Gerrit-Change-Number: 76127 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 30 Jun 2023 08:26:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5
by Eric Lai (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Leo Chou, Paul Menzel, Shou-Chieh Hsu, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75900?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5 ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75900/comment/05894739_d0a3f01d : PS8, Line 9: Update SX9324 register settings based on tuning value Please fit the 72 char per line. Also you should update the comment as you replied to Paul. -- To view, visit https://review.coreboot.org/c/coreboot/+/75900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Gerrit-Change-Number: 75900 Gerrit-PatchSet: 8 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 08:16:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/rex/var/screebo:Fix touchsreen thd:dat test fail
by Eric Lai (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, zhongtian wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76190?usp=email ) Change subject: mb/google/rex/var/screebo:Fix touchsreen thd:dat test fail ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: please add I2C timing into comment. Also the delta for the timing. -- To view, visit https://review.coreboot.org/c/coreboot/+/76190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae Gerrit-Change-Number: 76190 Gerrit-PatchSet: 1 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 08:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/rex/var/screebo:Fix touchpad timing
by Eric Lai (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, zhongtian wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76169?usp=email ) Change subject: mb/google/rex/var/screebo:Fix touchpad timing ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: please add I2C into the comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/76169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739 Gerrit-Change-Number: 76169 Gerrit-PatchSet: 2 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 08:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Yunlong Jia (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Derek Huang, Felix Singer, Henry Sun, Tarun Tuli. Yunlong Jia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 6: (6 comments) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/7acc3cf9_01fbfac8 : PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN : : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 > I just don't know where is the best place to put it. […] Done https://review.coreboot.org/c/coreboot/+/76013/comment/ba8e149d_af0c9c2d : PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN : : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 : > I'm Sorry for commenting late. […] Done File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/d6ba56db_ca6f8314 : PS3, Line 168: probed > We see that some places use "detect" and "probed", so what is the difference between the two? We don't have this `detect`. https://review.coreboot.org/c/coreboot/+/76013/comment/67593f13_80f6d755 : PS3, Line 176: device i2c 0x10 on end > Do you mean that we need to "stop_gpio" on the Touchscreen at a certain time? we don't think we need it． File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/2e6d6f03_d9977cff : PS4, Line 332: register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC > > trailing whitespace […] Done https://review.coreboot.org/c/coreboot/+/76013/comment/d3db295f_398f97f3 : PS4, Line 335: register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 > add an empty line here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 6 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 08:03:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Comment-In-Reply-To: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: acpi: Add SPCR table
by Eric Lai (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Arthur Heymans. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: acpi: Add SPCR table ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > Also have issue [ 1. […] The hang up issue always found on Rex. If remove the console=... from boot parameter. -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 30 Jun 2023 07:59:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Felix Singer (Code Review) 30 Jun '23

30 Jun '23

Attention is currently required from: Derek Huang, Henry Sun, Tarun Tuli, Yunlong Jia. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/0b21e54f_1d99752e : PS4, Line 332: register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC > trailing whitespace Please fix. This will fix the CI error. https://review.coreboot.org/c/coreboot/+/76013/comment/1f1a5c4a_46b028d0 : PS4, Line 335: register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 add an empty line here -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 4 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Jun 2023 07:46:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023