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Change subject: mb/google/myst: Expand flashmap to 32 MB
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Patch Set 2:
(1 comment)
File src/mainboard/google/myst/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/75642/comment/d2240bfd_1704d6ba :
PS2, Line 1: 0xFE000000
I'd think we should just leave this as it is:
- Nothing can actually be mapped at this address
- The next revision of the board will use a 16 MiB ROM.
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Change subject: mb/google/myst/bootblock.c: Initialize spi flash
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Patch Set 1:
(1 comment)
File src/mainboard/google/myst/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75588/comment/fd6ad726_6efcdf6f :
PS1, Line 41: // b:285110121 - temp workaround is to add a dummy flash call
Can you add "TODO" so it's easier to grep for this?
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Change subject: mb/google/myst: Expand flashmap to 32 MB
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Change subject: mb/google/myst: Enable USB WWAN
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Patch Set 5: Code-Review+2
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Change subject: mb/google/myst: Enable USB WWAN
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Change subject: mb/google/myst: Enable fingerprint on UART
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Patch Set 3: Code-Review+2
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Change subject: mb/google/myst: Enable fingerprint on UART
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Patch Set 3:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75629/comment/125d35ae_340ffb36 :
PS3, Line 71: PAD_GPO(GPIO_40, LOW),
> Micheal said we should keep it low durning boot. You can check the chat.
If that actually adds a delay to the boot sequence, it's working directly against our boot time optimization. I think we need to design a method of switching GPIOs at appropriate times instead of using delays.
I don't think this question should hold up this patch though.
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Change subject: drivers/spi/spi_flash.c: Print the flash ID when find_match fails
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Change subject: drivers/spi/winbond.c: Add W25Q256JW_DTR part
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Change subject: mb/google/myst/bootblock.c: Initialize spi flash
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