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Change subject: mb/google/brya/var/nereid: Add WLAN power sequence
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
We actually need EN to be pulled low for longer to fully discharge the rail, so instead drive EN high in romstage and release RST in ramstage.
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Hello Sam McNally, Reka Norman, build bot (Jenkins), Kangheui Won, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63368
to look at the new patch set (#3).
Change subject: mb/google/brya/var/nereid: Add WLAN power sequence
......................................................................
mb/google/brya/var/nereid: Add WLAN power sequence
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
in S3.
- During warm reboot, if we only assert RST without pulling the power
low, then the kernel crashes.
As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low in bootblock and high in romstage to
make sure it goes low during warm reboot.
BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.
Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman(a)google.com>
---
M src/mainboard/google/brya/variants/nereid/gpio.c
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63368/3
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63182 )
Change subject: soc/intel/common/cse: Implementing CSE EOP command asynchronously
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/63182/comment/2b06e974_7b121b86
PS3, Line 347: return handle_cse_eop_result(CSE_CMD_RESULT_ERROR);
Hi Subrata. Will there be a case where we end up going to recovery because CSE took more time for processing and we didn't get the CSE_CMD_EOP_RECEIVED in boot state ?
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Change subject: [RFC] Replace some ENV_ROMSTAGE conditionals
......................................................................
Patch Set 1: Code-Review+1
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Change subject: Factor TI50/CR50 config
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hmmm... okay, let's step back for a moment and try to look at the big picture. […]
It is worth a try, but it will be an involved refactoring.
Currently, I see both CRB_TPM and MAINBOARD_HAS_CRB_TPM in Kconfig. I am not sure how they are used differently, maybe the latter declares that the support exist, and the former can be used to actually enable it in coreboot. I support NO_TPM/TPM1/TPM2 could be used to declare whether we want to use the feature, and supersede CRB_TPM.
As I see it, I would end up with the following Kconfigs:
SPI_TPM
I2C_TPM
CRB_TPM
LPC_TPM
TPM_ATMEL
TPM_GOOGLE_CR50
TPM_GOOGLE_TI50
TPM_GENERIC (maybe absence of any of the above implies this)
MAINBOARD_HAS_TPM1
MAINBOARD_HAS_TPM2
The below are the ones which it makes sense for an end-user of a particular board to modify, they take their default from the above two:
TPM1
TPM2
NO_TPM
It will be a major refactoring, and I an worried that it will be hard for me to verify that I am not accidentally changing something unintended for an existing board.
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Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Arthur, do you think this is something that could gelp bootblock+romstage combo?
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Change subject: mb/google/brya/var/nereid: Enable pen garage
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> did you also test wake from S0ix?
Not yet. Sam, could you test this? (The pen garage on my nereid seems broken.)
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Change subject: Revert "soc/intel/alderlake: Use Kconfigs for Descriptor Region"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Arthur, do you mind if we rebase these on top of CB:63365 ? I'm happy to do it.
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Change subject: amdfwtool: Add a flag to record the second gen instead of romsig
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/63344/comment/1beeb85a_28b40b30
PS3, Line 1387: if (cb_config->second_gen) {
i think this has the logic backwards since EFS_SECOND_GEN is defined as 0.
at least for me it would make the code less error-prone if cb_config->second_gen was a bool and EFS_SECOND_GEN and EFS_BEFORE_SECOND_GEN would only be used in this function for writing amd_romsig->efs_gen.gen, but not for cb_config->second_gen
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Change subject: soc/intel/alderlake: Add support to update descriptor at runtime
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/bootblock/update_descriptor.c:
https://review.coreboot.org/c/coreboot/+/63365/comment/d5154294_1f4a7d3a
PS5, Line 42: CONFIG_SI_DESC_REGION_SZ
> re: these Kconfigs, see https://review.coreboot. […]
Thanks for pointing that out. We can rebase those cleanup CLs on top of this.
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