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Change subject: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63562/comment/dc852860_a86ae2c3
PS2, Line 9: Configure lcnt and hcnt directly to give the required frequency, tHIGH
> okay, just want to remind if too close too 400, different board may over 400. […]
Thanks, I wasn't aware that this was a consideration. I'll double check with our hardware engineer and update this if needed.
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Change subject: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt
......................................................................
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https://review.coreboot.org/c/coreboot/+/63562/comment/4192c7ab_6c9c8df4
PS2, Line 9: Configure lcnt and hcnt directly to give the required frequency, tHIGH
> I think they're all in the range 390 - 400 KHz. […]
okay, just want to remind if too close too 400, different board may over 400. Better to keep close to 390.
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Change subject: mb/google/brya: Create craask variant
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Change subject: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt
......................................................................
Patch Set 2:
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Commit Message:
https://review.coreboot.org/c/coreboot/+/63562/comment/9180305b_59292a06
PS2, Line 9: Configure lcnt and hcnt directly to give the required frequency, tHIGH
> Could you list the frequency for each bus after tuning?
I think they're all in the range 390 - 400 KHz. Is that enough information, or do you want exact numbers on each bus?
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Change subject: mb/google/brya: Add missing parameter name to variant_generate_s0ix_hook
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Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcnt
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63562/comment/76f5dcc0_691d4f56
PS2, Line 9: Configure lcnt and hcnt directly to give the required frequency, tHIGH
Could you list the frequency for each bus after tuning?
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Change subject: soc/intel/common: Enable rom cache on all CPU threads
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> > I'm not sure if i get Arthur's question. […]
sorry, i was busy on other P0 tasks, so i haven't yet tried.
i think technically that should work.
run_ap_work->(read_callback(&ap_callbacks[i]) == NULL) should do the work.
i will find some time to try this .
thank you
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Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Subrata Banik, Jonathan Zhang, Ravishankar Sarawadi, Johnny Lin, Christian Walter, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Michael Niewöhner, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63472
to look at the new patch set (#13).
Change subject: soc/intel: Remove dmi.h
......................................................................
soc/intel: Remove dmi.h
Remove dmi.h as it's replaced with gpmr driver and update
old platforms for not using the header file.
TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
---
M src/mainboard/ocp/deltalake/bootblock.c
M src/soc/intel/alderlake/bootblock/pch.c
M src/soc/intel/cannonlake/bootblock/pch.c
D src/soc/intel/common/block/include/intelblocks/dmi.h
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/elkhartlake/bootblock/pch.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/jasperlake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/xeon_sp/pch.c
11 files changed, 4 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63472/13
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Change subject: mb/google/brya/var/nereid: Enable OZ711LV2LN SD card controller
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Change subject: drivers/i2c/designware/dw_i2c: Remove unnecessary tabs in debug log
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Patch Set 2: Code-Review+2
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