Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68992 )
Change subject: device/dram: Add kconfig options for memory types
......................................................................
device/dram: Add kconfig options for memory types
Currently, we're building support for all memory types into every board,
and letting the linker remove anything that isn't needed. This is okay,
but it'd be nice to be able to build in just what's actually needed.
This change adds options to specify both what is used and what is not.
By doing it that way, the default values don't change, but platforms can
start removing support for memory types that are not needed. When all
platforms (SoCs, CPUs and/or Northbridge chips) specify what memory
types they support, the defaults on the options to use a particular
memory type can be set to no, and the options not to use a memory type
can be removed.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569
---
M src/device/Kconfig
A src/device/dram/Kconfig
M src/device/dram/Makefile.inc
3 files changed, 98 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68992/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index c0ba3d1..60ee047 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -953,4 +953,6 @@
help
Provides xHCI utility functions.
+source "src/device/dram/Kconfig"
+
endmenu
diff --git a/src/device/dram/Kconfig b/src/device/dram/Kconfig
new file mode 100644
index 0000000..7bb1dab
--- /dev/null
+++ b/src/device/dram/Kconfig
@@ -0,0 +1,57 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Short-term plan: Start adding 'USE_' and "NO_" options to each chip.
+#
+# Long-term plan: Every SoC or chipset should select the memory types they
+# use. When they all select their memory, the 'no_' options can be removed
+# and the defaults for all memory types can be set to n.
+
+config NO_DDR5
+ bool
+
+config NO_LPDDR4
+ bool
+
+config NO_DDR4
+ bool
+
+config NO_DDR3
+ bool
+
+config NO_DDR2
+ bool
+
+config USE_DDR5
+ bool
+ default n if NO_DDR5
+ default y
+ help
+ system supports DDR5 memory
+
+config USE_LPDDR4
+ bool
+ default n if NO_LPDDR4
+ default y
+ help
+ system supports LPDDR4 memory
+
+config USE_DDR4
+ bool
+ default n if NO_DDR4
+ default y
+ help
+ system supports DDR4 memory
+
+config USE_DDR3
+ bool
+ default n if NO_DDR3
+ default y
+ help
+ system supports DDR3 memory
+
+config USE_DDR2
+ bool
+ default n if NO_DDR2
+ default y
+ help
+ system supports DDR2 memory
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 31dfb91..fc472ea 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1,3 +1,18 @@
-romstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c
-ramstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c spd.c
+romstage-y += ddr_common.c
+ramstage-y += ddr_common.c spd.c
+
+romstage-$(CONFIG_USE_DDR5) += ddr5.c
+ramstage-$(CONFIG_USE_DDR5) += ddr5.c
+
+romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
+ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
+
+romstage-$(CONFIG_USE_DDR4) += ddr4.c
+ramstage-$(CONFIG_USE_DDR4) += ddr4.c
+
+romstage-$(CONFIG_USE_DDR3) += ddr3.c
+ramstage-$(CONFIG_USE_DDR3) += ddr3.c
+
+romstage-$(CONFIG_USE_DDR2) += ddr2.c
+ramstage-$(CONFIG_USE_DDR2) += ddr2.c
--
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Gerrit-Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569
Gerrit-Change-Number: 68992
Gerrit-PatchSet: 1
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Arthur Heymans, Bill XIE, Jonathan Zhang, Eric Lai, Werner Zeh, Kyösti Mälkki.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65420 )
Change subject: allocator_v4: Use memranges only for toplevel
......................................................................
Patch Set 14:
(1 comment)
File src/device/resource_allocator_v4.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161688):
https://review.coreboot.org/c/coreboot/+/65420/comment/3814f52c_349c2647
PS14, Line 440: void assign_resource_cb(void *param, struct device *dev, struct resource *res)
open brace '{' following function definitions go on the next line
--
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Jonathan Zhang has uploaded a new patch set (#14) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/65420 )
Change subject: allocator_v4: Use memranges only for toplevel
......................................................................
allocator_v4: Use memranges only for toplevel
During phase 1 of the resource allocation we gather all the size
requirements. Starting from the leafs of our devicetree, we cal-
culate the requirements per bus, until we reach the resource do-
main.
However, because alignment plays a role, we can't just accumulate
the sizes of all resources on a bus. Instead, we already sort all
the resources per bus to predict their relative placement, inclu-
ding alignment gaps. Then, phase 2 has to perform the final allo-
cations with the exact same relative placement.
This patch introduces a very simple mechanism to avoid repeating
all the calculations: In phase 1, we note the relative `base` of
each resource on a bus. And after we allocated all the resources
directly below the domain in phase 2, we add the absolute `base`
of bridge resources to the relative `base` of child resources.
This saves most of the computational complexity in phase 2. How-
ever, with a shallow devicetree with most devices directly below
the domain, this won't have a measurable impact.
Example after phase 1:
domain
|
`-- bridge #0
| res #0, base 0x000000 (relative),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
After phase 2 allocation at the domain level (assuming res #0 got
0xa000000 assigned):
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
Now, all we need to do is to add the `base` of bridge resources
recursively. Starting with resources on the bus below bridge #0:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
And finally for resources on the bus below bridge #1:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0xa000000 (absolute),
size 8M, align 8M
Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/resource_allocator_v4.c
1 file changed, 260 insertions(+), 267 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/65420/14
--
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Jonathan Zhang has uploaded a new patch set (#13) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/65420 )
Change subject: allocator_v4: Use memranges only for toplevel
......................................................................
allocator_v4: Use memranges only for toplevel
During phase 1 of the resource allocation we gather all the size
requirements. Starting from the leafs of our devicetree, we cal-
culate the requirements per bus, until we reach the resource do-
main.
However, because alignment plays a role, we can't just accumulate
the sizes of all resources on a bus. Instead, we already sort all
the resources per bus to predict their relative placement, inclu-
ding alignment gaps. Then, phase 2 has to perform the final allo-
cations with the exact same relative placement.
This patch introduces a very simple mechanism to avoid repeating
all the calculations: In phase 1, we note the relative `base` of
each resource on a bus. And after we allocated all the resources
directly below the domain in phase 2, we add the absolute `base`
of bridge resources to the relative `base` of child resources.
This saves most of the computational complexity in phase 2. How-
ever, with a shallow devicetree with most devices directly below
the domain, this won't have a measurable impact.
Example after phase 1:
domain
|
`-- bridge #0
| res #0, base 0x000000 (relative),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
After phase 2 allocation at the domain level (assuming res #0 got
0xa000000 assigned):
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0x800000 (relative),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0x000000 (relative),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
Now, all we need to do is to add the `base` of bridge resources
recursively. Starting with resources on the bus below bridge #0:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0x000000 (relative),
size 8M, align 8M
And finally for resources on the bus below bridge #1:
domain
|
`-- bridge #0
| res #0, base 0xa000000 (absolute),
| size 12M, align 8M
|
|-- device #0
| res #1, base 0xa800000 (absolute),
| size 4M, align 4M
|
`-- bridge #1
| res #2, base 0xa000000 (absolute),
| size 8M, align 8M
|
`-- device #1
res #3, base 0xa000000 (absolute),
size 8M, align 8M
Change-Id: I70c700318a85f6760f27597730bc9c9a86dbe6b3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/resource_allocator_v4.c
1 file changed, 259 insertions(+), 266 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/65420/13
--
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Attention is currently required from: Michał Żygowski, Krystian Hebel.
Hello Michał Żygowski, Krystian Hebel,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/68989
to review the following change.
Change subject: security/tpm: remove public tis_close()
......................................................................
security/tpm: remove public tis_close()
This function is never called from outside of drivers and
src/drivers/pc80/tpm/tis.c is the only one doing it.
tpm_vendor_cleanup() also isn't needed as one of tis_close() functions
was its only caller.
Change-Id: I9df76adfc21fca9fa1d1af7c40635ec0684ceb0f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/tis.c
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/tpm/tpm.c
M src/drivers/i2c/tpm/tpm.h
M src/drivers/pc80/tpm/tis.c
M src/drivers/spi/tpm/tis.c
M src/security/tpm/tis.h
9 files changed, 40 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/68989/1
diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
index bb1cf21..a7d4fa7 100644
--- a/src/drivers/crb/tis.c
+++ b/src/drivers/crb/tis.c
@@ -53,19 +53,6 @@
return 0;
}
-int tis_close(void)
-{
- if (tpm_is_open) {
- /*
- * Do we need to do something here, like waiting for a
- * transaction to stop?
- */
- tpm_is_open = 0;
- }
-
- return 0;
-}
-
int tis_init(void)
{
struct tpm2_info info;
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
index b5cb32c..42eeff4 100644
--- a/src/drivers/i2c/tpm/cr50.c
+++ b/src/drivers/i2c/tpm/cr50.c
@@ -494,10 +494,6 @@
return 0;
}
-void tpm_vendor_cleanup(struct tpm_chip *chip)
-{
-}
-
enum cb_err tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes)
{
return cr50_i2c_write(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS;
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index 80de2df..5b199be 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -39,16 +39,6 @@
return 0;
}
-int tis_close(void)
-{
- if (chip.is_open) {
- tpm_vendor_cleanup(&chip);
- chip.is_open = 0;
- }
-
- return 0;
-}
-
int tis_init(void)
{
return tpm_vendor_probe(CONFIG_DRIVER_TPM_I2C_BUS,
diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c
index 3a87dec..669ac68 100644
--- a/src/drivers/i2c/tpm/tis_atmel.c
+++ b/src/drivers/i2c/tpm/tis_atmel.c
@@ -27,11 +27,6 @@
return 0;
}
-int tis_close(void)
-{
- return 0;
-}
-
int tis_init(void)
{
return 0;
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index 840b947..606f14d 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -550,8 +550,3 @@
release_locality(chip, 0, 1);
return -1;
}
-
-void tpm_vendor_cleanup(struct tpm_chip *chip)
-{
- release_locality(chip, chip->vendor.locality, 1);
-}
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index eb4fef1..868b306 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -61,6 +61,4 @@
int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr);
-void tpm_vendor_cleanup(struct tpm_chip *chip);
-
#endif /* __DRIVERS_TPM_SLB9635_I2C_TPM_H__ */
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 06f5434..980c785 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -630,10 +630,30 @@
}
/*
+ * tis_close()
+ *
+ * terminate the current session with the TPM by releasing the locked
+ * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
+ * removal did not succeed).
+ */
+static int tis_close(void)
+{
+ u8 locality = 0;
+ if (tis_has_access(locality)) {
+ tis_drop_access(locality);
+ if (tis_wait_dropped_access(locality)) {
+ printf("%s:%d - failed to release locality %u\n",
+ __FILE__, __LINE__, locality);
+ return TPM_DRIVER_ERR;
+ }
+ }
+ return 0;
+}
+
+/*
* tis_open()
*
- * Requests access to locality 0 for the caller. After all commands have been
- * completed the caller is supposed to call tis_close().
+ * Requests access to locality 0 for the caller.
*
* Returns 0 on success, TPM_DRIVER_ERR on failure.
*/
@@ -664,27 +684,6 @@
}
/*
- * tis_close()
- *
- * terminate the current session with the TPM by releasing the locked
- * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
- * removal did not succeed).
- */
-int tis_close(void)
-{
- u8 locality = 0;
- if (tis_has_access(locality)) {
- tis_drop_access(locality);
- if (tis_wait_dropped_access(locality)) {
- printf("%s:%d - failed to release locality %u\n",
- __FILE__, __LINE__, locality);
- return TPM_DRIVER_ERR;
- }
- }
- return 0;
-}
-
-/*
* tis_sendrecv()
*
* Send the requested data to the TPM and then try to get its response
diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c
index 5106fc0..b9b2a4a 100644
--- a/src/drivers/spi/tpm/tis.c
+++ b/src/drivers/spi/tpm/tis.c
@@ -38,19 +38,6 @@
return 0;
}
-int tis_close(void)
-{
- if (tpm_is_open) {
- /*
- * Do we need to do something here, like waiting for a
- * transaction to stop?
- */
- tpm_is_open = 0;
- }
-
- return 0;
-}
-
int tis_init(void)
{
struct spi_slave spi;
diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h
index 8868e1a..04a137f 100644
--- a/src/security/tpm/tis.h
+++ b/src/security/tpm/tis.h
@@ -44,23 +44,13 @@
/*
* tis_open()
*
- * Requests access to locality 0 for the caller. After all commands have been
- * completed the caller is supposed to call tis_close().
+ * Requests access to locality 0 for the caller.
*
* Returns 0 on success, -1 on failure.
*/
int tis_open(void);
/*
- * tis_close()
- *
- * terminate the current session with the TPM by releasing the locked
- * locality. Returns 0 on success of -1 on failure (in case lock
- * removal did not succeed).
- */
-int tis_close(void);
-
-/*
* tis_sendrecv()
*
* Send the requested data to the TPM and then try to get its response
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68984 )
Change subject: soc: Add SPDX license headers to Makefiles
......................................................................
Patch Set 2: Code-Review+2
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Attention is currently required from: Rocky Phagura, Paul Menzel, Angel Pons, Tim Chu.
Hello build bot (Jenkins), Rocky Phagura, Angel Pons, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68758
to look at the new patch set (#5).
Change subject: drivers/ipmi/ocp: add PCIe SEL support
......................................................................
drivers/ipmi/ocp: add PCIe SEL support
Add Kconfig SOC_RAS_BMS_SEL and corresponding support for
generating PCIe error SEL records and sending them to BMC.
Add PCIe error definitions.
This is needed for SMM, so build the ipmi kcs driver in SMM.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Signed-off-by: Rocky Phagura <rphagura(a)fb.com>
Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com>
Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65
---
M src/drivers/ipmi/Makefile.inc
M src/drivers/ipmi/ocp/Kconfig
M src/drivers/ipmi/ocp/Makefile.inc
M src/drivers/ipmi/ocp/ipmi_ocp.h
A src/drivers/ipmi/ocp/ipmi_sel.c
5 files changed, 251 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/68758/5
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