coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: Documentation/releases: Update 4.15 vboot supported boards
by Jason Glenesk (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Felix Singer, Martin Roth, Matt DeVillier, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58975 ) Change subject: Documentation/releases: Update 4.15 vboot supported boards ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I think it would be a lot more helpful if the various Google boards were arranged/grouped based on b […] Thanks Matt. We can bring up a formatting change, and see how painful the scripting would be. Ideally I would like to minimize the # of hand changes, but I agree if we occasionally have to do one, it would not end the world. -- To view, visit https://review.coreboot.org/c/coreboot/+/58975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7 Gerrit-Change-Number: 58975 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 14:27:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58969 to look at the new patch set (#8). Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h 5 files changed, 330 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 8 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/lint/kconfig_lint: Fix off by one error that missed last line
by Felix Held (Code Review) 09 Nov '21

09 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58992 ) Change subject: util/lint/kconfig_lint: Fix off by one error that missed last line ...................................................................... util/lint/kconfig_lint: Fix off by one error that missed last line This error prevented the last line of the Kconfig tree from being printed or added to the output file. This is a significant problem if you try to use the generated file as the kconfig source, because it changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to NO. This causes the build to stop working. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/lint/kconfig_lint 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index a3495ce..32bf92d 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1312,7 +1312,7 @@ return unless $print_full_output; - for ( my $i = 0 ; $i < $#wholeconfig ; $i++ ) { + for ( my $i = 0 ; $i <= $#wholeconfig ; $i++ ) { my $line = $wholeconfig[$i]; chop( $line->{text} ); -- To view, visit https://review.coreboot.org/c/coreboot/+/58992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a Gerrit-Change-Number: 58992 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: amd/sata: Remove the weak function
by Felix Held (Code Review) 09 Nov '21

09 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58644 ) Change subject: amd/sata: Remove the weak function ...................................................................... amd/sata: Remove the weak function BUG=b:140165023 Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/sata/sata.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 79c381e..9caec89 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -6,8 +6,6 @@ #include <device/pci_ids.h> #include <amdblocks/sata.h> -void __weak soc_enable_sata_features(struct device *dev) { } - static const char *sata_acpi_name(const struct device *dev) { return "STCR"; 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Gerrit-Change-Number: 58644 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/brask: Enable LAN driver
by Zhuohao Lee (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Alan Huang. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Enable LAN driver ...................................................................... Patch Set 5: (3 comments) File src/mainboard/google/brya/variants/brask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58105/comment/ea5979b9_12ec0884 PS5, Line 84: 0x05af This is incorrect. Let's define the led in the buganizer. https://review.coreboot.org/c/coreboot/+/58105/comment/0756af18_4cfccfb3 PS5, Line 85: register "wake" = "0" I think you can remove this but let's follow up b/204289108 to see if we need to change the wakeup pin https://review.coreboot.org/c/coreboot/+/58105/comment/2a3f4218_83555f40 PS5, Line 86: register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" IIUC, this setting will disable the wake on lan. Could you please double check it? -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 14:09:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/variants/gimble: Update audio setting for SmartAMP
by Mark Hsieh (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Felix Held, Zhuohao Lee. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59046 ) Change subject: mb/google/brya/variants/gimble: Update audio setting for SmartAMP ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Gerrit-Change-Number: 59046 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Nov 2021 14:08:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/trogdor: Adjust mipi panel backlight gpio
by Xuxin Xiong (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: zanxi chen. Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59044 ) Change subject: mb/google/trogdor: Adjust mipi panel backlight gpio ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/59044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Gerrit-Change-Number: 59044 Gerrit-PatchSet: 5 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 13:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/trogdor: Adjust mipi panel backlight gpio
by zanxi chen (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: zanxi chen, Xuxin Xiong. Hello build bot (Jenkins), Xuxin Xiong, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59044 to look at the new patch set (#5). Change subject: mb/google/trogdor: Adjust mipi panel backlight gpio ...................................................................... mb/google/trogdor: Adjust mipi panel backlight gpio According hareware design of mrbland and wormdingler, mipi panel backlight relies on AP_BKLTEN(GPIO_12) and TP_EN(GPIO_85). Meanwhile, TP_EN(GPIO_85) needs pull up to enable PP3300_DISP_ON before AP_BKLTEN(GPIO_12) up. BUG=b:197709288,b:199081803,b:205166230 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/trogdor/board.h M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/trogdor/mainboard.c 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59044/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Gerrit-Change-Number: 59044 Gerrit-PatchSet: 5 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/trogdor: Adjust mipi panel backlight gpio
by build bot (Jenkins) (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: zanxi chen, Xuxin Xiong. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59044 ) Change subject: mb/google/trogdor: Adjust mipi panel backlight gpio ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/trogdor/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132709): https://review.coreboot.org/c/coreboot/+/59044/comment/d56ae09e_9504963b PS4, Line 145: if (CONFIG(BOARD_GOOGLE_MRBLAND) || CONFIG(BOARD_GOOGLE_WORMDINGLER)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/59044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Gerrit-Change-Number: 59044 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 13:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Angel Pons (Code Review) 09 Nov '21

09 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 52: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55367/comment/702c102c_a06cfac8 PS52, Line 9: The Intel® Programmable Services Engine (Intel® PSE) is a : dedicated offload engine for IoT functions powered by an ARM : Cortex-M7 microcontroller. It provides independent, low-DMIPS : computing and low-speed I/Os for IoT applications, plus : dedicated services for real-time computing and time-sensitive : synchronization. : : The PSE hosts new functions, including remote out-of-band : device management, network proxy, embedded controller lite : and sensor hub. : : This CL enables the user to provide the base address of the : PSE FW blob which will then be loaded by the FSP-S onto the : ARM controller. PSE FW will do the initialization work of : PSE controller and it's peripherals. The loading of PSE FW : should have negligible impact on boot time unless PSE : controller could not locate PSE FW and FSP will attempt to : redo PSE FW loading and wait for PSE handshake until it times : out. Once PSE controller locate PSE FW, it will do initialization : concurrently by itself with coreboot booting. : : It also adds PSE related FSP-S UPD settings which enables the : setup of peripheral ownership (assigned to the PSE or x86 : subsystem) and interrupts. These assignments need to take : place at a given point in the boot process and cannot be : changed later. : : To verify if PSE FW is loaded properly, the user could enable : PchPseShellEnabled flag and the log will be printed at PSE UART 2. : : For further info please refer to doc #611825 (for HW overview) : and #614110 (for PSE EDS). > Please reflow for 75 characters per line. Isn't the limit 72 characters per line? File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/bcdba45c_6ea46d09 PS52, Line 202: atom nit: Capitalize `Atom` https://review.coreboot.org/c/coreboot/+/55367/comment/31adf9fd_f526141e PS52, Line 212: c typo: remove extra `c` in `ex*ecuted` https://review.coreboot.org/c/coreboot/+/55367/comment/b85651a2_70de4565 PS52, Line 220: config PSE_FW_FILE_SIZE If these values are in KiB, how about adding a `_KIB` suffix to their names? I'd also use the `int` type for these options, as using hex values to specify sizes in KiB feels rather confusing to me. Alternatively, just specify the sizes in bytes using hex values. File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/208a3f34_2af2746a PS2, Line 58: pse.bin-align := 0x1000 > Fine with me! Looks like FSP copies the PSE FW to RAM, so the alignment of the file in CBFS shouldn't matter. Also, the current code copies the CBFS file into an array, which discards the alignment. File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/2d022a1e_e636372c PS52, Line 94: %08x You can use `z` to print a `size_t` variable without any casts. In this case, you can use `%08zx` and drop the `uint32_t` cast before `psefwsize`. https://review.coreboot.org/c/coreboot/+/55367/comment/38fbe2a2_3db18fb0 PS52, Line 129: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 3; Why does PSE init require these settings? Are they always required independently of the mainboard and PSE firmware being loaded? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 52 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 13:22:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021