coreboot-gerrit June 2020

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Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33788 Change subject: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code ...................................................................... [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code This is not wacom specific code. Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/lenovo.h M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87392/superio.c 6 files changed, 66 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33788/1 diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..c7e1b8f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,2 @@ int drivers_lenovo_is_wacom_present(void); -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..dfbd840 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -37,8 +37,7 @@ "2263", "2266", }; -int -drivers_lenovo_is_wacom_present(void) +int drivers_lenovo_is_wacom_present(void) { const char *pn; int i; @@ -85,9 +84,7 @@ return (result = 0); } -void -drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) { acpigen_write_scope(scope); @@ -110,27 +107,5 @@ acpigen_pop_len(); } - if (have_dock_serial) { - acpigen_write_device("COMA"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0501"); - acpigen_write_name("_UID"); - /* Byte */ - acpigen_write_byte(0x2); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); - acpigen_write_irq(1 << 4); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - acpigen_pop_len(); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7..bcb94b1 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -19,7 +19,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc..8cd87aa 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -58,7 +58,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0..9febea5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -115,7 +115,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..bf4ee54 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -25,12 +27,70 @@ return; } +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87392_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case PC87392_SP2: + case PC87392_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IOBASE not set.\n", + dev->path.pnp.device); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IRQ not set.\n", + dev->path.pnp.device); + break; + } + acpigen_write_scope(scope); + const char *dev_name = dev->path.pnp.device == PC87392_SP1 + ? "COMA" : "COMB"; + acpigen_write_device(dev_name); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); + /* Byte */ + acpigen_write_byte(0x2); + + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + + /* TODO, This likely depends on dock status */ + acpigen_write_STA(0xf); + + acpigen_pop_len(); /* pop scope */ + } +} +#endif + + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87392_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Gerrit-Change-Number: 33788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/it8728f: hook up power_on_after_fail
by James (Code Review) 10 Jun '23

10 Jun '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34884 ) Change subject: superio/ite/it8728f: hook up power_on_after_fail ...................................................................... superio/ite/it8728f: hook up power_on_after_fail Set the Super IO registers to power the system on if power_on_after_fail is set. Change-Id: Ia06dbbbed32ba13c2d91efa6377986db8452b3f4 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/superio/ite/it8728f/it8728f.h M src/superio/ite/it8728f/superio.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34884/1 diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 19a04de..36fd94e 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -28,6 +28,10 @@ #define IT8728F_GPIO 0x07 /* GPIO */ #define IT8728F_IR 0x0a /* Consumer IR */ +/* Registers in LDNs */ +#define IT8728F_EC_PCR1 0xf2 +#define IT8728F_EC_PCR2 0xf4 + /* Global configuration registers. */ #define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 7107bb4..d05be54 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -20,10 +20,42 @@ #include <pc80/keyboard.h> #include <stdlib.h> #include <superio/ite/common/env_ctrl.h> +#include <option.h> #include "chip.h" #include "it8728f.h" +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +static void power_control_init(struct device *dev) +{ + int power_on = MAINBOARD_POWER_OFF; + u8 value; + + get_option(&power_on, "power_on_after_fail"); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + value = pnp_read_config(dev, IT8728F_EC_PCR1); + if (power_on == MAINBOARD_POWER_KEEP) + value |= (1 << 5); + else + value &= ~(1 << 5); + pnp_write_config(dev, IT8728F_EC_PCR1, value); + + value = pnp_read_config(dev, IT8728F_EC_PCR2); + if (power_on == MAINBOARD_POWER_ON) + value |= (1 << 5); + else + value &= ~(1 << 5); + pnp_write_config(dev, IT8728F_EC_PCR2, value); + + pnp_exit_conf_mode(dev); +} + static void it8728f_init(struct device *dev) { const struct superio_ite_it8728f_config *conf = dev->chip_info; @@ -39,6 +71,7 @@ if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); + power_control_init(dev); break; case IT8728F_KBCK: set_kbc_ps2_mode(); -- To view, visit https://review.coreboot.org/c/coreboot/+/34884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06dbbbed32ba13c2d91efa6377986db8452b3f4 Gerrit-Change-Number: 34884 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Disable the eMMC controller for hatch
by V Sowmya (Code Review) 10 Jun '23

10 Jun '23

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615 Change subject: mb/google/hatch: Disable the eMMC controller for hatch ...................................................................... mb/google/hatch: Disable the eMMC controller for hatch eMMC controller is not used in hatch hence this patch adds the Kconfig option to disable the eMMC controller ACPI entries. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..15fe354 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select EXCLUDE_EMMC_INTERFACE if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/30615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Gerrit-Change-Number: 30615 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP
by Aamir Bohra (Code Review) 10 Jun '23

10 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30664 Change subject: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP ...................................................................... mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP **** DO NOT MERGE **** Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30664/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..4a47d12 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->RMT = 1; + memupd->FspmTestConfig.BdatEnable = 1; + mem_cfg->MrcFastBoot = 0; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + cannonlake_memcfg_init(mem_cfg, variant_memory_params(), &spd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Gerrit-Change-Number: 30664 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/ext_stage_cache: Use uintptr_t * as argument
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36560 ) Change subject: lib/ext_stage_cache: Use uintptr_t * as argument ...................................................................... lib/ext_stage_cache: Use uintptr_t * as argument This avoids a cast. Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/tseg_region.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36560/1 diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index a8b8bb7..519db61 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -68,11 +68,11 @@ return 0; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3c7d9fa..9f70711 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -52,7 +52,7 @@ #endif /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 52c0d6f..f56a9a4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -31,12 +31,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, size + (uintptr_t)base); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); -- To view, visit https://review.coreboot.org/c/coreboot/+/36560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Gerrit-Change-Number: 36560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Improve comment for DISB
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36650 ) Change subject: soc/intel/skylake: Improve comment for DISB ...................................................................... soc/intel/skylake: Improve comment for DISB Either documentation or FSP is wrong, as the behaviour of DISB is actually reversed. Document that and warn about clearing the bit. Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/pmc.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36650/1 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ab9297f..3bc5c68 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -31,7 +31,16 @@ void pmc_set_disb(void) { - /* Set the DISB after DRAM init */ + /* + * Set the DISB after DRAM init. + * + * According to Document Number: 332691-002EN + * "Intel 100 Series and Intel C230 Series Chipset Family Platform + * Controller Hub (PCH) Vol2" this bit must be CLEARED after DRAM init. + * + * Tests showed that either documentation or FSP is wrong. Clearing this + * bit here causes full memory training on every boot. + */ u32 disb_val; #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_PMC; -- To view, visit https://review.coreboot.org/c/coreboot/+/36650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Gerrit-Change-Number: 36650 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]util/inteltool: Add dumping x4x timings
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35812 ) Change subject: [WIP]util/inteltool: Add dumping x4x timings ...................................................................... [WIP]util/inteltool: Add dumping x4x timings TODO DQS RX settings. Change-Id: I8816a3eb43b9a27ea09997e9cc0407c519485943 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/inteltool/Makefile M util/inteltool/inteltool.h M util/inteltool/memory.c A util/inteltool/x4x_memory.c 4 files changed, 284 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35812/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8..6c7dc80 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o x4x_memory.o \ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..cdd42da 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -400,5 +400,6 @@ int print_ahci(struct pci_dev *ahci); int print_sgx(void); void ivybridge_dump_timings(const char *dump_spd_file); +void x4x_dump_timings(void); #endif diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e80f1ba..6fe025d 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -200,6 +200,7 @@ case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + x4x_dump_timings(); break; case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: mchbar_phys = pci_read_long(nb, 0x48); diff --git a/util/inteltool/x4x_memory.c b/util/inteltool/x4x_memory.c new file mode 100644 index 0000000..a00ce82 --- /dev/null +++ b/util/inteltool/x4x_memory.c @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <errno.h> +#include "inteltool.h" + +extern volatile uint8_t *mchbar; + +struct dll_setting { + u8 tap; + u8 pi; + u8 db_en; + u8 db_sel; + u8 clk_delay; + u8 coarse; +}; + +static void print_dll_setting(char *s, const struct dll_setting *dll_setting) +{ + printf("\t%s: %x.%x.%x.%x:%x.%x\n", + s, + dll_setting->coarse, + dll_setting->clk_delay, + dll_setting->tap, + dll_setting->pi, + dll_setting->db_en, + dll_setting->db_sel); +} + + +static uint32_t read_mchbar32(uint32_t addr) +{ + return *(volatile uint32_t *)(mchbar + addr); +} + +static void get_clkset0(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x5a0); + setting->clk_delay = (reg >> 14) & 3; + setting->db_sel = (reg >> 6) & 1; + setting->db_en = (reg >> 10) & 1; + reg = read_mchbar32(0x400 * channel + 0x581); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset0(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x59c); + setting->clk_delay = (reg >> 24) & 3; + setting->db_sel = (reg >> 20) & 1; + setting->db_en = (reg >> 21) & 1; + reg = read_mchbar32(0x400 * channel + 0x584); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_clkset1(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x5a0); + setting->clk_delay = (reg >> 16) & 3; + setting->db_sel = (reg >> 7) & 1; + setting->db_en = (reg >> 11) & 1; + reg = read_mchbar32(0x400 * channel + 0x582); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_cmdset(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 4) & 3; + reg = read_mchbar32(0x400 * channel + 0x594); + setting->db_sel = (reg >> 5) & 1; + setting->db_en = (reg >> 6) & 1; + reg = read_mchbar32(0x400 * channel + 0x580); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset1(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x59c); + setting->clk_delay = (reg >> 27) & 3; + setting->db_sel = (reg >> 22) & 1; + setting->db_en = (reg >> 23) & 1; + reg = read_mchbar32(0x400 * channel + 0x585); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset2(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 14) & 3; + setting->db_sel = (reg >> 12) & 1; + setting->db_en = (reg >> 13) & 1; + reg = read_mchbar32(0x400 * channel + 0x586); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_ctrlset3(u8 channel, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = 0; + reg = read_mchbar32(0x400 * channel + 0x598); + setting->clk_delay = (reg >> 10) & 3; + setting->db_sel = (reg >> 8) & 1; + setting->db_en = (reg >> 9) & 1; + reg = read_mchbar32(0x400 * channel + 0x587); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_dqs(u8 channel, u8 rank, u8 lane, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = (read_mchbar32(0x400 * channel + 0x5fc) >> (lane * 4 +1) & 1); + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5b4); + setting->db_sel = (reg >> lane) & 1; + setting->db_en = (reg >> (9 + lane)) & 1; + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5c8); + setting->clk_delay = (reg >> (16 + lane * 2)) & 3; + reg = read_mchbar32(0x400 * channel + rank + lane * 4 + 0x520); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +static void get_dq(u8 channel, u8 rank, u8 lane, struct dll_setting *setting) +{ + u32 reg; + setting->coarse = (read_mchbar32(0x400 * channel + 0x5fc) >> (lane * 4) & 1); + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5a4); + setting->db_sel = (reg >> lane) & 1; + setting->db_en = (reg >> (9 + lane)) & 1; + reg = read_mchbar32(0x400 * channel + rank * 4 + 0x5c8); + setting->clk_delay = (reg >> (lane * 2)) & 3; + reg = read_mchbar32(0x400 * channel + rank + lane * 4 + 0x500); + setting->pi = (reg >> 4) & 0xf; + setting->tap = reg & 0xf; +} + +void x4x_dump_timings(void) +{ + u32 reg = 0; + + printf("\nG45 Memory controller settings\n==============================\n\n"); + printf("Programmed timings:\n"); + switch (read_mchbar32(0xc00) & 0x7) { + case 0: + reg = 1066; + break; + case 2: + reg = 800; + break; + case 4: + reg = 1333; + break; + default: + printf("Unsupported FSB frequency.\n"); + break; + } + if (reg) + printf("\tFSB freq : %dMHZ\n", reg); + + u32 mem_clk = (read_mchbar32(0xc00) & 0x70) >> 4; + switch (mem_clk) { + case 0: + reg = 400; + break; + case 1: + reg = 533; + break; + case 2: + reg = 667; + break; + case 3: + reg = 800; + break; + case 4: + reg = 1066; + break; + case 5: + reg = 1333; + break; + default: + printf("Unsupported MEM frequency.\n"); + break; + } + if (reg) + printf("\tMEM freq : %dMT\n", reg); + + int is_ddr3 = (read_mchbar32(0x1a8) & 4) >> 2; + printf("\tDDR TYPE : %d\n", is_ddr3 ? 3 : 2); + + u8 tcas, tras, twl, twr, trrd, trp, trfc, trcd, twtr, trtp; + + for (int channel = 0; channel < 2; channel++) { + tcas = (read_mchbar32(0x240 + 0x400 * channel) & 0xf) + 3; + tras = read_mchbar32(0x25d + 0x400 * channel) & 0x3f; + twl = is_ddr3 ? (mem_clk - 3 + 5) : (tcas - 1U); + twr = ((read_mchbar32(0x250 + 0x400 * channel) >> 6) & 0x3f) - twl - 4; + trrd = (read_mchbar32(0x252 + 0x400 * channel) >> 17) & 0x1f; + trp = (read_mchbar32(0x252 + 0x400 * channel) >> 13) & 0x1f; + trfc = read_mchbar32(0x252 + 0x400 * channel) & 0x1ff; + trcd = (read_mchbar32(0x256 + 0x400 * channel) >> 12) & 0xf; + twtr = ((read_mchbar32(0x258 + 0x400 * channel) >> 12) & 0x1f) - 4 - twl; + trtp = ((read_mchbar32(0x250 + 0x400 * channel) >> 2) & 0xf) - 2; + + printf("Channel %d\n", channel); + printf("\ttCAS: %d\n", tcas); + printf("\ttRAS: %d\n", tras); + printf("\ttRP : %d\n", trp); + printf("\ttRCD: %d\n", trcd); + printf("\ttWR : %d\n", twr); + printf("\ttRFC: %d\n", trfc); + printf("\ttWTR: %d\n", twtr); + printf("\ttRRD: %d\n", trrd); + printf("\ttRTP: %d\n", trtp); + printf("\ttWL : %d\n", twl); + } + printf("\nProgrammed delays:\n"); + for (int channel = 0; channel < 2; channel++) { + printf("Channel %d\n", channel); + struct dll_setting setting; + char s[20]; + get_clkset0(channel, &setting); + print_dll_setting("clkset0 ", &setting); + get_ctrlset0(channel, &setting); + print_dll_setting("ctrlset0", &setting); + get_clkset1(channel, &setting); + print_dll_setting("clkset1 ", &setting); + get_cmdset(channel, &setting); + print_dll_setting("cmdset ", &setting); + get_ctrlset1(channel, &setting); + print_dll_setting("ctrlset1", &setting); + get_ctrlset2(channel, &setting); + print_dll_setting("ctrlset2", &setting); + get_ctrlset3(channel, &setting); + print_dll_setting("ctrlset3", &setting); + for (int lane = 0; lane < 8; lane++) { + sprintf(s, "DQS%d ", lane); + /* All rank should be programmed the same */ + get_dqs(channel, 0, lane, &setting); + print_dll_setting(s, &setting); + } + for (int lane = 0; lane < 8; lane++) { + sprintf(s, "DQ%d ", lane); + /* All rank should be programmed the same */ + get_dq(channel, 0, lane, &setting); + print_dll_setting(s, &setting); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8816a3eb43b9a27ea09997e9cc0407c519485943 Gerrit-Change-Number: 35812 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36748 ) Change subject: [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value ...................................................................... [TEST_ONLY]:mb/google/hatch/variants/baseboard: Update tcc_offset value Update tcc_offset value to 5 degree C to test this on i7 Helios systems. Change-Id: Ie319bf1460a5bdeeb86bdf579a24103cac273295 --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/36748/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a2831e1..386df3b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -45,7 +45,7 @@ # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" - register "tcc_offset" = "10" # TCC of 90C + register "tcc_offset" = "5" # TCC of 95C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" # SD card WP pin confguration -- To view, visit https://review.coreboot.org/c/coreboot/+/36748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie319bf1460a5bdeeb86bdf579a24103cac273295 Gerrit-Change-Number: 36748 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Start VBOOT in bootblock
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36926 ) Change subject: nb/intel/sandybridge: Start VBOOT in bootblock ...................................................................... nb/intel/sandybridge: Start VBOOT in bootblock This also puts romstage in RW fmap regions. Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36926/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..2ef6299 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -24,7 +24,8 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config USE_NATIVE_RAMINIT bool "Use native raminit" -- To view, visit https://review.coreboot.org/c/coreboot/+/36926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Gerrit-Change-Number: 36926 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36829 ) Change subject: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode ...................................................................... [TESTONLY]nb/intel/x4x: force COMMAND 2N mode Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36829/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..3626497 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -234,13 +234,13 @@ /* Default 2N mode */ s->nmode = 2; - if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) - s->nmode = 1; - /* 2N on DDR3 1066 with with 2 dimms per channel */ - if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && - (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || - BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) - s->nmode = 2; + /* if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) */ + /* s->nmode = 1; */ + /* /\* 2N on DDR3 1066 with with 2 dimms per channel *\/ */ + /* if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && */ + /* (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || */ + /* BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) */ + /* s->nmode = 2; */ launch1 = ddr3_launch1_tab[s->nmode - 1] [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; launch2 = ddr3_launch2_tab[s->nmode - 1] -- To view, visit https://review.coreboot.org/c/coreboot/+/36829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Gerrit-Change-Number: 36829 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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