coreboot-gerrit June 2020

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Change in coreboot[master]: lib/edid: Drop bytes_per_line
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39773 ) Change subject: lib/edid: Drop bytes_per_line ...................................................................... lib/edid: Drop bytes_per_line There where only two users of this field, but in both cases incorrectly implemented, as there was either no producer or no consumer. Remove it as the same information is now be passed directly to the framebuffer info storage and thus it's no longer needed. Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/lib/edid.c M src/northbridge/intel/i945/gma.c 4 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39773/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 8091802..4b57308 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -224,13 +224,12 @@ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; - edid.bytes_per_line = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); /* Updated framebuffer info for ast_crtc_mode_set */ - fb.pitches[0] = edid.bytes_per_line; + fb.pitches[0] = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d @ %d BPP\n", - edid.x_resolution, edid.y_resolution, edid.bytes_per_line, + edid.x_resolution, edid.y_resolution, fb.pitches[0], edid.framebuffer_bits_per_pixel); /* Convert EDID to AST DRM mode */ @@ -250,7 +249,7 @@ fb_add_framebuffer_info_from_edid(&edid, fb.mmio_addr, 8); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)fb.mmio_addr, 0, fb.pitches[0] * edid.y_resolution); return 0; } diff --git a/src/include/edid.h b/src/include/edid.h index 02afae7..9733b0c 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -83,14 +83,13 @@ struct edid_mode mode; u8 mode_is_supported[NUM_KNOWN_MODES]; unsigned int link_clock; - /* 3 variables needed for coreboot framebuffer. + /* 2 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha * and va variables, but not always, as in the * case of a 1366 wide display. */ u32 x_resolution; u32 y_resolution; - u32 bytes_per_line; int hdmi_monitor_detected; char ascii_string[EDID_ASCII_STRING_LENGTH + 1]; diff --git a/src/lib/edid.c b/src/lib/edid.c index 048cc6a..473fc1b 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1689,13 +1689,15 @@ void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment) { + uint32_t bytes_per_line; + /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); row_byte_alignment = MAX(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; - edid->bytes_per_line = ALIGN_UP(edid->mode.ha * + bytes_per_line = ALIGN_UP(edid->mode.ha * DIV_ROUND_UP(fb_bpp, 8), row_byte_alignment); - edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); + edid->x_resolution = bytes_per_line / (fb_bpp / 8); edid->y_resolution = edid->mode.va; } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1b1a1bf..078ab74 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -108,6 +108,7 @@ unsigned long temp; int hpolarity, vpolarity; u32 smallest_err = 0xffffffff; + u32 bytes_per_line; u32 target_frequency; u32 pixel_p1 = 1; u32 pixel_p2; @@ -314,10 +315,11 @@ write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(mmiobase + DSPPOS(0), 0); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + bytes_per_line = DIV_ROUND_UP(hactive * 32 / 8, 64); + write32(mmiobase + DSPADDR(0), 0); write32(mmiobase + DSPSURF(0), 0); - write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmiobase + DSPSTRIDE(0), bytes_per_line); write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/39773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Gerrit-Change-Number: 39773 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK sc7180: BL31 config change to 3MB in memlayout HACK
by Manideep Kurumella (Code Review) 07 Aug '23

07 Aug '23

Manideep Kurumella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39858 ) Change subject: HACK sc7180: BL31 config change to 3MB in memlayout HACK ...................................................................... HACK sc7180: BL31 config change to 3MB in memlayout HACK Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39858/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 67a372a..c8a9232 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -62,8 +62,8 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x300000, 0x1000) - BL31(0x80C00000, 2M) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 3M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/39858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f Gerrit-Change-Number: 39858 Gerrit-PatchSet: 1 Gerrit-Owner: Manideep Kurumella <mkurumel(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40203 ) Change subject: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB ...................................................................... mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 8.720370] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input2 [ 8.729081] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device (gigabyte/ga-945gcm-s2l, intel/d945gclf).. Fixes: 6390e525 ("mb/asus/p5gc-mx: Add mainboard") Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/p5gc-mx/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40203/1 diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl index 5187b2a..bb86c6c 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -12,14 +12,6 @@ * GNU General Public License for more details. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Gerrit-Change-Number: 40203 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/acpi: Increase Max PCI bus count support
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40335 ) Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ...................................................................... src/arch/x86/acpi: Increase Max PCI bus count support This patch increase maximum bus end variable type to match latest SoC specification [Ice Lake EDS vol 1 chapter 3.18] Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40335/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6eded1d..ccc24db 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -104,7 +104,7 @@ } int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) + u16 seg_nr, u8 start, u16 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 644f52f..82faa8f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -871,7 +871,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u16 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -- To view, visit https://review.coreboot.org/c/coreboot/+/40335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Gerrit-Change-Number: 40335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86/smm: add mainboard intruder detection SMI handler prototype
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40341 ) Change subject: x86/smm: add mainboard intruder detection SMI handler prototype ...................................................................... x86/smm: add mainboard intruder detection SMI handler prototype Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 --- M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40341/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3169ace..eff512f 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -191,3 +191,4 @@ void __weak mainboard_smi_gpi(u32 gpi_sts) {} int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} +void __weak mainboard_smi_intruder(u32 tco_sts) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 0b76708..7a78268 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -44,6 +44,7 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); +void mainboard_smi_intruder(u32 tco_sts); /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/40341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 Gerrit-Change-Number: 40341 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/elog: add event log parsing tables
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40343 ) Change subject: commonlib/elog: add event log parsing tables ...................................................................... commonlib/elog: add event log parsing tables Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda --- A src/commonlib/include/commonlib/elog.h 1 file changed, 402 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40343/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9034579 --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#include <stdint.h> + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +struct elog_event_name { + uint8_t event_type; + char *event_name; +}; + +static const struct elog_event_name elog_event_to_name[] = { + { ELOG_TYPE_UNDEFINED_EVENT, "UNDEFINED EVENT" }, + { ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR, "Single-Bit ECC memory error" }, + { ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR, "Multi-Bit ECC memory error" }, + { ELOG_TYPE_MEM_PARITY_ERR, "Memory parity error" }, + { ELOG_TYPE_BUS_TIMEOUT, "Bus time-out" }, + { ELOG_TYPE_IO_CHECK, "IO channel check" }, + { ELOG_TYPE_SW_NMI, "Software NMI" }, + { ELOG_TYPE_POST_MEM_RESIZE, "Post memory resize" }, + { ELOG_TYPE_POST_ERR, "Post error" }, + { ELOG_TYPE_PCI_PERR, "PCI parity error" }, + { ELOG_TYPE_PCI_SERR, "PCI system error" }, + { ELOG_TYPE_CPU_FAIL, "CPU failure" }, + { ELOG_TYPE_EISA_TIMEOUT, "EISA FailSafe Timer time-out" }, + { ELOG_TYPE_CORRECTABLE_MEMLOG_DIS, "Correctable memory log disable" }, + { ELOG_TYPE_LOG_DISABLED, "Event log disabled for type" }, + { ELOG_TYPE_UNDEFINED_EVENT2, "UNDEFINED EVENT 2" }, + { ELOG_TYPE_SYS_LIMIT_EXCEED, "System limit exceeded" }, + { ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED, "Asynchronous hardware timer expired and issued a system reset" }, + { ELOG_TYPE_SYS_CONFIG_INFO, "System configuration information" }, + { ELOG_TYPE_HDD_INFO, "Hard-disk information" }, + { ELOG_TYPE_SYS_RECONFIG, "System reconfigured" }, + { ELOG_TYPE_CPU_ERROR, "Uncorrectable CPU-complex error" }, + { ELOG_TYPE_LOG_CLEAR, "Log Area reset/cleared" }, + { ELOG_TYPE_BOOT, "System boot" }, + { ELOG_TYPE_OS_EVENT, "Operating system event" }, + { ELOG_TYPE_OS_BOOT, "Boot operating system" }, + { ELOG_TYPE_POWER_FAIL, "Power failure" }, + { ELOG_TYPE_SUS_POWER_FAIL, "Suspend power failure" }, + { ELOG_TYPE_PWROK_FAIL, "Power OK failure" }, + { ELOG_TYPE_SYS_PWROK_FAIL, "System power OK failure" }, + { ELOG_TYPE_POWER_ON, "Power on" }, + { ELOG_TYPE_POWER_BUTTON, "Power button pressed" }, + { ELOG_TYPE_POWER_BUTTON_OVERRIDE, "Power button override" }, + { ELOG_TYPE_RESET_BUTTON, "Reset button pressed" }, + { ELOG_TYPE_SYSTEM_RESET, "System reset" }, + { ELOG_TYPE_RTC_RESET, "Real Time Clock reset" }, + { ELOG_TYPE_TCO_RESET, "TCO timer reset" }, + { ELOG_TYPE_ACPI_ENTER, "Entered ACPI state" }, + { ELOG_TYPE_ACPI_WAKE, "ACPI wake event" }, + { ELOG_TYPE_WAKE_SOURCE, "ACPI wake source" }, + { ELOG_TYPE_CROS_DEVELOPER_MODE, "Entered ChromeOS developer mode" }, + { ELOG_TYPE_CROS_RECOVERY_MODE, "Entered ChromeOS recovery mode" }, + { ELOG_TYPE_MANAGEMENT_ENGINE, "Intel Management Engine event" }, + { ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Intel Management Engine extended event" }, + { ELOG_TYPE_LAST_POST_CODE, "Post code from last boot" }, + { ELOG_TYPE_POST_EXTRA, "Post code extra" }, + { ELOG_TYPE_EC_SHUTDOWN, "Embedded Controller shutdown" }, + { ELOG_TYPE_SLEEP, "Entered sleep mode", }, + { ELOG_TYPE_WAKE, "Wake event" }, + { ELOG_TYPE_FW_WAKE, "Firmware wake event" }, + { ELOG_TYPE_MEM_CACHE_UPDATE, "MRC cache update" }, + { ELOG_TYPE_THERM_TRIP, "Thermal trip occurred" }, + { ELOG_TYPE_CR50_UPDATE, "CR50 TPM update event" }, + { ELOG_TYPE_ACPI_DEEP_WAKE, "ACPI deep wake event" }, + { ELOG_TYPE_EC_DEVICE_EVENT, "Embedded controller device event" }, + { ELOG_TYPE_S0IX_ENTER, "Entered S0ix state" }, + { ELOG_TYPE_S0IX_EXIT, "Exited from S0ix state" }, + { ELOG_TYPE_EXTENDED_EVENT, "Extended event" }, + { ELOG_TYPE_CR50_NEED_RESET, "CR50 TPM configuration needs reset" }, + { ELOG_TYPE_INTRUDER_DETECTION, "Intrusion detection " } +}; + +static const struct elog_event_name elog_ec_event_to_name[] = { + { EC_EVENT_LID_CLOSED, "Lid closed" }, + { EC_EVENT_LID_OPEN, "Lid open" }, + { EC_EVENT_POWER_BUTTON, "Power button pressed" }, + { EC_EVENT_AC_CONNECTED, "AC power supply connected" }, + { EC_EVENT_AC_DISCONNECTED, "AC power supply disconnected" }, + { EC_EVENT_BATTERY_LOW, "Battery low" }, + { EC_EVENT_BATTERY_CRITICAL, "Battery critical" }, + { EC_EVENT_BATTERY, "Battery event" }, + { EC_EVENT_THERMAL_THRESHOLD, "Thermal threshold reached" }, + { EC_EVENT_DEVICE_EVENT, "Device event" }, + { EC_EVENT_THERMAL, "Thermal event" }, + { EC_EVENT_USB_CHARGER, "USB charger" }, + { EC_EVENT_KEY_PRESSED, "Key pressed" }, + { EC_EVENT_INTERFACE_READY, "Interface ready" }, + { EC_EVENT_KEYBOARD_RECOVERY, "Keyboard recovery" }, + { EC_EVENT_THERMAL_SHUTDOWN, "Thermal shutdown" }, + { EC_EVENT_BATTERY_SHUTDOWN, "Battery shutdown" }, + { EC_EVENT_FAN_ERROR, "Fan error" }, + { EC_EVENT_THROTTLE_STOP, "Throttling stopeed" }, + { EC_EVENT_HANG_DETECT, "Hang detected" }, + { EC_EVENT_HANG_REBOOT, "Reboot hang" }, + { EC_EVENT_PD_MCU, "PD processor" }, + { EC_EVENT_BATTERY_STATUS, "Battery status" }, + { EC_EVENT_PANIC, "Panic" }, + { EC_EVENT_KEYBOARD_FASTBOOT, "Keyboard fastboot" }, + { EC_EVENT_RTC, "Real Time Clock" }, + { EC_EVENT_MKBP, "Matrix Keyboard Protocol" }, + { EC_EVENT_USB_MUX, "USB multiplexer" }, + { EC_EVENT_MODE_CHANGE, "Mode change" }, + { EC_EVENT_KEYBOARD_RECOVERY_HWREINIT, "Keyboard recovery hardware reinitialization" }, + { EC_EVENT_EXTENDED, "Extended event" } +}; + +static const struct elog_event_name elog_wake_event_to_name[] = { + { ELOG_WAKE_SOURCE_PCIE, "PCI Express" }, + { ELOG_WAKE_SOURCE_PME, "PME" }, + { ELOG_WAKE_SOURCE_PME_INTERNAL, "Internal PME" }, + { ELOG_WAKE_SOURCE_RTC, "Real Time Clock" }, + { ELOG_WAKE_SOURCE_GPIO, "GPIO" }, + { ELOG_WAKE_SOURCE_SMBUS, "SMBus" }, + { ELOG_WAKE_SOURCE_PWRBTN, "Power Button" }, + { ELOG_WAKE_SOURCE_PME_HDA, "HD Audio PME" }, + { ELOG_WAKE_SOURCE_PME_GBE, "Gigabit Ethernet PME" }, + { ELOG_WAKE_SOURCE_PME_EMMC, "Embedded MMC PME" }, + { ELOG_WAKE_SOURCE_PME_SDCARD, "SD card PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE1, "PCI Express 1 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE2, "PCI Express 2 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE3, "PCI Express 3 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE4, "PCI Express 4 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE5, "PCI Express 5 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE6, "PCI Express 6 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE7, "PCI Express 7 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE8, "PCI Express 8 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE9, "PCI Express 9 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, + { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, + { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, + { ELOG_WAKE_SOURCE_PME_CSE3, "CSE 3 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI, "xHCI PME" }, + { ELOG_WAKE_SOURCE_PME_XDCI, "xDCI PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_2, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_3, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_WIFI, "WiFi PME" } +}; + +static const struct elog_event_name elog_ec_device_event_to_name[] = { + { ELOG_EC_DEVICE_EVENT_TRACKPAD, "Trackpad" }, + { ELOG_EC_DEVICE_EVENT_DSP, "DSP" }, + { ELOG_EC_DEVICE_EVENT_WIFI, "WiFi" } +}; + +static const struct elog_event_name mrc_upd_slots[] = { + { ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, "NORMAL" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, "RECOVERY" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, "VARIABLE" } +}; + +static const char *const me_bios_paths[] = { + "ME normal BIOS path", + "ME S3 wake BIOS path", + "ME error BIOS path", + "ME recovery BIOS path", + "ME disable BIOS path", + "ME firmware update BIOS path", +}; + +#endif /* ELOG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda Gerrit-Change-Number: 40343 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: commonlib/elog: move the event definitions to commonlib
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40416 ) Change subject: commonlib/elog: move the event definitions to commonlib ...................................................................... commonlib/elog: move the event definitions to commonlib Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 --- A src/commonlib/include/commonlib/elog.h M src/drivers/elog/elog.c D src/drivers/elog/elog_internal.h M src/include/elog.h 4 files changed, 261 insertions(+), 238 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40416/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9c10beb --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef COMMONLIB_ELOG_H_ +#define COMMONLIB_ELOG_H_ + +/* ELOG header */ +struct elog_header { + uint32_t magic; + uint8_t version; + uint8_t header_size; + uint8_t reserved[2]; +} __packed; + +/* ELOG related constants */ +#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ +#define ELOG_VERSION 1 +#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ +#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ + +/* SMBIOS event log header */ +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* SMBIOS Type 15 related constants */ +#define ELOG_HEADER_TYPE_OEM 0x88 + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +#endif /* COMMONLIB_ELOG_H_ */ diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c353d59..2313ff1 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -20,8 +20,6 @@ #include <stdint.h> #include <string.h> #include <elog.h> -#include "elog_internal.h" - #if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h deleted file mode 100644 index 3c58ee2..0000000 --- a/src/drivers/elog/elog_internal.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#ifndef ELOG_INTERNAL_H_ -#define ELOG_INTERNAL_H_ - -/* ELOG header */ -struct elog_header { - u32 magic; - u8 version; - u8 header_size; - u8 reserved[2]; -} __packed; - -/* ELOG related constants */ -#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ -#define ELOG_VERSION 1 -#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ -#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ - -/* SMBIOS event log header */ -struct event_header { - u8 type; - u8 length; - u8 year; - u8 month; - u8 day; - u8 hour; - u8 minute; - u8 second; -} __packed; - -/* SMBIOS Type 15 related constants */ -#define ELOG_HEADER_TYPE_OEM 0x88 - -#endif /* ELOG_INTERNAL_H_ */ diff --git a/src/include/elog.h b/src/include/elog.h index 5a7632d..de642ae 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -4,206 +4,7 @@ #ifndef ELOG_H_ #define ELOG_H_ -#define MAX_EVENT_SIZE 0x7F - -/* End of log */ -#define ELOG_TYPE_EOL 0xFF - -/* - * Standard SMBIOS event log types below 0x80 - */ -#define ELOG_TYPE_UNDEFINED_EVENT 0x00 -#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 -#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 -#define ELOG_TYPE_MEM_PARITY_ERR 0x03 -#define ELOG_TYPE_BUS_TIMEOUT 0x04 -#define ELOG_TYPE_IO_CHECK 0x05 -#define ELOG_TYPE_SW_NMI 0x06 -#define ELOG_TYPE_POST_MEM_RESIZE 0x07 -#define ELOG_TYPE_POST_ERR 0x08 -#define ELOG_TYPE_PCI_PERR 0x09 -#define ELOG_TYPE_PCI_SERR 0x0A -#define ELOG_TYPE_CPU_FAIL 0x0B -#define ELOG_TYPE_EISA_TIMEOUT 0x0C -#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D -#define ELOG_TYPE_LOG_DISABLED 0x0E -#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F -#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 -#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 -#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 -#define ELOG_TYPE_HDD_INFO 0x13 -#define ELOG_TYPE_SYS_RECONFIG 0x14 -#define ELOG_TYPE_CPU_ERROR 0x15 -#define ELOG_TYPE_LOG_CLEAR 0x16 -#define ELOG_TYPE_BOOT 0x17 - -/* - * Extended defined OEM event types start at 0x80 - */ - -/* OS/kernel events */ -#define ELOG_TYPE_OS_EVENT 0x81 - -/* Last event from coreboot */ -#define ELOG_TYPE_OS_BOOT 0x90 - -/* Embedded controller event */ -#define ELOG_TYPE_EC_EVENT 0x91 - -/* Power */ -#define ELOG_TYPE_POWER_FAIL 0x92 -#define ELOG_TYPE_SUS_POWER_FAIL 0x93 -#define ELOG_TYPE_PWROK_FAIL 0x94 -#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 -#define ELOG_TYPE_POWER_ON 0x96 -#define ELOG_TYPE_POWER_BUTTON 0x97 -#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 - -/* Reset */ -#define ELOG_TYPE_RESET_BUTTON 0x99 -#define ELOG_TYPE_SYSTEM_RESET 0x9a -#define ELOG_TYPE_RTC_RESET 0x9b -#define ELOG_TYPE_TCO_RESET 0x9c - -/* Sleep/Wake */ -#define ELOG_TYPE_ACPI_ENTER 0x9d -/* - * Deep Sx wake variant is provided below - 0xad - * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 - */ - -#define ELOG_TYPE_ACPI_WAKE 0x9e -#define ELOG_TYPE_WAKE_SOURCE 0x9f -#define ELOG_WAKE_SOURCE_PCIE 0x00 -#define ELOG_WAKE_SOURCE_PME 0x01 -#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 -#define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 -#define ELOG_WAKE_SOURCE_SMBUS 0x05 -#define ELOG_WAKE_SOURCE_PWRBTN 0x06 -#define ELOG_WAKE_SOURCE_PME_HDA 0x07 -#define ELOG_WAKE_SOURCE_PME_GBE 0x08 -#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 -#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a -#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b -#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c -#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d -#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e -#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f -#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 -#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 -#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 -#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 -#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 -#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 -#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 -#define ELOG_WAKE_SOURCE_PME_SATA 0x17 -#define ELOG_WAKE_SOURCE_PME_CSE 0x18 -#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 -#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a -#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b -#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e -#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f -#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 -#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 -#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 -#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 -#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 -#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 -#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 -#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 -#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 -#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 -#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a -#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b - -struct elog_event_data_wake { - u8 source; - u32 instance; -} __packed; - -/* Chrome OS related events */ -#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 -#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 -#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 - -/* Management Engine Events */ -#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 -#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 -struct elog_event_data_me_extended { - u8 current_working_state; - u8 operation_state; - u8 operation_mode; - u8 error_code; - u8 progress_code; - u8 current_pmevent; - u8 current_state; -} __packed; - -/* Last post code from previous boot */ -#define ELOG_TYPE_LAST_POST_CODE 0xa3 -#define ELOG_TYPE_POST_EXTRA 0xa6 - -/* EC Shutdown Reason */ -#define ELOG_TYPE_EC_SHUTDOWN 0xa5 - -/* ARM/generic versions of sleep/wake - These came from another firmware - * apparently, but not all the firmware sources were updated so that the - * elog namespace was coherent. */ -#define ELOG_TYPE_SLEEP 0xa7 -#define ELOG_TYPE_WAKE 0xa8 -#define ELOG_TYPE_FW_WAKE 0xa9 - -/* Memory Cache Update */ -#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa -#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 -#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 -#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 -#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 -#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 -struct elog_event_mem_cache_update { - u8 slot; - u8 status; -} __packed; - -/* CPU Thermal Trip */ -#define ELOG_TYPE_THERM_TRIP 0xab - -/* Cr50 */ -#define ELOG_TYPE_CR50_UPDATE 0xac - -/* Deep Sx wake variant */ -#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad - -/* EC Device Event */ -#define ELOG_TYPE_EC_DEVICE_EVENT 0xae -#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 -#define ELOG_EC_DEVICE_EVENT_DSP 0x02 -#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 - -/* S0ix sleep/wake */ -#define ELOG_TYPE_S0IX_ENTER 0xaf -#define ELOG_TYPE_S0IX_EXIT 0xb0 - -/* Extended events */ -#define ELOG_TYPE_EXTENDED_EVENT 0xb1 -#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 -#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 - -/* Cr50 reset to enable TPM */ -#define ELOG_TYPE_CR50_NEED_RESET 0xb2 - -/* Intruder detection */ -#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 -#define ELOG_CASE_OPENED 0x01 -#define ELOG_CASE_CLOSED 0x02 - -struct elog_event_extended_event { - u8 event_type; - u32 event_complement; -} __packed; +#include <commonlib/elog.h> #if CONFIG(ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 Gerrit-Change-Number: 40416 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/tcss: Add common code support for TCSS
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41010 ) Change subject: soc/intel/common/block/tcss: Add common code support for TCSS ...................................................................... soc/intel/common/block/tcss: Add common code support for TCSS For now only added CONFIG_TCSS_PCIE_SEGMENT Kconfig to allow dedicated PCI segment support for iTBT. SoC user can select CONFIG_TCSS_PCIE_SEGMENT from dedicated SoC Kconfig to include this support. Change-Id: I33c1e5612a6d4882377784294ca0bcef131f2c0a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/tcss/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/41010/1 diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig new file mode 100644 index 0000000..0f7fe7c --- /dev/null +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_TCSS + bool + help + Intel Processor common TCSS support + +config TCSS_PCIE_SEGMENT + bool + help + Indicate the extra PCIE segment is required for iTBT or not -- To view, visit https://review.coreboot.org/c/coreboot/+/41010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33c1e5612a6d4882377784294ca0bcef131f2c0a Gerrit-Change-Number: 41010 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41013 ) Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ...................................................................... soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL This patch performs below operations 1. Include additional PCI segment by selecting TCSS_PCIE_SEGMENT from SoC 2. Clean up TGL SoC IRQ programming as TBT related programming is now moved into common code (src/soc/intel/common/block/acpi/acpi/pcisegment.asl) Change-Id: Ib94396bd2a06b661d4828357d7a4be973846c707 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h 3 files changed, 1 insertion(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/41013/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@ #define ISH_IRQ 16 -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/41013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94396bd2a06b661d4828357d7a4be973846c707 Gerrit-Change-Number: 41013 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: memrange: Add helper for stealing memory from the last range in the list
by Furquan Shaikh (Code Review) 07 Aug '23

07 Aug '23

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41418 ) Change subject: memrange: Add helper for stealing memory from the last range in the list ...................................................................... memrange: Add helper for stealing memory from the last range in the list This change adds a helper fucntion memranges_steal_last() that allows the caller to request memory to be stolen from the last range in the list. Memory is stolen from the start of the last range and matches the constraints (limit, align, tag, size) provided by the caller. The current helper functin memranges_steal() defaults to always returning stolen memory from the first available range in the list. Additionally, this change updates the internal function memranges_find_entry() to handle stealing from first and last entries as requested by the caller. Change-Id: I70c07e587597b44306857f0e52eb47b330ca3b1b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/memrange.h M src/lib/memrange.c 2 files changed, 59 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41418/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00e..4b64e1a 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -160,7 +160,8 @@ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); -/* Steals memory from the available list in given ranges as per the constraints: +/* Steals memory from the first available entry in the list of given ranges as per the + * constraints: * limit = Upper bound for the memory range to steal (Inclusive). * size = Requested size for the stolen memory. * align = Required alignment(log 2) for the starting address of the stolen memory. @@ -172,4 +173,18 @@ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, unsigned char align, unsigned long tag, resource_t *stolen_base); + +/* Steals memory from the last available entry in the list of given ranges as per the + * constraints: + * limit = Upper bound for the memory range to steal (Inclusive). + * size = Requested size for the stolen memory. + * align = Required alignment(log 2) for the starting address of the stolen memory. + * tag = Use a range that matches the given tag. + * + * If the constraints can be satisfied, this function creates a hole in the memrange, + * writes the base address of that hole to stolen_base and returns true. Otherwise it returns + * false. */ +bool memranges_steal_last(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base); + #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 39f502c..4b13b00 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -376,17 +376,27 @@ return r->next; } +enum { + STEAL_FIRST_AVAILABLE, + STEAL_LAST_AVAILABLE, +} + /* Find a range entry that satisfies the given constraints to fit a hole that matches the - * required alignment, is big enough, does not exceed the limit and has a matching tag. */ + * required alignment, is big enough, does not exceed the limit and has a matching tag. + * Depending upon the value of "steal_from", this function either returns the first range entry + * that satisfies the constraints (STEAL_FIRST_AVAILABLE) or the last range entry that + * satisfies the constrains (STEAL_LAST_AVAILABLE). */ static const struct range_entry *memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag) + unsigned char align, unsigned long tag, + int steal_from) { const struct range_entry *r; + const struct range_entry *last_entry = NULL; resource_t base, end; if (size == 0) - return NULL; + return false; memranges_each_entry(r, ranges) { @@ -407,17 +417,27 @@ if (end > limit) break; - return r; + last_entry = r; + + /* + * If caller wants to steal from the first available range, then break and + * return the found entry. + */ + if (steal_from == STEAL_FIRST_AVAILABLE) + break; } - return NULL; + return last_entry; } -bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base) +static bool __memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base, + int steal_from) { resource_t base; - const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + const struct range_entry *r; + + r = memranges_find_entry(ranges, limit, size, align, tag, steal_from); if (r == NULL) return false; @@ -428,4 +448,19 @@ *stolen_base = base; return true; + +} + +bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base) +{ + return __memranges_steal(ranges, limit, size, align, tag, stolen_base, + STEAL_FIRST_AVAILABLE); +} + +bool memranges_steal_last(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, resource_t *stolen_base) +{ + return __memranges_steal(ranges, limit, size, align, tag, stolen_base, + STEAL_LAST_AVAILABLE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c07e587597b44306857f0e52eb47b330ca3b1b Gerrit-Change-Number: 41418 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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