coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers
by Michael Niewöhner (Code Review) 27 Nov '20

27 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48087 to look at the new patch set (#6). Change subject: mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers ...................................................................... mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e --- M src/mainboard/supermicro/x11-lga1151-series/Makefile.inc M src/mainboard/supermicro/x11-lga1151-series/bootblock.c A src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h M src/mainboard/supermicro/x11-lga1151-series/mainboard.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c 10 files changed, 100 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48087/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/48087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Gerrit-Change-Number: 48087 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: docs/mb/supermicro/x11-lga-series: Update documentation
by Michael Niewöhner (Code Review) 27 Nov '20

27 Nov '20

Hello Felix Singer, build bot (Jenkins), Bill XIE, Paul Menzel, Tim Wawrzynczak, Christian Walter, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48101 to look at the new patch set (#5). Change subject: docs/mb/supermicro/x11-lga-series: Update documentation ...................................................................... docs/mb/supermicro/x11-lga-series: Update documentation - Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726 - Add missing reference to X11SSH-F - Drop TODO reference; there are no TODOs left Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48101/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/48101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5 Gerrit-Change-Number: 48101 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: docs/mb/supermicro/x11-lga-series: Update documentation
by Paul Menzel (Code Review) 27 Nov '20

27 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48101 ) Change subject: docs/mb/supermicro/x11-lga-series: Update documentation ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Thank you for maintaining the documentation. Next time, maybe two commits (general and board specific) would be nice to have. https://review.coreboot.org/c/coreboot/+/48101/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48101/4//COMMIT_MSG@10 PS4, Line 10: CB:35726 No idea, why this is not marked up as a link by Gerrit. https://review.coreboot.org/c/coreboot/+/48101/4//COMMIT_MSG@14 PS4, Line 14: - Drop vanished issue on PCIe warning. : - Drop TODO section, since the TODOs are done. Nit: I’d remove the dots/periods at the end. -- To view, visit https://review.coreboot.org/c/coreboot/+/48101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5 Gerrit-Change-Number: 48101 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Nov 2020 09:47:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Makefile.inc: Move adding mcu FIT entries
by Arthur Heymans (Code Review) 27 Nov '20

27 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46453 ) Change subject: Makefile.inc: Move adding mcu FIT entries ...................................................................... Makefile.inc: Move adding mcu FIT entries This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/cpu/intel/fit/Makefile.inc 2 files changed, 23 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46453/1 diff --git a/Makefile.inc b/Makefile.inc index 882673b..b5b81f0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1133,42 +1133,8 @@ $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif +# Print final FIT table $(IFITTOOL) -f $@.tmp -D -r COREBOOT - -# Second FIT in TOP_SWAP bootblock -ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) -# INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG adds a region as first ucode into the seconds bootblock -ifneq ($(FIT_ENTRY),) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif - $(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT - -endif - -endif # !CONFIG_UPDATE_IMAGE endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 4b540ba..0d1ab60 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -1 +1,23 @@ bootblock-y += fit.S + +ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) +INTERMEDIATE+=add_mcu_fit +add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) + @printf " UPDATE-FIT Microcode\n" + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT + +# Second FIT in TOP_SWAP bootblock +ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) +INTERMEDIATE+=add_ts_mcu_fit +add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) + @printf " UPDATE-FIT Top Swap: Microcode\n" +ifneq ($(FIT_ENTRY),) + $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT +endif + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT +endif # ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) +endif # ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) +endif # ($(CONFIG_UPDATE_IMAGE),y) + + -- To view, visit https://review.coreboot.org/c/coreboot/+/46453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a7764205e0510be89c131058ec56861a479699 Gerrit-Change-Number: 46453 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: WP: soc/mediatek/mt8192: remove dma reset after i2c transfer
by Jg Daolongzhu (Code Review) 27 Nov '20

27 Nov '20

Jg Daolongzhu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47392 ) Change subject: WP: soc/mediatek/mt8192: remove dma reset after i2c transfer ...................................................................... WP: soc/mediatek/mt8192: remove dma reset after i2c transfer remove dma reset after per i2c transfer TEST=Boots correctly on MT8192P1 Signed-off-by: jg_daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Ie5ba7f5514ce415422e586cdfc411382c8b4a539 --- M src/soc/mediatek/common/i2c.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47392/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c old mode 100644 new mode 100755 index 931e36d..ab3551d --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -215,7 +215,7 @@ /* reset the i2c controller for next i2c transfer. */ write32(&regs->softreset, 0x1); - i2c_dma_reset(dma_regs); + //i2c_dma_reset(dma_regs); return ret_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ba7f5514ce415422e586cdfc411382c8b4a539 Gerrit-Change-Number: 47392 Gerrit-PatchSet: 1 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/jasperlake: Enable VT-d and generate DMAR Table
by Meera Ravindranath (Code Review) 27 Nov '20

27 Nov '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47506 ) Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table ...................................................................... soc/intel/jasperlake: Enable VT-d and generate DMAR Table Update UPDs required for the creation of DMAR table. TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47506/1 diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 528ef0f..d420351 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -81,6 +82,17 @@ /* VT-d config */ m_cfg->VtdDisable = 0; + m_cfg->VtdIopEnable = 0x1; + + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + + if (m_cfg->SaIpuEnable) { + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + } m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE]; -- To view, visit https://review.coreboot.org/c/coreboot/+/47506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Gerrit-Change-Number: 47506 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by V Sowmya (Code Review) 27 Nov '20

27 Nov '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Nov 2020 03:40:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by V Sowmya (Code Review) 27 Nov '20

27 Nov '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Nov 2020 03:40:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Zhuohao Lee (Code Review) 27 Nov '20

27 Nov '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47736 ) Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Nov 2020 03:04:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Zhuohao Lee (Code Review) 27 Nov '20

27 Nov '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47736 ) Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Nov 2020 03:03:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020