Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/19705 )
Change subject: drivers/spi_flash: Pass in flash structure to fill in
......................................................................
drivers/spi_flash: Pass in flash structure to fill in
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/cpu/amd/pi/spi.c
M src/drivers/intel/fsp1_0/fastboot_cache.c
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/boot_device_rw_nommap.c
M src/drivers/spi/cbfs_spi.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi_flash.c
M src/drivers/spi/spi_flash_internal.h
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/include/spi_flash.h
M src/northbridge/amd/agesa/oem_s3.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/intel/common/mrc_cache.c
M src/soc/broadcom/cygnus/ddr_init.c
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
M src/soc/intel/fsp_baytrail/nvm.c
M src/soc/mediatek/mt8173/flash_controller.c
M src/southbridge/intel/common/spi.c
25 files changed, 261 insertions(+), 271 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/19705/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/19704 )
Change subject: drivers/spi_flash: Add page_size to struct spi_flash
......................................................................
drivers/spi_flash: Add page_size to struct spi_flash
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/include/spi_flash.h
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
12 files changed, 162 insertions(+), 305 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/19704/2
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19701
to look at the new patch set (#2).
Change subject: lib/boot_device: Add API for getting boot device information
......................................................................
lib/boot_device: Add API for getting boot device information
Add API boot_device_get_info that can be provided by boot device
implementations to return any information that can be useful for the
caller. Return value is void *, so each implementation can return a
pointer to any data structure that is required. By default, NULL is
returned by weak implementation indicating that no information is
available for use by the caller.
BUG=b:38330715
Change-Id: Ia35fc275a2aacf1cf8a3080d5f0da5dc19284206
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/include/boot_device.h
M src/lib/boot_device.c
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19701/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ia35fc275a2aacf1cf8a3080d5f0da5dc19284206
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/19694 )
Change subject: siemens/mc_apl1: Select external 8250 UART
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/19694/1//COMMIT_MSG
Commit Message:
Line 10: output. For this reason we need to activate the 8250 LPC UART.
> So until now, there no console logs could be read, right?
No, for our first mainboards we have both options for console logs. Initialy, we used the MMIO UART, just as on the APL CRBs. But finally our mainboard should use the console output over LPC.
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes