Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16585
-gerrit
commit 826b9279eb99d0260cf295622603dfb1312f3606
Author: Simon Glass <sjg(a)chromium.org>
Date: Sun Sep 4 16:37:04 2016 -0600
selfboot: Move the usable-RAM check into a function
In preparation for making this check optional, move it into its own
function. load_self_segments() is already long and we don't want to make
it longer.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs correctly
Change-Id: If48d2bf485a23f21c5599670e77a7b8b098f1a88
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 2381e02efa2033857ac06acbc4f0c0dd08de1080
Original-Change-Id: I005e5e4d9b2136605bdd95e9060655df7a8238cb
Original-Signed-off-by: Simon Glass <sjg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381092
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/lib/selfboot.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 2fdf8ce..1ce7f94 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -328,23 +328,20 @@ static int build_self_segment_list(
return 1;
}
-static int load_self_segments(
- struct segment *head,
- struct prog *payload)
+static int payload_targets_usable_ram(struct segment *head)
{
- struct segment *ptr;
const unsigned long one_meg = (1UL << 20);
- unsigned long bounce_high = lb_end;
+ struct segment *ptr;
- for(ptr = head->next; ptr != head; ptr = ptr->next) {
+ for (ptr = head->next; ptr != head; ptr = ptr->next) {
if (bootmem_region_targets_usable_ram(ptr->s_dstaddr,
- ptr->s_memsz))
+ ptr->s_memsz))
continue;
if (ptr->s_dstaddr < one_meg &&
(ptr->s_dstaddr + ptr->s_memsz) <= one_meg) {
printk(BIOS_DEBUG,
- "Payload being loaded below 1MiB "
+ "Payload being loaded at below 1MiB "
"without region being marked as RAM usable.\n");
continue;
}
@@ -357,6 +354,19 @@ static int load_self_segments(
return 0;
}
+ return 1;
+}
+
+static int load_self_segments(
+ struct segment *head,
+ struct prog *payload)
+{
+ struct segment *ptr;
+ unsigned long bounce_high = lb_end;
+
+ if (!payload_targets_usable_ram(head))
+ return 0;
+
for(ptr = head->next; ptr != head; ptr = ptr->next) {
/*
* Add segments to bootmem memory map before a bounce buffer is
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16583
-gerrit
commit 9b4023d39bc0a8ebf01e7af50aa4fe4642dda08b
Author: Shunqian Zheng <zhengsq(a)rock-chips.com>
Date: Sat Sep 3 08:29:20 2016 +0800
gru/kevin: set 1.15v for lit cpu 1.5G
In kernel side we set 1.1v for 1.5G, even for coreboot RO,
a higer voltage could be safer, 1.2v now seems too high.
BRANCH=none
BUG=chrome-os-partner:56948
TEST=bootup
Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab
Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df
Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/380896
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/mainboard/google/gru/bootblock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 420fdf1..2214a5c 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -65,7 +65,7 @@ void bootblock_mainboard_early_init(void)
static void speed_up_boot_cpu(void)
{
- pwm_regulator_configure(PWM_REGULATOR_LIT, 1200);
+ pwm_regulator_configure(PWM_REGULATOR_LIT, 1150);
udelay(200);
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16582
-gerrit
commit 47686e92077ba78a3e7236c460a2b314d575964c
Author: Simon Glass <sjg(a)chromium.org>
Date: Sat Aug 27 15:10:30 2016 -0600
rockchip: spi: Improve SPI read efficiency
The SPI driver is quite slow at reading data. For example, with a 24MHz
clock on gru it achieves a read speed of only 13.9Mbps.
We can correct this by reading the status registers once, then reading as
many bytes as are available before checking the status registers again. It
seems likely that a status register read requires synchronizing with the
SPI FIFO clock domain, which takes a while.
BUG=chrome-os-partner:56556
BRANCH=none
TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps
Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9
Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2
Original-Signed-off-by: Simon Glass <sjg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376945
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/rockchip/common/include/soc/spi.h | 7 +++++++
src/soc/rockchip/common/spi.c | 15 +++++++++++----
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h
index 7e9e568..dcaa471 100644
--- a/src/soc/rockchip/common/include/soc/spi.h
+++ b/src/soc/rockchip/common/include/soc/spi.h
@@ -165,6 +165,13 @@ check_member(rockchip_spi, rxdr, 0x800);
#define SPI_OMOD_SLAVE 0x01
/* --------Bit fields in CTRLR0--------end */
+
+/* TXFLR bits */
+#define TXFLR_LEVEL_MASK 0x3f
+
+/* RXFLR bits */
+#define RXFLR_LEVEL_MASK 0x3f
+
/* Bit fields in SR, 7 bits */
#define SR_MASK 0x7f
#define SR_BUSY (1 << 0)
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 6784f5b..f35f915 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -235,11 +235,18 @@ static int do_xfer(struct rockchip_spi *regs, const void *dout,
xferred = 1;
}
+ /*
+ * Try to read as many bytes as are available in one go.
+ * Reading the status registers probably requires
+ * sychronizing with the SPI clock which is pretty slow.
+ */
if (*bytes_in && !(sr & SR_RF_EMPT)) {
- *in_buf = read32(®s->rxdr) & 0xff;
- in_buf++;
- *bytes_in -= 1;
- xferred = 1;
+ int todo = read32(®s->rxflr) & RXFLR_LEVEL_MASK;
+
+ *bytes_in -= todo;
+ xferred = todo;
+ while (todo-- > 0)
+ *in_buf++ = read32(®s->rxdr) & 0xff;
}
min_xfer -= xferred;
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16580
-gerrit
commit 599ed4670494a13f3c025d69e983eb01f807b497
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Sep 1 11:50:18 2016 -0700
google/gru: Fix up PWM regulator ranges
We did yet another small adjustment to the PWM regulator ranges for
Kevin rev6... this patch reflects that in code. Also rewrite code and
descriptions to indicate that these new ranges are not just for Kevin,
but also planned to be used on Gru rev2 and any future Gru derivatives
(which as I understand it is the plan, right?).
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted my rev5, for whatever that's worth...
Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9
Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/379921
Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org>
---
src/mainboard/google/gru/pwm_regulator.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c
index f382b2b..d0cdf43 100644
--- a/src/mainboard/google/gru/pwm_regulator.c
+++ b/src/mainboard/google/gru/pwm_regulator.c
@@ -31,12 +31,12 @@
#define PWM_DESIGN_VOLTAGE_MIN 8000
#define PWM_DESIGN_VOLTAGE_MAX 15000
-/* The min & max design voltages are different after kevin-r6 */
-int kevin_voltage_min_max_r6[][2] = {
- [PWM_REGULATOR_GPU] = {7910, 12139},
- [PWM_REGULATOR_BIG] = {7986, 13057},
- [PWM_REGULATOR_LIT] = {7997, 13002},
- [PWM_REGULATOR_CENTERLOG] = {7996, 10507}
+/* Later boards (Kevin rev6+, Gru rev2+) use different regulator ranges. */
+int pwm_design_voltage_later[][2] = {
+ [PWM_REGULATOR_GPU] = {7858, 12177},
+ [PWM_REGULATOR_BIG] = {7987, 13022},
+ [PWM_REGULATOR_LIT] = {7991, 13037},
+ [PWM_REGULATOR_CENTERLOG] = {8001, 10497}
};
void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt)
@@ -61,9 +61,10 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt)
voltage_min = PWM_DESIGN_VOLTAGE_MIN;
voltage_max = PWM_DESIGN_VOLTAGE_MAX;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) {
- voltage_min = kevin_voltage_min_max_r6[pwm][0];
- voltage_max = kevin_voltage_min_max_r6[pwm][1];
+ if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) &&
+ !(IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) {
+ voltage_min = pwm_design_voltage_later[pwm][0];
+ voltage_max = pwm_design_voltage_later[pwm][1];
}
assert(voltage <= voltage_max && voltage >= voltage_min);
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16578
-gerrit
commit 5b62c90d86322d36a04511fdcb90ec146d099b7e
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Aug 24 19:38:05 2016 -0700
gru: Add watchdog reset support
This patch adds support to reboot the whole board after a hardware
watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to
Veyron.
From my tests it looks like both SRAM and PMUSRAM get preserved across
warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that
makes it easier to deal with in coreboot (PMUSRAM is currently not
mapped as cached, so we don't need to worry about flushing the results
back before reboot).
BRANCH=None
BUG=chrome-os-partner:56600
TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30
seconds. Confirm that system reboots correctly without entering recovery
and we get a HW watchdog event in the eventlog.
Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098
Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/375562
Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org>
---
src/mainboard/google/gru/Makefile.inc | 1 +
src/mainboard/google/gru/bootblock.c | 4 ++++
src/soc/rockchip/rk3399/clock.c | 6 ++++++
src/soc/rockchip/rk3399/include/soc/clock.h | 1 +
src/soc/rockchip/rk3399/include/soc/memlayout.ld | 5 +++++
5 files changed, 17 insertions(+)
diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc
index 9e07a6c..034edde 100644
--- a/src/mainboard/google/gru/Makefile.inc
+++ b/src/mainboard/google/gru/Makefile.inc
@@ -20,6 +20,7 @@ bootblock-y += chromeos.c
bootblock-y += memlayout.ld
bootblock-y += pwm_regulator.c
bootblock-y += boardid.c
+bootblock-y += reset.c
verstage-y += chromeos.c
verstage-y += memlayout.ld
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index ff91e1a..420fdf1 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -24,6 +24,7 @@
#include <soc/i2c.h>
#include <soc/pwm.h>
#include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "board.h"
#include "pwm_regulator.h"
@@ -75,6 +76,9 @@ void bootblock_mainboard_init(void)
{
speed_up_boot_cpu();
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
+
/* Set pinmux and configure spi flashrom. */
write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 428a210..3eeda38 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -834,3 +834,9 @@ void rkclk_configure_emmc(void)
CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
}
+
+int rkclk_was_watchdog_reset(void)
+{
+ /* Bits 5 and 4 are "second" and "first" global watchdog reset. */
+ return read32(&cru_ptr->glb_rst_st) & 0x30;
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index de86ed4..53f16ac 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -112,6 +112,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
void rkclk_configure_tsadc(unsigned int hz);
void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
+int rkclk_was_watchdog_reset(void);
uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index ec12c80..54cfbe1 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -24,6 +24,11 @@ SECTIONS
DMA_COHERENT(0x10000000, 2M)
FRAMEBUFFER(0x10200000, 8M)
+ /* 8K of special SRAM in PMU power domain. */
+ SYMBOL(pmu_sram, 0xFF3B0000)
+ WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4)
+ SYMBOL(epmu_sram, 0xFF3B2000)
+
SRAM_START(0xFF8C0000)
PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
TIMESTAMP(0xFF8C1C00, 1K)
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16577
-gerrit
commit 77b85086f61deec1e48a557469730c3892955c50
Author: Randall Spangler <rspangler(a)chromium.org>
Date: Fri Aug 26 16:01:16 2016 -0700
vboot/vbnv_flash: Binary search to find last used entry
This improves the previous linear search to O(log n). No change in
storage format.
BUG=chromium:640656
BRANCH=none
TEST=Manual
(test empty)
flashrom -i RW_NVRAM -e
Reboot; device should boot normally.
(start using records)
crossystem kern_nv=0xaab0
crossystem recovery_request=1 && reboot
Device should go into recovery mode with reason 1
Reboot again; it should boot normally.
crossystem kern_nv (should still contain 0xaab0)
Repeat steps several times with request=2, 3, etc.
flashrom -i RW_NVRAM -r nvdata
Modify nvdata to copy the first record across all valid
records
flashrom -i RW_NVRAM -w nvdata
Reboot; device should boot normally.
Change-Id: Ieb97563ab92bd1d18a4f6a9e1d20157efe311fb4
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: db9bb2d3927ad57270d7acfd42cf0652102993b1
Original-Change-Id: I1eb5fd9fa6b2ae56833f024bcd3c250147bcc7a1
Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376928
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
src/vboot/vbnv_flash.c | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/src/vboot/vbnv_flash.c b/src/vboot/vbnv_flash.c
index 81c4f08..dd128a9 100644
--- a/src/vboot/vbnv_flash.c
+++ b/src/vboot/vbnv_flash.c
@@ -65,6 +65,7 @@ static int init_vbnv(void)
struct region_device *rdev = &ctx->vbnv_dev;
uint8_t buf[BLOB_SIZE];
uint8_t empty_blob[BLOB_SIZE];
+ int used_below, empty_above;
int offset;
int i;
@@ -78,25 +79,30 @@ static int init_vbnv(void)
for (i = 0; i < BLOB_SIZE; i++)
empty_blob[i] = erase_value();
- offset = 0;
ctx->top_offset = region_device_sz(rdev) - BLOB_SIZE;
- /*
- * after the loop, offset is supposed to point the blob right before
- * the first empty blob, the last blob in the nvram if there is no
- * empty blob, or the base of the region if the nvram has never been
- * used.
- */
- for (i = 0; i <= ctx->top_offset; i += BLOB_SIZE) {
- if (rdev_readat(rdev, buf, i, BLOB_SIZE) < 0) {
+ /* Binary search for the border between used and empty */
+ used_below = 0;
+ empty_above = region_device_sz(rdev) / BLOB_SIZE;
+
+ while (used_below + 1 < empty_above) {
+ int guess = (used_below + empty_above) / 2;
+ if (rdev_readat(rdev, buf, guess * BLOB_SIZE, BLOB_SIZE) < 0) {
printk(BIOS_ERR, "failed to read nvdata\n");
return 1;
}
if (!memcmp(buf, empty_blob, BLOB_SIZE))
- break;
- offset = i;
+ empty_above = guess;
+ else
+ used_below = guess;
}
+ /*
+ * Offset points to the last non-empty blob. Or if all blobs are empty
+ * (nvram is totally erased), point to the first blob.
+ */
+ offset = used_below * BLOB_SIZE;
+
/* reread the nvdata and write it to the cache */
if (rdev_readat(rdev, ctx->cache, offset, BLOB_SIZE) < 0) {
printk(BIOS_ERR, "failed to read nvdata\n");