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New patch to review for coreboot: apple/imac52: add mainboard
by Arthur Heymans
19 Sep '16
19 Sep '16
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16638
-gerrit commit a81b83c6e43ff36bb71be7ac88ef2c5a95cf98bc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 18 20:15:45 2016 +0200 apple/imac52: add mainboard The macbook21 rom works on iMac5,2 desktop computer. Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/imac52/Kconfig | 7 +++++++ src/mainboard/apple/imac52/Kconfig.name | 2 ++ src/mainboard/apple/imac52/board_info.txt | 8 ++++++++ src/mainboard/apple/macbook21/Kconfig | 2 +- 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/mainboard/apple/imac52/Kconfig b/src/mainboard/apple/imac52/Kconfig new file mode 100644 index 0000000..ba2ff95 --- /dev/null +++ b/src/mainboard/apple/imac52/Kconfig @@ -0,0 +1,7 @@ +if BOARD_APPLE_IMAC52 + +config MAINBOARD_PART_NUMBER + string + default "iMac5,2" + +endif diff --git a/src/mainboard/apple/imac52/Kconfig.name b/src/mainboard/apple/imac52/Kconfig.name new file mode 100644 index 0000000..034222b --- /dev/null +++ b/src/mainboard/apple/imac52/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_IMAC52 + bool "iMac5,2" diff --git a/src/mainboard/apple/imac52/board_info.txt b/src/mainboard/apple/imac52/board_info.txt new file mode 100644 index 0000000..918d394 --- /dev/null +++ b/src/mainboard/apple/imac52/board_info.txt @@ -0,0 +1,8 @@ +Board name: iMac5,2 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Clone of: apple/macbook21 +Release year: 2007 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index e653c08..ebf3954 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -1,4 +1,4 @@ -if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 +if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y
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Patch set updated for coreboot: southbridge/amd: Add space around operators
by HAOUAS Elyes
19 Sep '16
19 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16637
-gerrit commit da73fadedde7e9ec291c2b4d6508eda87c0fd64a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 18 19:18:56 2016 +0200 southbridge/amd: Add space around operators Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 4 ++-- src/southbridge/amd/agesa/hudson/imc.c | 6 ++--- src/southbridge/amd/agesa/hudson/ramtop.c | 4 ++-- src/southbridge/amd/amd8111/amd8111_smbus.h | 4 ++-- src/southbridge/amd/cimx/sb700/lpc.c | 2 +- src/southbridge/amd/cimx/sb800/ramtop.c | 4 ++-- src/southbridge/amd/cs5535/chipsetinit.c | 28 +++++++++++----------- src/southbridge/amd/cs5535/cs5535.c | 4 ++-- src/southbridge/amd/cs5536/pirq.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 4 ++-- src/southbridge/amd/pi/hudson/enable_usbdebug.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 24 +++++++++---------- src/southbridge/amd/sb600/hda.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 6 ++--- src/southbridge/amd/sb700/enable_usbdebug.c | 2 +- src/southbridge/amd/sb700/hda.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/reset.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 8 +++---- src/southbridge/amd/sb800/enable_usbdebug.c | 4 ++-- src/southbridge/amd/sb800/hda.c | 2 +- 22 files changed, 62 insertions(+), 62 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1cdaa05..a5f46be 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -94,7 +94,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -107,7 +107,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 5874c37..fce7f5b 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 4da6814..049eca95 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -66,12 +66,12 @@ void enable_imc_thermal_zone(void) regs[0] = 0; regs[1] = 0; FunNum = Fun_80; - for (i=0; i<=1; i++) + for (i = 0; i <= 1; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); - for (i=2; i<=9; i++) + for (i = 2; i <= 9; i++) ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); /* enable thermal zone 0 */ @@ -79,7 +79,7 @@ void enable_imc_thermal_zone(void) regs[0] = 0; regs[1] = 0; FunNum = Fun_81; - for (i=0; i<=9; i++) + for (i = 0; i <= 9; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index e76a0c4..567cd12 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index bf0b037..f82bb19 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -267,7 +267,7 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned } /* read data block */ - for (i=0; i<msglen && i<bytes; i++) { + for (i = 0; i < msglen && i < bytes; i++) { buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; } /* empty fifo */ @@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne outw(bytes, smbus_io_base + SMBHSTDAT); /* set the data block */ - for (i=0; i<bytes; i++) { + for (i = 0; i < bytes; i++) { outw(buf[i], smbus_io_base + SMBHSTFIFO); } diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 60c07cb..1639f08 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -29,7 +29,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index c1ea53e..44a4960 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index a6c0084..1b7fe5d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -22,11 +22,11 @@ struct msrinit { /* Master Configuration Register for Bus Masters. */ static struct msrinit SB_MASTER_CONF_TABLE[] = { - { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */ - { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} }, - { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} }, + { USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */ + { USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} }, + { AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} }, /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLIU_SB_GLD_MSR_CONF, 0x0*/ @@ -35,15 +35,15 @@ static struct msrinit SB_MASTER_CONF_TABLE[] = { /* 5535_A3 Clock Gating*/ static struct msrinit CS5535_CLOCK_GATING_TABLE[] = { - { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, - { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { 0, {.hi=0, .lo=0x000000000} } + { USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} }, + { ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { 0, {.hi = 0, .lo = 0x000000000} } }; #ifdef UNUSED_CODE diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 3f6e48f..2868683 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -56,9 +56,9 @@ static void dump_south(struct device *dev) { int i, j; - for (i=0; i<256; i+=16) { + for (i = 0; i < 256; i+=16) { printk(BIOS_DEBUG, "0x%02x: ", i); - for (j=0; j<16; j++) + for (j = 0; j < 16; j++) printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c index 4bb33d5..0352dbc 100644 --- a/src/southbridge/amd/cs5536/pirq.c +++ b/src/southbridge/amd/cs5536/pirq.c @@ -19,7 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index dce1620..29809f1 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -149,7 +149,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -162,7 +162,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 84691eb..787da6b 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 0); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 0); else return PCI_DEV(0, 0x12, 0); diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 78cb837..c2b3d3a 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -110,7 +110,7 @@ MMIORANGE MMIO[8], CreativeMMIO[8]; static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } @@ -127,7 +127,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; MMIORANGE * TempRange; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) { TempRange = AllocMMIO(pMMIO); if (TempRange == 0) return 0x80000000; @@ -148,12 +148,12 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) static u8 FinalizeMMIO(MMIORANGE *pMMIO) { int i, j, n = 0; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Base == pMMIO[i].Limit) { FreeMMIO(&pMMIO[i]); continue; } - for (j=0; j<i; j++) { + for (j = 0; j < i; j++) { if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) { if (pMMIO[i].Base == pMMIO[j].Limit) { pMMIO[j].Limit = pMMIO[i].Limit; @@ -166,7 +166,7 @@ static u8 FinalizeMMIO(MMIORANGE *pMMIO) } } } - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Limit != 0) n++; } return n; @@ -344,7 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Clear vgainfo. */ bpointer = (unsigned char *) &vgainfo; - for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { + for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { *bpointer = 0; bpointer++; } @@ -448,7 +448,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; - vgainfo.ucMemoryType = 3; // 3=ddr3 sp mem, 2=ddr2 sp mem + vgainfo.ucMemoryType = 3; // 3 = ddr3 sp mem, 2 = ddr2 sp mem vgainfo.ulMinSidePortClock = 333*100; #endif @@ -628,7 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; - for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { + for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { #if CONFIG_GFXUMA *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else @@ -662,12 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* clear MMIO and CreativeMMIO. */ bpointer = (unsigned char *)MMIO; - for (i=0; i<sizeof(MMIO); i++) { + for (i = 0; i < sizeof(MMIO); i++) { *bpointer = 0; bpointer++; } bpointer = (unsigned char *)CreativeMMIO; - for (i=0; i<sizeof(CreativeMMIO); i++) { + for (i = 0; i < sizeof(CreativeMMIO); i++) { *bpointer = 0; bpointer++; } @@ -943,11 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev) /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */ /* Init PM timing. */ - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa0+i); nbmc_write_index(nb_dev, 0xc8+i, l_dword); } - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa8+i); nbmc_write_index(nb_dev, 0xcc+i, l_dword); } diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index 748610c..88b242e 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -176,7 +176,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 1aa7be0..ea7eb27 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -814,7 +814,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -827,7 +827,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); @@ -865,7 +865,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xfc, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 2b0f8cc..22f730f 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,7 +27,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==2) + if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index 8497cc5..2253722 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -98,7 +98,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index f138d88..7b53820 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -93,7 +93,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index d0cd4a4..3c44982 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -23,7 +23,7 @@ #define HTIC_BIOSR_Detect (1<<5) #if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 070c1f5..1096159 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -525,7 +525,7 @@ static void sb800_pmio_por_init(void) byte |= 1 << 0; pmio_write(0xB2, byte); - for (i=0; i<sizeof(pm_table)/sizeof(struct pm_entry); i++) { + for (i = 0; i < sizeof(pm_table)/sizeof(struct pm_entry); i++) { byte = pmio_read(pm_table[i].port); byte &= pm_table[i].mask; byte |= pm_table[i].bit; @@ -637,7 +637,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -650,7 +650,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); @@ -676,7 +676,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xfc, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 7a52e1a..3959ea8 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 2d0852e..78e9862 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -100,7 +100,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1);
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New patch to review for coreboot: southbridge/amd: Add space around operators
by HAOUAS Elyes
19 Sep '16
19 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16637
-gerrit commit 389ec8a47538d5bf8ab738aa8d72ad55416e9849 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 18 19:18:56 2016 +0200 southbridge/amd: Add space around operators Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 4 ++-- src/southbridge/amd/agesa/hudson/imc.c | 6 ++--- src/southbridge/amd/agesa/hudson/ramtop.c | 4 ++-- src/southbridge/amd/amd8111/amd8111_smbus.h | 4 ++-- src/southbridge/amd/cimx/sb700/lpc.c | 2 +- src/southbridge/amd/cimx/sb800/ramtop.c | 4 ++-- src/southbridge/amd/cs5535/chipsetinit.c | 28 +++++++++++----------- src/southbridge/amd/cs5535/cs5535.c | 4 ++-- src/southbridge/amd/cs5536/pirq.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 4 ++-- src/southbridge/amd/pi/hudson/enable_usbdebug.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 24 +++++++++---------- src/southbridge/amd/sb600/hda.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 6 ++--- src/southbridge/amd/sb700/enable_usbdebug.c | 2 +- src/southbridge/amd/sb700/hda.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/reset.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 8 +++---- src/southbridge/amd/sb800/enable_usbdebug.c | 4 ++-- src/southbridge/amd/sb800/hda.c | 2 +- 22 files changed, 62 insertions(+), 62 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1cdaa05..a5f46be 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -94,7 +94,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -107,7 +107,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 5874c37..fce7f5b 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 4da6814..26debd5 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -66,12 +66,12 @@ void enable_imc_thermal_zone(void) regs[0] = 0; regs[1] = 0; FunNum = Fun_80; - for (i=0; i<=1; i++) + for (i = 0; i<=1; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); - for (i=2; i<=9; i++) + for (i = 2; i<=9; i++) ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); /* enable thermal zone 0 */ @@ -79,7 +79,7 @@ void enable_imc_thermal_zone(void) regs[0] = 0; regs[1] = 0; FunNum = Fun_81; - for (i=0; i<=9; i++) + for (i = 0; i<=9; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index e76a0c4..567cd12 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index bf0b037..f82bb19 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -267,7 +267,7 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned } /* read data block */ - for (i=0; i<msglen && i<bytes; i++) { + for (i = 0; i < msglen && i < bytes; i++) { buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; } /* empty fifo */ @@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne outw(bytes, smbus_io_base + SMBHSTDAT); /* set the data block */ - for (i=0; i<bytes; i++) { + for (i = 0; i < bytes; i++) { outw(buf[i], smbus_io_base + SMBHSTFIFO); } diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 60c07cb..1639f08 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -29,7 +29,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index c1ea53e..44a4960 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index a6c0084..1b7fe5d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -22,11 +22,11 @@ struct msrinit { /* Master Configuration Register for Bus Masters. */ static struct msrinit SB_MASTER_CONF_TABLE[] = { - { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */ - { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} }, - { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, - { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} }, + { USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */ + { USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} }, + { AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, + { MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} }, /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLIU_SB_GLD_MSR_CONF, 0x0*/ @@ -35,15 +35,15 @@ static struct msrinit SB_MASTER_CONF_TABLE[] = { /* 5535_A3 Clock Gating*/ static struct msrinit CS5535_CLOCK_GATING_TABLE[] = { - { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, - { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, - { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, - { 0, {.hi=0, .lo=0x000000000} } + { USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} }, + { ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} }, + { 0, {.hi = 0, .lo = 0x000000000} } }; #ifdef UNUSED_CODE diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 3f6e48f..2868683 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -56,9 +56,9 @@ static void dump_south(struct device *dev) { int i, j; - for (i=0; i<256; i+=16) { + for (i = 0; i < 256; i+=16) { printk(BIOS_DEBUG, "0x%02x: ", i); - for (j=0; j<16; j++) + for (j = 0; j < 16; j++) printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c index 4bb33d5..0352dbc 100644 --- a/src/southbridge/amd/cs5536/pirq.c +++ b/src/southbridge/amd/cs5536/pirq.c @@ -19,7 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index dce1620..29809f1 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -149,7 +149,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -162,7 +162,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 84691eb..787da6b 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 0); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 0); else return PCI_DEV(0, 0x12, 0); diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 78cb837..c2b3d3a 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -110,7 +110,7 @@ MMIORANGE MMIO[8], CreativeMMIO[8]; static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } @@ -127,7 +127,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; MMIORANGE * TempRange; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) { TempRange = AllocMMIO(pMMIO); if (TempRange == 0) return 0x80000000; @@ -148,12 +148,12 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) static u8 FinalizeMMIO(MMIORANGE *pMMIO) { int i, j, n = 0; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Base == pMMIO[i].Limit) { FreeMMIO(&pMMIO[i]); continue; } - for (j=0; j<i; j++) { + for (j = 0; j < i; j++) { if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) { if (pMMIO[i].Base == pMMIO[j].Limit) { pMMIO[j].Limit = pMMIO[i].Limit; @@ -166,7 +166,7 @@ static u8 FinalizeMMIO(MMIORANGE *pMMIO) } } } - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (pMMIO[i].Limit != 0) n++; } return n; @@ -344,7 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Clear vgainfo. */ bpointer = (unsigned char *) &vgainfo; - for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { + for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { *bpointer = 0; bpointer++; } @@ -448,7 +448,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; - vgainfo.ucMemoryType = 3; // 3=ddr3 sp mem, 2=ddr2 sp mem + vgainfo.ucMemoryType = 3; // 3 = ddr3 sp mem, 2 = ddr2 sp mem vgainfo.ulMinSidePortClock = 333*100; #endif @@ -628,7 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; - for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { + for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { #if CONFIG_GFXUMA *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else @@ -662,12 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* clear MMIO and CreativeMMIO. */ bpointer = (unsigned char *)MMIO; - for (i=0; i<sizeof(MMIO); i++) { + for (i = 0; i < sizeof(MMIO); i++) { *bpointer = 0; bpointer++; } bpointer = (unsigned char *)CreativeMMIO; - for (i=0; i<sizeof(CreativeMMIO); i++) { + for (i = 0; i < sizeof(CreativeMMIO); i++) { *bpointer = 0; bpointer++; } @@ -943,11 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev) /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */ /* Init PM timing. */ - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa0+i); nbmc_write_index(nb_dev, 0xc8+i, l_dword); } - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa8+i); nbmc_write_index(nb_dev, 0xcc+i, l_dword); } diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index 748610c..88b242e 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -176,7 +176,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 1aa7be0..ea7eb27 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -814,7 +814,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -827,7 +827,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); @@ -865,7 +865,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xfc, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 2b0f8cc..22f730f 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,7 +27,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==2) + if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index 8497cc5..2253722 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -98,7 +98,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index f138d88..7b53820 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -93,7 +93,7 @@ void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; - for (i = 0; i<4; i++) { + for (i = 0; i < 4; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index d0cd4a4..3c44982 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -23,7 +23,7 @@ #define HTIC_BIOSR_Detect (1<<5) #if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 070c1f5..1096159 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -525,7 +525,7 @@ static void sb800_pmio_por_init(void) byte |= 1 << 0; pmio_write(0xB2, byte); - for (i=0; i<sizeof(pm_table)/sizeof(struct pm_entry); i++) { + for (i = 0; i < sizeof(pm_table)/sizeof(struct pm_entry); i++) { byte = pmio_read(pm_table[i].port); byte &= pm_table[i].mask; byte |= pm_table[i].bit; @@ -637,7 +637,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); nvram_pos++; @@ -650,7 +650,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { u32 data = *old_dword; int i; - for (i = 0; i<size; i++) { + for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); data |= inb(BIOSRAM_DATA) << (i *8); @@ -676,7 +676,7 @@ unsigned long get_top_of_ram(void) int xnvram_pos = 0xfc, xi; if (acpi_get_sleep_type() != 3) return 0; - for (xi = 0; xi<4; xi++) { + for (xi = 0; xi < 4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 7a52e1a..3959ea8 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -26,9 +26,9 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - if (hcd_idx==3) + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); - else if (hcd_idx==2) + else if (hcd_idx == 2) return PCI_DEV(0, 0x13, 2); else return PCI_DEV(0, 0x12, 2); diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 2d0852e..78e9862 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -100,7 +100,7 @@ static int wait_for_ready(void *base) int timeout = 50; while (timeout--) { - u32 dword=read32(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1);
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New patch to review for coreboot: crossgcc: Add Dockerfile
by Patrick Georgi
19 Sep '16
19 Sep '16
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16636
-gerrit commit 6f96532a760ccf565c6b8097279df7857b6db163 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Sep 18 20:11:15 2016 +0200 crossgcc: Add Dockerfile The dockerfile allows building an image with the current tree's crossgcc code. Change-Id: I59cd85b0acdf8776e3e090742d7f5d89d1c154e7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/crossgcc/Dockerfile | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/util/crossgcc/Dockerfile b/util/crossgcc/Dockerfile new file mode 100644 index 0000000..da3c840 --- /dev/null +++ b/util/crossgcc/Dockerfile @@ -0,0 +1,36 @@ +FROM debian:sid +MAINTAINER Martin Roth <gaumless(a)gmail.com> + +RUN \ + useradd -p locked -m coreboot && \ + apt-get -qq update && \ + apt-get -qq upgrade && \ + apt-get -qqy install gcc g++ make patch python diffutils bison flex \ + git doxygen ccache subversion p7zip-full unrar-free \ + m4 wget curl bzip2 vim-common cmake xz-utils pkg-config \ + dh-autoreconf unifont \ + libssl-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ + libyaml-dev libncurses5-dev uuid-dev libusb-dev libftdi-dev \ + libusb-1.0-0-dev libreadline-dev libglib2.0-dev libgmp-dev \ + libelf-dev libxml2-dev libfreetype6-dev && \ + apt-get clean + +COPY buildgcc Makefile* root/coreboot/util/crossgcc/ +COPY patches/ /root/coreboot/util/crossgcc/patches/ +COPY sum/ /root/coreboot/util/crossgcc/sum/ +COPY tarballs/ /root/coreboot/util/crossgcc/tarballs/ + +RUN \ + cd /root/coreboot/util/crossgcc && \ + make all_without_gdb CPUS=$(nproc) DEST=/opt/xgcc && \ + cd /root && \ + rm -rf coreboot + +RUN mkdir /home/coreboot/.ccache && \ + chown coreboot:coreboot /home/coreboot/.ccache && \ + mkdir /home/coreboot/cb_build && \ + chown coreboot:coreboot /home/coreboot/cb_build +VOLUME /home/coreboot/.ccache + +ENV PATH $PATH:/opt/xgcc/bin +USER coreboot
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New patch to review for coreboot: southbridge/via: Add space around operators
by HAOUAS Elyes
19 Sep '16
19 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16635
-gerrit commit fd5aa25395c42df6fbcf29385cebbccd3484c2c0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 18 19:07:40 2016 +0200 southbridge/via: Add space around operators Change-Id: Ib48c98bb161b92b28497df26fcfd0eae2c6829df Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/via/k8t890/pcie.c | 2 +- src/southbridge/via/vt8237r/pirq.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c index 25254c3..cc39f57 100644 --- a/src/southbridge/via/k8t890/pcie.c +++ b/src/southbridge/via/k8t890/pcie.c @@ -60,7 +60,7 @@ static void pcie_common_init(struct device *dev) /* Wait up to 100ms for link to come up */ up = 0; - for (i=0; i<1000; i++) { + for (i = 0; i < 1000; i++) { if (pci_read_config16(dev, 0x52) & (1<<13)) { up = 1; break; diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c index 4687e82..ec393b4 100644 --- a/src/southbridge/via/vt8237r/pirq.c +++ b/src/southbridge/via/vt8237r/pirq.c @@ -21,7 +21,7 @@ #include <device/pci_ids.h> #include <pc80/i8259.h> -#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1) void pirq_assign_irqs(const unsigned char route[4]) { device_t pdev;
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Patch set updated for coreboot: i945/gma.c: use linux code to calculate divisors
by Arthur Heymans
19 Sep '16
19 Sep '16
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16504
-gerrit commit bca25d5c60339956cde0d07152a586ec3e47a03a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c: use linux code to calculate divisors The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 83 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 02caa0a..b2ab3cf 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -26,6 +26,7 @@ #include <string.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <commonlib/helpers.h> #include "i945.h" #include "chip.h" @@ -43,7 +44,7 @@ #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 -#define BASE_FREQUENCY 120000 +#define BASE_FREQUENCY 100000 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT @@ -85,10 +86,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; - u32 candp1, candn; - u32 best_delta = 0xffffffff; + u32 smallest_err = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -158,43 +159,39 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom - + BASE_FREQUENCY / 2) / BASE_FREQUENCY; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (BASE_FREQUENCY * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* p2 divisor must 7 for dual channel LVDS */ + /* and 14 for single channel LVDS */ + pixel_p2 = mode->lvds_dual_channel ? 7 : 14; + target_frequency = mode->pixel_clock; + + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < smallest_err) { + smallest_err = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } } } } - if (best_delta == 0xffffffff) { + if (smallest_err == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } @@ -216,8 +213,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); @@ -242,8 +239,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS @@ -252,8 +249,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | @@ -261,8 +257,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) - | (pixel_p1 << 16) - | (pixel_p1)); + | (0x10000 << pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16)
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Patch set updated for coreboot: src/mainboard: Add space around operators
by HAOUAS Elyes
19 Sep '16
19 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16616
-gerrit commit 283c7c2863a3fde578e4fef1818cb5d42ada22eb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Sep 16 20:49:38 2016 +0200 src/mainboard: Add space around operators Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/a-trend/atc-6220/irq_tables.c | 14 ++-- src/mainboard/a-trend/atc-6240/irq_tables.c | 14 ++-- src/mainboard/abit/be6-ii_v2_0/irq_tables.c | 18 ++--- src/mainboard/adi/rcc-dff/irq_tables.c | 26 ++++---- src/mainboard/advansus/a785e-i/romstage.c | 2 +- src/mainboard/amd/bimini_fam10/romstage.c | 2 +- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 8 +-- src/mainboard/amd/dbm690t/fadt.c | 6 +- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dbm690t/romstage.c | 4 +- src/mainboard/amd/dinar/fadt.c | 2 +- src/mainboard/amd/dinar/gpio.c | 6 +- src/mainboard/amd/dinar/gpio.h | 24 +++---- src/mainboard/amd/inagua/BiosCallOuts.c | 6 +- src/mainboard/amd/inagua/broadcom.c | 26 ++++---- src/mainboard/amd/lamar/BiosCallOuts.c | 8 +-- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 4 +- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- src/mainboard/amd/persimmon/BiosCallOuts.c | 4 +- src/mainboard/amd/pistachio/fadt.c | 6 +- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 4 +- src/mainboard/amd/rumba/irq_tables.c | 6 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 8 +-- src/mainboard/amd/serengeti_cheetah/fadt.c | 8 +-- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 30 ++++----- src/mainboard/amd/serengeti_cheetah/romstage.c | 24 +++---- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 8 +-- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 8 +-- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 8 +-- .../amd/serengeti_cheetah_fam10/irq_tables.c | 2 +- .../amd/serengeti_cheetah_fam10/mptable.c | 34 +++++----- .../amd/serengeti_cheetah_fam10/romstage.c | 12 ++-- src/mainboard/amd/south_station/BiosCallOuts.c | 6 +- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 6 +- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/amd/torpedo/gpio.c | 6 +- src/mainboard/amd/torpedo/gpio.h | 24 +++---- src/mainboard/amd/union_station/BiosCallOuts.c | 6 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 4 +- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +- src/mainboard/asus/a8v-e_se/romstage.c | 4 +- src/mainboard/asus/k8v-x/mainboard.c | 4 +- src/mainboard/asus/kcma-d8/acpi_tables.c | 2 +- src/mainboard/asus/kcma-d8/irq_tables.c | 2 +- src/mainboard/asus/kcma-d8/mptable.c | 2 +- src/mainboard/asus/kcma-d8/romstage.c | 10 +-- src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- src/mainboard/asus/kgpe-d16/acpi_tables.c | 2 +- src/mainboard/asus/kgpe-d16/irq_tables.c | 2 +- src/mainboard/asus/kgpe-d16/mptable.c | 2 +- src/mainboard/asus/kgpe-d16/romstage.c | 10 +-- src/mainboard/asus/m2v/irq_tables.c | 4 +- src/mainboard/asus/m2v/mainboard.c | 4 +- src/mainboard/asus/m2v/romstage.c | 8 +-- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/asus/m5a88-v/romstage.c | 2 +- src/mainboard/asus/mew-am/irq_tables.c | 16 ++--- src/mainboard/asus/mew-vm/irq_tables.c | 24 +++---- src/mainboard/asus/p2b-f/irq_tables.c | 14 ++-- src/mainboard/asus/p2b/irq_tables.c | 12 ++-- src/mainboard/asus/p3b-f/irq_tables.c | 16 ++--- src/mainboard/avalue/eax-785e/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/irq_tables.c | 14 ++-- src/mainboard/bcom/winnetp680/irq_tables.c | 20 +++--- src/mainboard/bcom/winnetp680/romstage.c | 4 +- src/mainboard/biostar/m6tba/irq_tables.c | 14 ++-- src/mainboard/broadcom/blast/mptable.c | 42 ++++++------ src/mainboard/broadcom/blast/romstage.c | 4 +- .../compaq/deskpro_en_sff_p600/irq_tables.c | 10 +-- src/mainboard/digitallogic/msm800sev/irq_tables.c | 20 +++--- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/emulation/qemu-i440fx/irq_tables.c | 14 ++-- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/getac/p470/irq_tables.c | 38 +++++------ src/mainboard/getac/p470/romstage.c | 4 +- src/mainboard/gigabyte/ga-6bxc/irq_tables.c | 12 ++-- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 8 +-- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 8 +-- src/mainboard/gigabyte/m57sli/fanctl.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 14 ++-- src/mainboard/gigabyte/m57sli/romstage.c | 8 +-- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- src/mainboard/google/butterfly/chromeos.c | 2 +- src/mainboard/google/butterfly/hda_verb.c | 12 ++-- src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/cyan/spd/spd.c | 6 +- src/mainboard/google/falco/Makefile.inc | 16 ++--- src/mainboard/google/falco/gma.c | 2 +- src/mainboard/google/falco/i915io.c | 4 +- src/mainboard/google/guado/lan.c | 2 +- src/mainboard/google/guado/romstage.c | 4 +- src/mainboard/google/guado/smihandler.c | 8 +-- src/mainboard/google/jecht/lan.c | 2 +- src/mainboard/google/link/i915.c | 26 ++++---- src/mainboard/google/link/i915io.c | 16 ++--- src/mainboard/google/link/i915io.h | 2 +- src/mainboard/google/ninja/lan.c | 2 +- src/mainboard/google/panther/lan.c | 2 +- src/mainboard/google/peach_pit/mainboard.c | 6 +- src/mainboard/google/peppy/gma.c | 2 +- src/mainboard/google/rikku/lan.c | 2 +- src/mainboard/google/rikku/romstage.c | 4 +- src/mainboard/google/rikku/smihandler.c | 8 +-- src/mainboard/google/stout/mainboard.c | 2 +- src/mainboard/google/tidus/lan.c | 2 +- src/mainboard/google/tidus/led.c | 8 +-- src/mainboard/hp/dl145_g1/acpi_tables.c | 4 +- src/mainboard/hp/dl145_g1/fadt.c | 12 ++-- src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 +- src/mainboard/hp/dl145_g1/irq_tables.c | 2 +- src/mainboard/hp/dl145_g1/romstage.c | 30 ++++----- src/mainboard/hp/dl145_g3/get_bus_conf.c | 6 +- src/mainboard/hp/dl145_g3/irq_tables.c | 42 ++++++------ src/mainboard/hp/dl145_g3/mptable.c | 38 +++++------ src/mainboard/hp/dl145_g3/romstage.c | 22 +++---- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 6 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 30 ++++----- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibase/mb899/irq_tables.c | 38 +++++------ src/mainboard/ibase/mb899/romstage.c | 16 ++--- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c | 18 ++--- src/mainboard/intel/bayleybay_fsp/romstage.c | 2 +- src/mainboard/intel/d945gclf/irq_tables.c | 38 +++++------ src/mainboard/intel/eagleheights/debug.c | 6 +- src/mainboard/intel/littleplains/irq_tables.c | 26 ++++---- src/mainboard/intel/minnowmax/gpio.c | 2 +- src/mainboard/intel/mohonpeak/irq_tables.c | 26 ++++---- src/mainboard/intel/mtarvon/mptable.c | 26 ++++---- src/mainboard/intel/stargo2/gpio.h | 8 +-- src/mainboard/intel/truxton/mptable.c | 34 +++++----- src/mainboard/intel/wtm2/graphics.c | 2 +- src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 8 +-- src/mainboard/iwill/dk8_htx/fadt.c | 8 +-- src/mainboard/iwill/dk8_htx/irq_tables.c | 2 +- src/mainboard/iwill/dk8_htx/mptable.c | 42 ++++++------ src/mainboard/iwill/dk8_htx/romstage.c | 12 ++-- src/mainboard/jetway/j7f2/irq_tables.c | 20 +++--- src/mainboard/jetway/j7f2/romstage.c | 4 +- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 4 +- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/irq_tables.c | 38 +++++------ src/mainboard/kontron/986lcd-m/romstage.c | 32 ++++----- src/mainboard/kontron/kt690/fadt.c | 6 +- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 4 +- src/mainboard/lenovo/t430s/hda_verb.c | 12 ++-- src/mainboard/lenovo/t530/hda_verb.c | 12 ++-- src/mainboard/lenovo/x230/hda_verb.c | 12 ++-- src/mainboard/lippert/frontrunner-af/mainboard.c | 4 +- src/mainboard/lippert/frontrunner/irq_tables.c | 6 +- src/mainboard/lippert/hurricane-lx/mainboard.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 4 +- src/mainboard/lippert/literunner-lx/mainboard.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 6 +- src/mainboard/lippert/roadrunner-lx/mainboard.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +- src/mainboard/lippert/spacerunner-lx/devicetree.cb | 2 +- src/mainboard/lippert/spacerunner-lx/mainboard.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +- src/mainboard/lippert/toucan-af/mainboard.c | 4 +- src/mainboard/msi/ms6119/irq_tables.c | 14 ++-- src/mainboard/msi/ms6147/irq_tables.c | 16 ++--- src/mainboard/msi/ms6178/irq_tables.c | 8 +-- src/mainboard/msi/ms9185/mptable.c | 40 ++++++------ src/mainboard/msi/ms9185/romstage.c | 10 +-- src/mainboard/msi/ms9282/mptable.c | 10 +-- src/mainboard/msi/ms9282/romstage.c | 14 ++-- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 10 +-- src/mainboard/msi/ms9652_fam10/mptable.c | 10 +-- src/mainboard/msi/ms9652_fam10/romstage.c | 4 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 4 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 8 +-- src/mainboard/rca/rm4100/irq_tables.c | 16 ++--- src/mainboard/roda/rk886ex/irq_tables.c | 38 +++++------ src/mainboard/roda/rk886ex/m3885.c | 6 +- src/mainboard/roda/rk886ex/m3885.h | 76 +++++++++++----------- src/mainboard/roda/rk886ex/mainboard.c | 6 +- src/mainboard/roda/rk886ex/romstage.c | 4 +- src/mainboard/samsung/lumpy/gpio.c | 8 +-- src/mainboard/samsung/stumpy/romstage.c | 6 +- src/mainboard/samsung/stumpy/smihandler.c | 12 ++-- src/mainboard/siemens/mc_tcu3/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/fadt.c | 6 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 4 +- src/mainboard/sunw/ultra40/mptable.c | 32 ++++----- src/mainboard/sunw/ultra40/romstage.c | 18 ++--- src/mainboard/sunw/ultra40m2/mptable.c | 4 +- src/mainboard/sunw/ultra40m2/romstage.c | 8 +-- src/mainboard/supermicro/h8dme/mptable.c | 18 ++--- src/mainboard/supermicro/h8dme/romstage.c | 6 +- src/mainboard/supermicro/h8dmr/mptable.c | 18 ++--- src/mainboard/supermicro/h8dmr/romstage.c | 12 ++-- .../supermicro/h8dmr_fam10/get_bus_conf.c | 6 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 10 +-- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/fadt.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- .../supermicro/h8qme_fam10/get_bus_conf.c | 6 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 10 +-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 10 +-- src/mainboard/supermicro/h8scm/fadt.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- src/mainboard/technexion/tim5690/fadt.c | 6 +- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 4 +- src/mainboard/technexion/tim5690/speaker.c | 4 +- src/mainboard/technexion/tim5690/tn_post_code.c | 68 +++++++++---------- src/mainboard/technexion/tim8690/fadt.c | 6 +- src/mainboard/technexion/tim8690/mainboard.c | 2 +- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 4 +- src/mainboard/thomson/ip1000/irq_tables.c | 16 ++--- src/mainboard/thomson/ip1000/mainboard.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 6 +- src/mainboard/tyan/s2912/mptable.c | 10 +-- src/mainboard/tyan/s2912/romstage.c | 8 +-- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 6 +- src/mainboard/tyan/s2912_fam10/mptable.c | 10 +-- src/mainboard/tyan/s2912_fam10/romstage.c | 6 +- src/mainboard/tyan/s8226/BiosCallOuts.c | 4 +- src/mainboard/tyan/s8226/fadt.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 2 +- src/mainboard/via/epia-cn/irq_tables.c | 18 ++--- src/mainboard/via/epia-cn/romstage.c | 4 +- src/mainboard/via/pc2500e/irq_tables.c | 20 +++--- src/mainboard/winent/mb6047/mptable.c | 10 +-- src/mainboard/winent/mb6047/romstage.c | 2 +- 254 files changed, 1204 insertions(+), 1204 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/irq_tables.c b/src/mainboard/a-trend/atc-6220/irq_tables.c index a5bb224..b8170e9 100644 --- a/src/mainboard/a-trend/atc-6220/irq_tables.c +++ b/src/mainboard/a-trend/atc-6220/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x4e, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/a-trend/atc-6240/irq_tables.c b/src/mainboard/a-trend/atc-6240/irq_tables.c index 3e50af7..baa5d2d 100644 --- a/src/mainboard/a-trend/atc-6240/irq_tables.c +++ b/src/mainboard/a-trend/atc-6240/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x44, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c index 83b710e..71d6305 100644 --- a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c +++ b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c @@ -30,15 +30,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x4b, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x13<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x61, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x6, 0x0}, - {0x00,(0x08<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x7, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x13 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x61, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x6, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x7, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/adi/rcc-dff/irq_tables.c b/src/mainboard/adi/rcc-dff/irq_tables.c index 538478d..5399c46 100644 --- a/src/mainboard/adi/rcc-dff/irq_tables.c +++ b/src/mainboard/adi/rcc-dff/irq_tables.c @@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x0F1C, /* Device */ @@ -42,18 +42,18 @@ const struct irq_routing_table intel_irq_routing_table = { 0x86, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC + {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA + {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA + {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA + {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH + {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD + {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD + {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC } }; diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 55c94a6..45e5d50 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index be381a1..9ea7e44 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index c2f9c83..f46116a 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -292,10 +292,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* Azalia Controller OEM Codec Table Pointer */ FchParams->Azalia.AzaliaPinCfg = TRUE; FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ - .AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, - .AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, - .AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, - .AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 + .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03, + .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03, + .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03, + .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03 }; FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; /* Azalia Controller Front Panel OEM Table Pointer */ diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c index f9768b2..b397f52 100644 --- a/src/mainboard/amd/dbm690t/fadt.c +++ b/src/mainboard/amd/dbm690t/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 261ac9a..76ee056 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 517f75b..26275b6 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c index 977a6ce..1aad0b5 100644 --- a/src/mainboard/amd/dinar/fadt.c +++ b/src/mainboard/amd/dinar/fadt.c @@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index 17097b3..affda6f 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -179,7 +179,7 @@ gpioEarlyInit( RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI - // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -357,7 +357,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO - // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // } @@ -377,7 +377,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO - // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index c61f445..3ac8bfa 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -341,8 +341,8 @@ #define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA #define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD -#define TYPE_GPI (1<<5) -#define TYPE_GPO (0<<5) +#define TYPE_GPI (1 << 5) +#define TYPE_GPO (0 << 5) #define GPIO_00_TYPE TYPE_GPO #define GPIO_01_TYPE TYPE_GPO @@ -578,8 +578,8 @@ #define GPIO_228_TYPE TYPE_GPO #define GPIO_229_TYPE TYPE_GPO -#define GPO_LOW (0<<6) -#define GPO_HI (1<<6) +#define GPO_LOW (0 << 6) +#define GPO_HI (1 << 6) #define GPO_00_LEVEL GPO_HI #define GPO_01_LEVEL GPO_HI @@ -812,8 +812,8 @@ #define GPO_228_LEVEL GPO_LOW #define GPO_229_LEVEL GPO_LOW -#define GPIO_NONSTICKY (0<<2) -#define GPIO_STICKY (1<<2) +#define GPIO_NONSTICKY (0 << 2) +#define GPIO_STICKY (1 << 2) #define GPIO_00_STICKY GPIO_NONSTICKY #define GPIO_01_STICKY GPIO_NONSTICKY @@ -1046,8 +1046,8 @@ #define GPIO_228_STICKY GPIO_NONSTICKY #define GPIO_229_STICKY GPIO_NONSTICKY -#define PULLUP_ENABLE (0<<3) -#define PULLUP_DISABLE (1<<3) +#define PULLUP_ENABLE (0 << 3) +#define PULLUP_DISABLE (1 << 3) #define GPIO_00_PULLUP PULLUP_DISABLE #define GPIO_01_PULLUP PULLUP_DISABLE @@ -1282,8 +1282,8 @@ #define GPIO_228_PULLUP PULLUP_DISABLE #define GPIO_229_PULLUP PULLUP_DISABLE -#define PULLDOWN_ENABLE (1<<4) -#define PULLDOWN_DISABLE (0<<4) +#define PULLDOWN_ENABLE (1 << 4) +#define PULLDOWN_DISABLE (0 << 4) #define GPIO_00_PULLDOWN PULLDOWN_DISABLE #define GPIO_01_PULLDOWN PULLDOWN_DISABLE @@ -1750,7 +1750,7 @@ typedef enum _GPIO_COUNT { - GPIO_00=0, + GPIO_00 = 0, GPIO_01, GPIO_02, GPIO_03, @@ -2227,7 +2227,7 @@ GPIO_SETTINGS gpio_table[]= typedef enum _GEVENT_COUNT { - GEVENT_00=0x60, + GEVENT_00 = 0x60, GEVENT_01, GEVENT_02, GEVENT_03, diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 3a45761..4b64055 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; + Data16 = Data8 << 8; WriteIo8 (0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16 |= Data8; @@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 905f6c3..640f639 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -73,7 +73,7 @@ void broadcom_init(void); * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and * won't say anything about their purpose. Appearently hardware designers are * expected to blindly copy the Inagua reference schematic: GBE_STAT2: - * 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit. + * 0 = activity; GBE_STAT[1:0]: 11 = no link, 10 = 10Mbit, 01 = 100Mbit, 00 = 1Gbit. * * For package processing the 5785 also features a MIPS-based RISC CPU, booting * from an internal ROM. The firmware loads config data and supplements (e.g. to @@ -119,7 +119,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! u16 basic_config; //?, see below u8 checksum; //byte sum of header == 0 u8 unknown2; //?, patch rejected if changed - u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...) + u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) } header; struct { /* Init code */ @@ -197,8 +197,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! /* Bitfield enabling general features/codepaths in the firmware or * selecting support for one of several supported PHYs? * Bits not listed had no appearent effect: - * 14-11: any bit 1=firmware execution seemed delayed - * 10: 0=firmware execution seemed delayed + * 14-11: any bit 1 = firmware execution seemed delayed + * 10: 0 = firmware execution seemed delayed * 9,2,0: select PHY type, affects these registers, probably more * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes * -------+---------------------------------------------------------- @@ -221,7 +221,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * never seen used. Generally, lower values appear to be run earlier. * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60, * 68, 20, 70, 80 to be interpreted in this order. - * All tests were performed with .basic_config=0x0604. + * All tests were performed with .basic_config = 0x0604. */ .init.hunk1_when = 0x10, //only once at RISC CPU reset? /* Instructions are obviously a specialized bytecode interpreted by the @@ -250,7 +250,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) #endif - be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars be(0x06100D38), be(0x00000000), //v1.03 : - | be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| @@ -287,7 +287,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x08380000), //CFR-AF: PHY18| be(0x083C0000), //CFR-AF: PHY1C| #endif - be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0==1 -->skip next 12 bytes + be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode #else @@ -304,9 +304,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY #endif be(0xF7F30116), // IDDQ PHY - be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII - be(0xC4180400), //v1.09 : 400.3=0| - be(0xC3100400), //v1.09 : 400.2=1| + be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII + be(0xC4180400), //v1.09 : 400.3 = 0| + be(0xC3100400), //v1.09 : 400.2 = 1| }, //-->PWRDN_LENGTH! }; @@ -326,10 +326,10 @@ void broadcom_init(void) printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow); /* Halt RISC CPU before uploading the firmware patch */ - for (i=10000; i > 0; i--) { + for (i = 10000; i > 0; i--) { gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state - gec_base[0x5000/4] |= (1<<10); //issue RISC halt - if (gec_base[0x5000/4] | (1<<10)) + gec_base[0x5000/4] |= (1 << 10); //issue RISC halt + if (gec_base[0x5000/4] | (1 << 10)) break; udelay(10); } diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 5112782..2c633e5 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -321,10 +321,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* Azalia Controller OEM Codec Table Pointer */ FchParams->Azalia.AzaliaPinCfg = TRUE; FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ - .AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, - .AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, - .AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, - .AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 + .AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03, + .AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03, + .AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03, + .AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03 }; FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; /* Azalia Controller Front Panel OEM Table Pointer */ diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index c627cf5..708ddbd 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 662e7cf..1e0000e 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 3428aab..1ee6698 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 9a2a9bb..b0b79ab 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -63,10 +63,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c index f9768b2..b397f52 100644 --- a/src/mainboard/amd/pistachio/fadt.c +++ b/src/mainboard/amd/pistachio/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 261ac9a..76ee056 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index c78f0d2..549ad0c 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 1ef4f5f..81579d2 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -36,7 +36,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x2, /* Device */ @@ -45,8 +45,8 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index f75f820..ddc232f 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -37,7 +37,7 @@ unsigned long acpi_fill_madt(unsigned long current) { - u32 gsi_base=0x18; + u32 gsi_base = 0x18; struct mb_sysconf_t *m; @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -149,11 +149,11 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; - if(i<7) { + if(i < 7) { c = (u8) ('4' + i - 1); } else { diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index bd00961..6bb03e9 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -37,13 +37,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0; fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 2fc3ee6..3d9820f 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -124,7 +124,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num++; //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; int j = 0; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 8236e7b..acc4a6c 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { @@ -101,34 +101,34 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); // Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); //Slot 3 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 } //Slot 4 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 } //Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // } //Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 } j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; device_t dev; @@ -141,8 +141,8 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // } } } @@ -152,8 +152,8 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 } } } diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 51fce31..53adf6c 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,8 +38,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -49,11 +49,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -74,10 +74,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#define RC0 ((1<<0)<<8) -#define RC1 ((1<<1)<<8) -#define RC2 ((1<<2)<<8) -#define RC3 ((1<<3)<<8) +#define RC0 ((1 << 0)<<8) +#define RC1 ((1 << 1)<<8) +#define RC2 ((1 << 2)<<8) +#define RC3 ((1 << 3)<<8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* Read FIDVID_STATUS */ msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } @@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 int i; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { activate_spd_rom(&cpu[i]); dump_smbus_registers(); } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 7496a60..d7aaff2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_madt(unsigned long current) { - u32 gsi_base=0x18; + u32 gsi_base = 0x18; struct mb_sysconf_t *m; @@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -138,11 +138,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, /* same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; - if(i<7) { + if(i < 7) { c = (u8) ('4' + i - 1); } else { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 3183a7e..7f54896 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -40,13 +40,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0; fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 66dee18..87ca672 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -103,7 +103,7 @@ void get_bus_conf(void) m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -141,8 +141,8 @@ void get_bus_conf(void) } /* HT chain 1 */ - j=0; - for(i=1; i< sysconf.hc_possible_num; i++) { + j = 0; + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; // check hcid type here @@ -199,7 +199,7 @@ void get_bus_conf(void) m->apicid_8111 = apicid_base + 0; m->apicid_8132_1 = apicid_base + 1; m->apicid_8132_2 = apicid_base + 2; - for(i=0;i<j;i++) { + for(i = 0; i < j; i++) { m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 380510d..4bb03c7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num++; //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; int j = 0; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 7b2e22e..8699294 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v) j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { @@ -103,34 +103,34 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); // Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); //Slot 3 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 } // Slot 4 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 } // Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); // } //Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 } j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; @@ -143,10 +143,10 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj=0; jj<4; jj++) { + for(jj = 0; jj < 4; jj++) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // } } } @@ -156,10 +156,10 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj=0; jj<4; jj++) { + for(jj = 0; jj < 4; jj++) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 } } } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 0c84b6d..1ccdf26 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -51,8 +51,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1 - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void activate_spd_rom(const struct mem_controller *ctrl) @@ -63,11 +63,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7))); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index e68db13..711a0d5 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; + Data16 = Data8 << 8; WriteIo8 (0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16 |= Data8; @@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 68281e7..1faac4d 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 6f5e0a9..b64cef3 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -58,7 +58,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; + Data16 = Data8 << 8; WriteIo8 (0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16 |= Data8; @@ -108,10 +108,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index fba8fc8..b20cfc8 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index b9fe745..ac98557 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -177,7 +177,7 @@ gpioEarlyInit( RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI - // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -355,7 +355,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO -// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) +// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // } @@ -375,7 +375,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO -// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) +// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index f5decb3..f2ceb02 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -341,8 +341,8 @@ #define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA #define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD -#define TYPE_GPI (1<<5) -#define TYPE_GPO (0<<5) +#define TYPE_GPI (1 << 5) +#define TYPE_GPO (0 << 5) #define GPIO_00_TYPE TYPE_GPO #define GPIO_01_TYPE TYPE_GPO @@ -578,8 +578,8 @@ #define GPIO_228_TYPE TYPE_GPO #define GPIO_229_TYPE TYPE_GPO -#define GPO_LOW (0<<6) -#define GPO_HI (1<<6) +#define GPO_LOW (0 << 6) +#define GPO_HI (1 << 6) #define GPO_00_LEVEL GPO_HI #define GPO_01_LEVEL GPO_HI @@ -812,8 +812,8 @@ #define GPO_228_LEVEL GPO_LOW #define GPO_229_LEVEL GPO_LOW -#define GPIO_NONSTICKY (0<<2) -#define GPIO_STICKY (1<<2) +#define GPIO_NONSTICKY (0 << 2) +#define GPIO_STICKY (1 << 2) #define GPIO_00_STICKY GPIO_NONSTICKY #define GPIO_01_STICKY GPIO_NONSTICKY @@ -1046,8 +1046,8 @@ #define GPIO_228_STICKY GPIO_NONSTICKY #define GPIO_229_STICKY GPIO_NONSTICKY -#define PULLUP_ENABLE (0<<3) -#define PULLUP_DISABLE (1<<3) +#define PULLUP_ENABLE (0 << 3) +#define PULLUP_DISABLE (1 << 3) #define GPIO_00_PULLUP PULLUP_DISABLE #define GPIO_01_PULLUP PULLUP_DISABLE @@ -1282,8 +1282,8 @@ #define GPIO_228_PULLUP PULLUP_DISABLE #define GPIO_229_PULLUP PULLUP_DISABLE -#define PULLDOWN_ENABLE (1<<4) -#define PULLDOWN_DISABLE (0<<4) +#define PULLDOWN_ENABLE (1 << 4) +#define PULLDOWN_DISABLE (0 << 4) #define GPIO_00_PULLDOWN PULLDOWN_DISABLE #define GPIO_01_PULLDOWN PULLDOWN_DISABLE @@ -1750,7 +1750,7 @@ typedef enum _GPIO_COUNT { - GPIO_00=0, + GPIO_00 = 0, GPIO_01, GPIO_02, GPIO_03, @@ -2227,7 +2227,7 @@ const GPIO_SETTINGS gpio_table[]= typedef enum _GEVENT_COUNT { - GEVENT_00=0x60, + GEVENT_00 = 0x60, GEVENT_01, GEVENT_02, GEVENT_03, diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index e68db13..711a0d5 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; + Data16 = Data8 << 8; WriteIo8 (0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16 |= Data8; @@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index c8bd9cc..b0bfc5b 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -36,7 +36,7 @@ int spd_read_byte(unsigned int device, unsigned int address) int i; if (device == DIMM0) { - for (i=0; i < (ARRAY_SIZE(spd_table)); i++) { + for (i = 0; i < (ARRAY_SIZE(spd_table)); i++) { if (spd_table[i].address == address) { return spd_table[i].data; } diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 4ca76c0..8ac36a6 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index b4023e0..cbe320b 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 676de22..2e86ff6 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -55,7 +55,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; + Data16 = Data8 << 8; WriteIo8 (0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16 |= Data8; diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index e6b8ef5..b8f631b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -126,8 +126,8 @@ static void sio_init(void) pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_exit_ext_func_mode(GPIO_DEV); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4a33f77..4c74d0f 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -126,8 +126,8 @@ static void sio_init(void) pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_exit_ext_func_mode(GPIO_DEV); diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index 6efbe02..ab5b2c4 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -42,9 +42,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) gpio_in = inl(acpi_io_base + 0x48); /* bit 29 for primary port, clear if unconnected or 80-pin cable */ - res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + res = gpio_in & (1 << 29) ? 0 : VT8237R_IDE0_80PIN_CABLE; /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ - res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + res |= gpio_in & (1 << 8) ? 0 : VT8237R_IDE1_80PIN_CABLE; printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c index 8395b9d..8af85f9 100644 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; uint32_t apicid_sp5100; uint32_t apicid_sr5650; /* create all subtables for processors */ diff --git a/src/mainboard/asus/kcma-d8/irq_tables.c b/src/mainboard/asus/kcma-d8/irq_tables.c index 5dc2d15..fa7b22a 100644 --- a/src/mainboard/asus/kcma-d8/irq_tables.c +++ b/src/mainboard/asus/kcma-d8/irq_tables.c @@ -24,7 +24,7 @@ #include <cpu/amd/amdfam10_sysconf.h> /* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ -#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) +#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15)) #define LNKA 1 #define LNKB 2 diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index 8967560..aff077a 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v) /* Hide IDE */ dword &= ~(0x00080000); - /* dword_ptr |= 1<<22; PIC and APIC co exists */ + /* dword_ptr |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index e06e02b..256cf7e 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -256,7 +256,7 @@ static void execute_memory_test(void) uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); *dataptr = 0x55555555; dataptr = (void *)(start + i + 4); @@ -264,7 +264,7 @@ static void execute_memory_test(void) } printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Testing memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); readback = *dataptr; if (readback != 0x55555555) @@ -281,7 +281,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -301,7 +301,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -499,7 +499,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0889f24..c7fa429 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 8395b9d..8af85f9 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; uint32_t apicid_sp5100; uint32_t apicid_sr5650; /* create all subtables for processors */ diff --git a/src/mainboard/asus/kgpe-d16/irq_tables.c b/src/mainboard/asus/kgpe-d16/irq_tables.c index 5dc2d15..fa7b22a 100644 --- a/src/mainboard/asus/kgpe-d16/irq_tables.c +++ b/src/mainboard/asus/kgpe-d16/irq_tables.c @@ -24,7 +24,7 @@ #include <cpu/amd/amdfam10_sysconf.h> /* Free irqs are 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15 */ -#define IRQBM ((1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15)) +#define IRQBM ((1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 12)|(1 << 14)|(1 << 15)) #define LNKA 1 #define LNKB 2 diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c index c869d31..a55101d 100644 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ b/src/mainboard/asus/kgpe-d16/mptable.c @@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v) /* Hide IDE */ dword &= ~(0x00080000); - /* dword_ptr |= 1<<22; PIC and APIC co exists */ + /* dword_ptr |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index e5550bd..80d1c45 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -297,7 +297,7 @@ static void execute_memory_test(void) uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); *dataptr = 0x55555555; dataptr = (void *)(start + i + 4); @@ -305,7 +305,7 @@ static void execute_memory_test(void) } printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Testing memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); readback = *dataptr; if (readback != 0x55555555) @@ -322,7 +322,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -342,7 +342,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -540,7 +540,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } diff --git a/src/mainboard/asus/m2v/irq_tables.c b/src/mainboard/asus/m2v/irq_tables.c index 6a93d1c..18bebf5 100644 --- a/src/mainboard/asus/m2v/irq_tables.c +++ b/src/mainboard/asus/m2v/irq_tables.c @@ -22,7 +22,7 @@ #include <device/pci_ids.h> /* Free irqs are 3, 5, 10 and 11 */ -#define IRQBM ((1<<3)|(1<<5)|(1<<10)|(1<<11)) +#define IRQBM ((1 << 3)|(1 << 5)|(1 << 10)|(1 << 11)) #define LNKA 1 #define LNKB 2 @@ -44,7 +44,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0, /* Where the interrupt router lies (bus) */ - (0x11<<3)|0, /* Where the interrupt router lies (dev) */ + (0x11 << 3)|0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */ PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */ diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index ca83621..3d538f5c 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -38,9 +38,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) gpio_in = inl(acpi_io_base + 0x48); /* bit 9 for primary port, clear if unconnected or 80-pin cable */ - res = gpio_in & (1<<9) ? 0 : VT8237R_IDE0_80PIN_CABLE; + res = gpio_in & (1 << 9) ? 0 : VT8237R_IDE0_80PIN_CABLE; /* bit 4 for secondary port, clear if unconnected or 80-pin cable */ - res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE; + res |= gpio_in & (1 << 4) ? 0 : VT8237R_IDE1_80PIN_CABLE; printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 9eacecf..c61557b 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -154,10 +154,10 @@ static void m2v_it8712f_gpio_init(void) * pcirst5# -> maybe n/c (untested) * * For software control of PCIRST[1-5]#: - * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control) - * 0x25=0x17 (select gpio function) - * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable - * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable + * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control) + * 0x25 = 0x17 (select gpio function) + * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable + * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable */ giv = gpio_init_data; while (giv->addr) { diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 844fc93..6c081d4 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index e43dbbc..2393e38 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 1630497..28867ee 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c index 85cbd92..34dee31 100644 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ b/src/mainboard/asus/mew-am/irq_tables.c @@ -30,14 +30,14 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xe3, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x08<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x01,(0x09<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x01,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x01,(0x0b<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x1f<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x02<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x1e << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x01,(0x08 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x01,(0x09 << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x01,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x01,(0x0b << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x1f << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x01,(0x02 << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 3d8bebe..5c5e078 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -5,7 +5,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x11 << 3)|0x0, /* Where the interrupt router lies (dev) */ 0xe20, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7120, /* Device */ @@ -15,17 +15,17 @@ static const struct irq_routing_table intel_irq_routing_table = { that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index 11d22a9..9be2bb4 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf9, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, - {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index 93373da..bde4c46 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -30,12 +30,12 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x54, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 6a41eda..b4b3330 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -30,14 +30,14 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x95, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, - {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, + {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index ff1aa9e..0dc2552 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/azza/pt-6ibd/irq_tables.c b/src/mainboard/azza/pt-6ibd/irq_tables.c index dd35f0d..8807792 100644 --- a/src/mainboard/azza/pt-6ibd/irq_tables.c +++ b/src/mainboard/azza/pt-6ibd/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x3c, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x09<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/bcom/winnetp680/irq_tables.c b/src/mainboard/bcom/winnetp680/irq_tables.c index c66e971..0bea6a0 100644 --- a/src/mainboard/bcom/winnetp680/irq_tables.c +++ b/src/mainboard/bcom/winnetp680/irq_tables.c @@ -31,16 +31,16 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x3e, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 0a3ba72..5f6f29a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -48,7 +48,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); - /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -57,7 +57,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80); - /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/biostar/m6tba/irq_tables.c b/src/mainboard/biostar/m6tba/irq_tables.c index 4c42d5e..59e58f6 100644 --- a/src/mainboard/biostar/m6tba/irq_tables.c +++ b/src/mainboard/biostar/m6tba/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xc7, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d283d85..2ecc6af 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -59,11 +59,11 @@ static void *smp_write_config_table(void *v) //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e << 2)|0, apicid_bcm5785[0], 0xf); //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { + for(i = 0; i < 3; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // } @@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts + dword |= (1 << 4); // enable interrupts pci_write_config32(dev, 0x6c, dword); } @@ -85,50 +85,50 @@ static void *smp_write_config_table(void *v) } //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // } //pci slot (on bcm5785) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); // } //onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // } - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // } //onboard Broadcom - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // + for(i = 0; i < 2; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // } // First PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); // } // Second PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); // } // Third PCI-E x1 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); // } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index d7ba383..e687c2e 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -46,8 +46,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" -#define RC0 (6<<8) -#define RC1 (7<<8) +#define RC0 (6 << 8) +#define RC1 (7 << 8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c index 7b14eaf..cafd05e 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c @@ -30,11 +30,11 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x97, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0d<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x00ef8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x63, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x14<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x00ef8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x62, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x00ef8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x63, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x14 << 3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x00ef8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x62, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c index 4398f70..da31394 100644 --- a/src/mainboard/digitallogic/msm800sev/irq_tables.c +++ b/src/mainboard/digitallogic/msm800sev/irq_tables.c @@ -42,7 +42,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x0f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x100b, /* Vendor */ 0x2b, /* Device */ @@ -53,15 +53,15 @@ static const struct irq_routing_table intel_irq_routing_table = { bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, + {0x00,(0x13 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, } }; diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index e801ae3..f7c4b2d 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -16,7 +16,7 @@ #
http://www.arm.com/products/tools/development-boards/versatile-express
# To execute, do: -# export QEMU_AUDIO_DRV=none +# export QEMU_AUDIO_DRV = none # qemu-system-arm -M vexpress-a9 -m 1024M -nographic -bios build/coreboot.rom if BOARD_EMULATION_QEMU_ARMV7 diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c index daa6782..ae9975e 100644 --- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c @@ -5,7 +5,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x01 << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ @@ -14,12 +14,12 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x02 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x03 << 3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x04 << 3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x05 << 3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x06 << 3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 46281ff..63b1833 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -33,7 +33,7 @@ static void qemu_nb_init(device_t dev) uint8_t v = pci_read_config8(dev, 0x59); v |= 0x30; pci_write_config8(dev, 0x59, v); - for (i=0; i<6; i++) + for (i = 0; i < 6; i++) pci_write_config8(dev, 0x5a + i, 0x33); /* This sneaked in here, because Qemu does not diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index 140b73e..07b03c9 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -30,24 +30,24 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } }; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 396a2ec..bbe45ad 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -82,7 +82,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT + lpt_en = 1 << 2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -126,7 +126,7 @@ static void early_superio_config(void) { device_t dev; - dev=PNP_DEV(0x4e, 0x00); + dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x02, 0x0e); // UART power diff --git a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c index bfcca63..2a5e053 100644 --- a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c +++ b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c @@ -30,12 +30,12 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x8, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x07<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 8a955e8..a7962f54 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) PCI_INT(0, sbdn+5, 2, 0x15); // 21 PCI_INT(0, sbdn+8, 0, 0x16); // 22 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_sis966[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<2; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 2; j++) + for(i = 0; i < 4; i++) { PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 8bc71a9..68cbaad 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -89,11 +89,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c index 07a2666..cc0cdca 100644 --- a/src/mainboard/gigabyte/m57sli/fanctl.c +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -75,7 +75,7 @@ static const struct { void init_ec(uint16_t base) { int i; - for (i=0; i<ARRAY_SIZE(sequence); i++) { + for (i = 0; i < ARRAY_SIZE(sequence); i++) { write_index(base, sequence[i].index, sequence[i].value); } } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index e6cb28b..403b969 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -84,9 +84,9 @@ static void *smp_write_config_table(void *v) /* The PCIe slots, each on its own bus */ k = 1; - for(i=0; i<4; i++){ - for(j=7; j>1; j--){ - if(k>3) k=0; + for(i = 0; i < 4; i++){ + for(j = 7; j > 1; j--){ + if(k > 3) k = 0; PCI_INT(j,0,i, 16+k); k++; } @@ -97,10 +97,10 @@ static void *smp_write_config_table(void *v) physical PCI slots are j = 7,8 FireWire is j = 10 */ - k=2; - for(i=0; i<4; i++){ - for(j=6; j<11; j++){ - if(k>3) k=0; + k = 2; + for(i = 0; i < 4; i++){ + for(j = 6; j < 11; j++){ + if(k > 3) k = 0; PCI_INT(1,j,i, 16+k); k++; } diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b1c849b..f8d12c6 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -80,11 +80,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index baf49af..06eaa8c 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index b8ab282..860b1f1 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 43bae3c..9efda6f 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index b25d78e..b2e3356 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; - int lidswitch=0; + int lidswitch = 0; if (!gpio_base) return; diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index caf8b4a..46d3e86 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -37,32 +37,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x103C18F9), /* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), /* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), /* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), /* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), /* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), /* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 2c5170d..dd2f7b5 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -225,7 +225,7 @@ static void mainboard_init(device_t dev) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index c2e9e79..6ab0063 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -113,9 +113,9 @@ void mainboard_fill_spd_data(struct pei_data *ps) /* * Set SPD and memory configuration: - * Memory type: 0=DimmInstalled, - * 1=SolderDownMemory, - * 2=DimmDisabled + * Memory type: 0 = DimmInstalled, + * 1 = SolderDownMemory, + * 2 = DimmDisabled */ if (spd_content != NULL) { ps->spd_data_ch0 = spd_content; diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 34de87a..6ea2284 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -25,14 +25,14 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) -SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010) -SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100) -SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) -SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) -SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID = 000) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID = 001) +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID = 010) +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID = 011) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID = 100) +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID = 101) +SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID = 110) +SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID = 111) SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c index 986d9c3..c76c50e 100644 --- a/src/mainboard/google/falco/gma.c +++ b/src/mainboard/google/falco/gma.c @@ -90,7 +90,7 @@ static void palette(void) unsigned long color = 0; for(i = 0; i < 256; i++, color += 0x010101){ - gtt_write(_LGC_PALETTE_A + (i<<2),color); + gtt_write(_LGC_PALETTE_A + (i << 2),color); } } diff --git a/src/mainboard/google/falco/i915io.c b/src/mainboard/google/falco/i915io.c index 0936de9..5f33586 100644 --- a/src/mainboard/google/falco/i915io.c +++ b/src/mainboard/google/falco/i915io.c @@ -84,8 +84,8 @@ void runio(struct intel_dp *dp) gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a); - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a); + gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a); + gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a); intel_dp_set_bw(dp); intel_dp_set_lane_count(dp); diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c index 041c3f0..fa292ad 100644 --- a/src/mainboard/google/guado/lan.c +++ b/src/mainboard/google/guado/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/guado/romstage.c b/src/mainboard/google/guado/romstage.c index 24acc80..3ae31f0 100644 --- a/src/mainboard/google/guado/romstage.c +++ b/src/mainboard/google/guado/romstage.c @@ -57,8 +57,8 @@ void mainboard_pre_console_init(void) /* Turn On GPIO10.LED */ it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); } diff --git a/src/mainboard/google/guado/smihandler.c b/src/mainboard/google/guado/smihandler.c index d37cc33..0118e6b 100644 --- a/src/mainboard/google/guado/smihandler.c +++ b/src/mainboard/google/guado/smihandler.c @@ -62,14 +62,14 @@ void mainboard_smi_sleep(u8 slp_typ) switch (slp_typ) { case ACPI_S3: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ + 0x01 /* polarity */, 0x01 /* 1 = pullup */, + 0x01 /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 651c8e6..e76994f 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 31249a1..6158f53 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -148,7 +148,7 @@ static void palette(void) unsigned long color = 0; for(i = 0; i < 256; i++, color += 0x010101){ - io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); + io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2)); } } @@ -277,57 +277,57 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, index = run(0); printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe; + auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); - auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0; + auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); index = run(index); printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0; + auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); index = run(index); printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; auxout[1] = 0x01000000; /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; auxout[1] = 0x0a840000; /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ auxout[2] = 0x00000000; auxout[3] = 0x01000000; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; auxout[1] = 0x21000000; /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; auxout[1] = 0x00000000; /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; + auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; auxout[1] = 0x22000000; /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; auxout[1] = 0x00000000; /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); index = run(index); - auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; + auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); index = run(index); - auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; auxout[1] = 0x00000000; /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 5ebb42d..0f8e0f2 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -116,8 +116,8 @@ struct iodef iodefs[] = { {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, - {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, - {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, + {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x00000000, 0}, + {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, {R, 1, "", _DSPAADDR, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, @@ -194,15 +194,15 @@ struct iodef iodefs[] = { {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0}, + {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, {R, 1, "", 0x145d10, 0x2010040c, 0}, {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, @@ -271,8 +271,8 @@ struct iodef iodefs[] = { {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, {R, 1, "", _DSPAADDR, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h index a7e915a..42893ae 100644 --- a/src/mainboard/google/link/i915io.h +++ b/src/mainboard/google/link/i915io.h @@ -18,7 +18,7 @@ /* things that are, strangely, not defined anywhere? */ #define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1<<31) +#define WMx_LP_SR_EN (1 << 31) /* Google Link-specific defines */ /* how many 4096-byte pages do we need for the framebuffer? diff --git a/src/mainboard/google/ninja/lan.c b/src/mainboard/google/ninja/lan.c index dad8692..cea30e8 100644 --- a/src/mainboard/google/ninja/lan.c +++ b/src/mainboard/google/ninja/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 202d8d0..91d882f 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 4cc72f1..f6e785c 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -138,18 +138,18 @@ static const struct parade_write parade_writes[] = { { 0x04, 0x71, 0x2d }, /* * 2.7G CDR settings - * NOF=40LSB for HBR CDR setting + * NOF = 40LSB for HBR CDR setting */ { 0x04, 0x7d, 0x07 }, { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */ { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */ /* * 1.62G CDR settings - * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + * [5:2]NOF = 64LSB [1:0]DCO scale is 2/5 */ { 0x04, 0xc0, 0x12 }, { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */ - { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */ + { 0x04, 0xc2, 0x1c }, /* Fbstep = 100% */ { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */ /* * RPIO Setting diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c index 8110c8b..f3470a4 100644 --- a/src/mainboard/google/peppy/gma.c +++ b/src/mainboard/google/peppy/gma.c @@ -91,7 +91,7 @@ static void palette(void) unsigned long color = 0; for(i = 0; i < 256; i++, color += 0x010101){ - gtt_write(_LGC_PALETTE_A + (i<<2),color); + gtt_write(_LGC_PALETTE_A + (i << 2),color); } } diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c index e5676af..6099bc1 100644 --- a/src/mainboard/google/rikku/lan.c +++ b/src/mainboard/google/rikku/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c index 5f06ed9..b626bdd 100644 --- a/src/mainboard/google/rikku/romstage.c +++ b/src/mainboard/google/rikku/romstage.c @@ -56,8 +56,8 @@ void mainboard_pre_console_init(void) /* Turn On GPIO10.LED */ it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); } diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c index 4331a1f..4649411 100644 --- a/src/mainboard/google/rikku/smihandler.c +++ b/src/mainboard/google/rikku/smihandler.c @@ -61,14 +61,14 @@ void mainboard_smi_sleep(u8 slp_typ) switch (slp_typ) { case ACPI_S3: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ + 0x01 /* polarity */, 0x01 /* 1 = pullup */, + 0x01 /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 4e3839f..ca67759 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID, STOUT_NIC_DEVICE_ID, dev); diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c index 7c03f6c..08205cc 100644 --- a/src/mainboard/google/tidus/lan.c +++ b/src/mainboard/google/tidus/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/tidus/led.c b/src/mainboard/google/tidus/led.c index c0bf332..4c605e6 100644 --- a/src/mainboard/google/tidus/led.c +++ b/src/mainboard/google/tidus/led.c @@ -27,9 +27,9 @@ void set_power_led(u8 led_pin_map, int state) 1 /* set */, 0x01 /* select */, state /* polarity: non-inverting */, - 0x00 /* 0=pulldown */, + 0x00 /* 0 = pulldown */, 0x01 /* output */, - 0x01 /* 1=Simple IO function */, + 0x01 /* 1 = Simple IO function */, led_pin_map, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; @@ -38,9 +38,9 @@ void set_power_led(u8 led_pin_map, int state) 1 /* set */, 0x01 /* select */, 0x01 /* polarity */, - 0x01 /* 1=pullup */, + 0x01 /* 1 = pullup */, 0x01 /* output */, - 0x00, /* 0=Alternate function */ + 0x00, /* 0 = Alternate function */ led_pin_map, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index c85f380..47e0a3a 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -25,7 +25,7 @@ unsigned long acpi_fill_madt(unsigned long current) { - unsigned int gsi_base=0x18; + unsigned int gsi_base = 0x18; struct mb_sysconf_t *m; @@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c index fb0c62b..877cb5b 100644 --- a/src/mainboard/hp/dl145_g1/fadt.c +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0; fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x04; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x04; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; @@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state - fadt->flush_size = 0; // ignored if wbindv=1 in flags - fadt->flush_stride = 0; // ignored if wbindv=1 in flags + fadt->flush_size = 0; // ignored if wbindv = 1 in flags + fadt->flush_stride = 0; // ignored if wbindv = 1 in flags fadt->duty_offset = 1; fadt->duty_width = 3; // 0 means duty cycle not supported // _alrm value 0 means RTC alarm feature not supported diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index 9c35814..da02095 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -52,7 +52,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -60,7 +60,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m = sysconf.mb; sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index 4988ea1..597acca 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; pirq_info++; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 8b5b428..ea0b60c 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -28,12 +28,12 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { /* Set the memreset low. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* Ensure the BIOS has control of the memory lines. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } else { /* Ensure the CPU has control of the memory lines. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17); } } @@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) if (is_cpu_pre_c0()) { udelay(800); /* Set memreset high. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); udelay(90); } } @@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device) { int ret, i; printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device); - i=2; + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } @@ -91,8 +91,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) +#define RC0 ((1 << 1)<<8) +#define RC1 ((1 << 2)<<8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* Read FIDVID_STATUS */ msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } @@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } @@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); int i; - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { activate_spd_rom(&sysinfo->ctrl[i]); } - for(i=RC0;i<=RC1;i<<=1) { + for(i = RC0; i <= RC1; i<<=1) { change_i2c_mux(i); } diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index 87f065d..d69e224 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -78,7 +78,7 @@ void get_bus_conf(void) sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -125,6 +125,6 @@ void get_bus_conf(void) apicid_base = get_apicid_base(3); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - for(i=0;i<3;i++) + for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c index 3e256b7..2088baf 100644 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ b/src/mainboard/hp/dl145_g3/irq_tables.c @@ -9,7 +9,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x0, /* Where the interrupt router lies (bus) */ - (0x2<<3)|0x4, + (0x2 << 3)|0x4, 0, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ @@ -20,26 +20,26 @@ static const struct irq_routing_table intel_irq_routing_table = { bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge - {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb - {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr - {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge - {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA - {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge - //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, - {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet - {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, - {0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge + {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge + {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb + {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr + {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge + {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA + {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge + //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, + {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, + {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet + {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge + //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, + {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot } }; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 5aeb71d..3a784e7 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biederman<ebiderman(a)lnxi.com> + * Copyright (C) 2001 Eric W.Biederman <ebiderman(a)lnxi.com> * * Copyright (C) 2006 AMD * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) device_t dev = 0; int i; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 pci_write_config32(dev, 0x64, dword); } // set GEVENT pins to NO OP @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1<<26); + dword |= (1 << 26); pci_write_config32(dev, 0x64, dword); } } @@ -116,32 +116,32 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); //SATA -/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ -/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ - printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); +/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ +/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ + printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); //USB printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa); //VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7); //PCIE - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe); //IDE // outb(0x02, 0xc00); outb(0x0e, 0xc01); // printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); -// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe); +// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe); //onboard Broadcom GbE - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4); @@ -153,7 +153,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts + dword |= (1 << 4); // enable interrupts printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 12d18cf..1d1195a 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -79,11 +79,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void setup_early_ipmi_serial() { unsigned char result; - char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05}; - char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f}; - char serial_mux1[]={0x0c<<2,0x12,0x04,0x06}; - char serial_mux2[]={0x0c<<2,0x12,0x04,0x03}; - char serial_mux3[]={0x0c<<2,0x12,0x04,0x07}; + char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05}; + char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f}; + char serial_mux1[]={0x0c << 2,0x12,0x04,0x06}; + char serial_mux2[]={0x0c << 2,0x12,0x04,0x03}; + char serial_mux3[]={0x0c << 2,0x12,0x04,0x07}; // earlydbg(0x0d); //set channel access system only @@ -91,19 +91,19 @@ static void setup_early_ipmi_serial() // earlydbg(result); /* //Set serial/modem config - result=ipmi_request(6,serialmodem_conf); + result = ipmi_request(6,serialmodem_conf); earlydbg(result); //Set serial mux 1 - result=ipmi_request(4,serial_mux1); + result = ipmi_request(4,serial_mux1); earlydbg(result); //Set serial mux 2 - result=ipmi_request(4,serial_mux2); + result = ipmi_request(4,serial_mux2); earlydbg(result); //Set serial mux 3 - result=ipmi_request(4,serial_mux3); + result = ipmi_request(4,serial_mux3); earlydbg(result); */ // earlydbg(0x0e); @@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index e323873..68c3881 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -80,7 +80,7 @@ void get_bus_conf(void) sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -124,6 +124,6 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ apicid_base = 0x10; - for(i=0;i<3;i++) + for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 395de57..17e42e4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biederman<ebiderman(a)lnxi.com> + * Copyright (C) 2001 Eric W.Biederman < ebiderman(a)lnxi.com> * * Copyright (C) 2006 AMD * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) device_t dev = 0; int i; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 + dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 pci_write_config32(dev, 0x64, dword); } // set GEVENT pins to NO OP @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x64); - dword |= (1<<26); + dword |= (1 << 26); pci_write_config32(dev, 0x64, dword); } } @@ -113,16 +113,16 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0, m->apicid_bcm5785[0], 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0, m->apicid_bcm5785[0], 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0, m->apicid_bcm5785[2], 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1, m->apicid_bcm5785[2], 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0, m->apicid_bcm5785[2], 0xa); /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ @@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts + dword |= (1 << 4); // enable interrupts printk(BIOS_DEBUG, "6ch: %x\n",dword); pci_write_config32(dev, 0x6c, dword); } diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 84e28f7..39cd0e3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index ab1849d..0e89b59 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b9, /* Device */ @@ -29,24 +29,24 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 - {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } }; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9d2b90a..3fa339f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -87,14 +87,14 @@ static void early_superio_config_w83627ehg(void) pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? - dev=PNP_DEV(0x4e, W83627EHG_SP1); + dev = PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627EHG_SP2); + dev = PNP_DEV(0x4e, W83627EHG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); @@ -102,7 +102,7 @@ static void early_superio_config_w83627ehg(void) // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); @@ -110,27 +110,27 @@ static void early_superio_config_w83627ehg(void) //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627EHG_GPIO2); + dev = PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it - dev=PNP_DEV(0x4e, W83627EHG_GPIO3); + dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - dev=PNP_DEV(0x4e, W83627EHG_FDC); + dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - dev=PNP_DEV(0x4e, W83627EHG_PP); + dev = PNP_DEV(0x4e, W83627EHG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ - dev=PNP_DEV(0x4e, W83627EHG_HWM); + dev = PNP_DEV(0x4e, W83627EHG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 4c74e4e..3f9d7c7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 7b00176..09e4ec7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c index d21a7e0..69dd16d 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c @@ -57,7 +57,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [0] = { .slot = 0x0, /* means also "on board" */ .bus = 0x00, - .devfn = (0x01<<3)|0x0, /* 0x01 is CS5536 */ + .devfn = (0x01 << 3)|0x0, /* 0x01 is CS5536 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQA, @@ -81,7 +81,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [1] = { .slot = 0x0, /* means also "on board" */ .bus = 0x00, - .devfn = (0x0f<<3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */ + .devfn = (0x0f << 3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_NONE, @@ -105,7 +105,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [2] = { .slot = 0x0, /* means also "on board" */ .bus = 0x00, - .devfn = (0x0e<<3)|0x0, /* 0x0e is eth0 */ + .devfn = (0x0e << 3)|0x0, /* 0x0e is eth0 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQD, @@ -129,7 +129,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [3] = { .slot = 0x0, /* means also "on board" */ .bus = 0x00, - .devfn = (0x10<<3)|0x0, /* 0x10 is eth1 */ + .devfn = (0x10 << 3)|0x0, /* 0x10 is eth1 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQB, @@ -153,7 +153,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [4] = { .slot = 0x0, /* means also "on board" */ .bus = 0x00, - .devfn = (0x11<<3)|0x0, /* 0x11 is SATA */ + .devfn = (0x11 << 3)|0x0, /* 0x11 is SATA */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQA, @@ -184,7 +184,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [5] = { .slot = 0x1, /* This is real PCI slot. */ .bus = 0x00, - .devfn = (0x09<<3)|0x0, /* 0x09 is PCI1 */ + .devfn = (0x09 << 3)|0x0, /* 0x09 is PCI1 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQA, @@ -210,7 +210,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [6] = { .slot = 0x2, /* This is real PCI slot. */ .bus = 0x00, - .devfn = (0x0a<<3)|0x0, /* 0x0a is PCI2 */ + .devfn = (0x0a << 3)|0x0, /* 0x0a is PCI2 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQD, @@ -236,7 +236,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [7] = { .slot = 0x3, /* This is real PCI slot. */ .bus = 0x00, - .devfn = (0x0b<<3)|0x0, /* 0x0b is PCI3 */ + .devfn = (0x0b << 3)|0x0, /* 0x0b is PCI3 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQC, @@ -262,7 +262,7 @@ static const struct irq_routing_table intel_irq_routing_table = { [8] = { .slot = 0x4, /* This is real PCI slot. */ .bus = 0x00, - .devfn = (0x0c<<3)|0x0, /* 0x0c is PCI4 */ + .devfn = (0x0c << 3)|0x0, /* 0x0c is PCI4 */ .irq = { [0] = { /* <-- 0 means this is INTA# output from the device or slot */ .link = LINK_PIRQB, diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 56ca33a..1afc517 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -144,7 +144,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { 0x10EC0262, /* Vendor ID/Device IDA */ 0x0000, /* SubSystem ID */ 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1=yes, 2=no) */ + 0x01, /* Front panel support (1 = yes, 2 = no) */ 0x000B, /* Number of Rear Jacks = 11 */ 0x0002 /* Number of Front Jacks = 2 */ }, diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c index 7c87f9f..7342995 100644 --- a/src/mainboard/intel/d945gclf/irq_tables.c +++ b/src/mainboard/intel/d945gclf/irq_tables.c @@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -29,24 +29,24 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } }; diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index 608489b..79ca0a4 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -61,13 +61,13 @@ static inline void siodump(void) unsigned char data; printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { + for (i = 0x10; i <= 0x2d; i++) { print_reg((unsigned char)i); } #if 0 printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { + for (i = 0xf0; i <= 0xff; i++) { print_reg((unsigned char)i); } @@ -82,7 +82,7 @@ static inline void siodump(void) #endif printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { + for (i = 0xf0; i <= 0xf8; i++) { print_reg((unsigned char)i); } printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); diff --git a/src/mainboard/intel/littleplains/irq_tables.c b/src/mainboard/intel/littleplains/irq_tables.c index 538478d..5399c46 100644 --- a/src/mainboard/intel/littleplains/irq_tables.c +++ b/src/mainboard/intel/littleplains/irq_tables.c @@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x0F1C, /* Device */ @@ -42,18 +42,18 @@ const struct irq_routing_table intel_irq_routing_table = { 0x86, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC + {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA + {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA + {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA + {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH + {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD + {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD + {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC } }; diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index d0f1b1f..b17f57c 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -175,7 +175,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */ GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */ GPIO_NC, /* GPIO_S5[04] - No Connect */ - GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/ + GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0 = 1GB 1 = 2GB or 4GB*/ GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c index 538478d..5399c46 100644 --- a/src/mainboard/intel/mohonpeak/irq_tables.c +++ b/src/mainboard/intel/mohonpeak/irq_tables.c @@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x0F1C, /* Device */ @@ -42,18 +42,18 @@ const struct irq_routing_table intel_irq_routing_table = { 0x86, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD - {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA - {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA - {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA - {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH - {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH - {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD - {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD - {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC + {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD + {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA + {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA + {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA + {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH + {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH + {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD + {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD + {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC } }; diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c index 5788e34..ee9d1c2 100644 --- a/src/mainboard/intel/mtarvon/mptable.c +++ b/src/mainboard/intel/mtarvon/mptable.c @@ -47,31 +47,31 @@ static void *smp_write_config_table(void *v) /* Internal PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */ + 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */ + 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */ + 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */ + 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */ + 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */ + 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */ + 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */ + 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */ + 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */ + 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */ + 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */ + 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */ + 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */ /* PCI slot */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, diff --git a/src/mainboard/intel/stargo2/gpio.h b/src/mainboard/intel/stargo2/gpio.h index 25ecfeb..9651655 100644 --- a/src/mainboard/intel/stargo2/gpio.h +++ b/src/mainboard/intel/stargo2/gpio.h @@ -165,9 +165,9 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio37 = GPIO_MODE_NONE, /* Unused */ .gpio38 = GPIO_MODE_GPIO, /* Dev Kit Board Version high bit */ .gpio39 = GPIO_MODE_GPIO, /* Dev Kit Board Version low bit */ - .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N<1> */ - .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N<2> */ - .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N<3> */ + .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N <1> */ + .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N <2> */ + .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N <3> */ .gpio43 = GPIO_MODE_NONE, /* Unused */ .gpio44 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO1_SUS : MLR TODO */ .gpio45 = GPIO_MODE_NONE, /* Unused */ @@ -184,7 +184,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio56 = GPIO_MODE_GPIO, /* CONN_GBE_RESET_N */ .gpio57 = GPIO_MODE_NONE, /* Unused */ .gpio58 = GPIO_MODE_NATIVE, /* PCH_SML1_CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N<0> */ + .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N <0> */ .gpio60 = GPIO_MODE_NONE, /* Unused */ .gpio61 = GPIO_MODE_NATIVE, /* PCH_SUS_STAT_N */ .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK */ diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index f6cf1cf..ca934b3 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -75,50 +75,50 @@ static void *smp_write_config_table(void *v) /* IMCH/IICH PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */ + 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */ + 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ + 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */ + 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */ + 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */ + 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */ if (bus_pea0) { /* PCIe slot 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|0, 0x8, 0x10); + bus_pea0, (0 << 2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|1, 0x8, 0x11); + bus_pea0, (0 << 2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|2, 0x8, 0x12); + bus_pea0, (0 << 2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|3, 0x8, 0x13); + bus_pea0, (0 << 2)|3, 0x8, 0x13); } if (bus_pea1) { /* PCIe slots 1-4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|0, 0x8, 0x10); + bus_pea1, (0 << 2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|1, 0x8, 0x11); + bus_pea1, (0 << 2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|2, 0x8, 0x12); + bus_pea1, (0 << 2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|3, 0x8, 0x13); + bus_pea1, (0 << 2)|3, 0x8, 0x13); } if (bus_aioc) { /* AIOC PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */ + bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */ + bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */ + bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */ } /* There is no extension information... */ diff --git a/src/mainboard/intel/wtm2/graphics.c b/src/mainboard/intel/wtm2/graphics.c index d51184b..46f8ff4 100644 --- a/src/mainboard/intel/wtm2/graphics.c +++ b/src/mainboard/intel/wtm2/graphics.c @@ -23,7 +23,7 @@ void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose) io_i915_write32(0x80000000,0x45400); io_i915_write32(0x00000000,_CURACNTR); - io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR); + io_i915_write32((/* PIPEA */0x0 << 24)|0x00000000,_DSPACNTR); io_i915_write32(0x00000000,_DSPBCNTR); io_i915_write32(0x80000000,CPU_VGACNTRL); io_i915_write32(0x00000000,_DSPASIZE+0xc); diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 9750d08..a5c0c9c 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -219,7 +219,7 @@ void transaction3(unsigned char dev_addr) // sch_SMbus_regs (); //check the status register for busy state - //temp=inb(SMBusBase+SMBHSTSTS); + //temp = inb(SMBusBase+SMBHSTSTS); //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //sch_SMbus_regs (); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 7c8835a..5b2b2b0 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -24,7 +24,7 @@ unsigned long acpi_fill_madt(unsigned long current) { - unsigned int gsi_base=0x18; + unsigned int gsi_base = 0x18; struct mb_sysconf_t *m; @@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -144,11 +144,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; uint8_t c; - if(i<7) { + if(i < 7) { c = (uint8_t) ('4' + i - 1); } else { diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c index 43d7c16..c7d649a 100644 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ b/src/mainboard/iwill/dk8_htx/fadt.c @@ -23,13 +23,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0; fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index e9f13b4..2f1dade 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -111,7 +111,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num++; //pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; int j = 0; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index eecad5c..9361a58 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; switch(sysconf.hcid[i]) { @@ -87,47 +87,47 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); // Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); // Onboard VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12); //Slot 5 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 } //Slot 6 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 } //Slot 1: HTX //Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30 } //Slot 3 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 } //Slot 4 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26 } //Onboard NICS - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24 //Onboard SATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25 j = 0; - for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; device_t dev; @@ -140,8 +140,8 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // } } } @@ -151,8 +151,8 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + for(ii = 0; ii < 4; ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 } } } diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 4cf89b1..fa0c11c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -28,12 +28,12 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { /* Set the memreset low. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 28); /* Ensure the BIOS has control of the memory lines. */ - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 29); } else { /* Ensure the CPU has control of the memory lines. */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 29); } } @@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) if (is_cpu_pre_c0()) { udelay(800); /* Set memreset_high */ - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } } @@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/jetway/j7f2/irq_tables.c b/src/mainboard/jetway/j7f2/irq_tables.c index c66e971..0bea6a0 100644 --- a/src/mainboard/jetway/j7f2/irq_tables.c +++ b/src/mainboard/jetway/j7f2/irq_tables.c @@ -31,16 +31,16 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x3e, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 0de239c..c7e2fe9 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -53,7 +53,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); - /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -62,7 +62,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80); - /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 37caa6e..44c41fd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -66,10 +66,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8 << 8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); - Data16|=Data8; + Data16 |= Data8; AcpiMmioAddr = (uint32_t)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 0db35ce..895057b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -134,7 +134,7 @@ chip northbridge/amd/agesa/family14/root_complex # # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD # with i2cdump tool. -# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. +# Notes: 0xa0 = 0x50*2, 0xa2 = 0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. # register "spdAddrLookup" = " { diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 0afd86e..59e7e9f 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 8c87563..43e88d1 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index 2e59f93..a591668 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -29,24 +29,24 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } }; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 3dcf4cc..e9143a8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -57,7 +57,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT + lpt_en = 1 << 2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -98,7 +98,7 @@ static void early_superio_config_w83627thg(void) { device_t dev; - dev=PNP_DEV(0x2e, W83627THG_SP1); + dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); pnp_write_config(dev, 0x24, 0xc6); // PNPCSV @@ -106,14 +106,14 @@ static void early_superio_config_w83627thg(void) pnp_write_config(dev, 0x29, 0x43); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings - dev=PNP_DEV(0x2e, W83627THG_SP1); + dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x2e, W83627THG_SP2); + dev = PNP_DEV(0x2e, W83627THG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); @@ -121,7 +121,7 @@ static void early_superio_config_w83627thg(void) // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); - dev=PNP_DEV(0x2e, W83627THG_KBC); + dev = PNP_DEV(0x2e, W83627THG_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); @@ -129,33 +129,33 @@ static void early_superio_config_w83627thg(void) // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs pnp_set_enable(dev, 1); - dev=PNP_DEV(0x2e, W83627THG_GPIO2); + dev = PNP_DEV(0x2e, W83627THG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it - dev=PNP_DEV(0x2e, W83627THG_GPIO3); + dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - dev=PNP_DEV(0x2e, W83627THG_FDC); + dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - dev=PNP_DEV(0x2e, W83627THG_PP); + dev = PNP_DEV(0x2e, W83627THG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ - dev=PNP_DEV(0x2e, W83627THG_HWM); + dev = PNP_DEV(0x2e, W83627THG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); @@ -163,7 +163,7 @@ static void early_superio_config_w83627thg(void) pnp_exit_func_mode(dev); - dev=PNP_DEV(0x4e, W83627THG_SP1); + dev = PNP_DEV(0x4e, W83627THG_SP1); pnp_enter_func_mode(dev); pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values @@ -172,22 +172,22 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); + dev = PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 10); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_FDC); + dev = PNP_DEV(0x4e, W83627THG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - dev=PNP_DEV(0x4e, W83627THG_PP); + dev = PNP_DEV(0x4e, W83627THG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - dev=PNP_DEV(0x4e, W83627THG_KBC); + dev = PNP_DEV(0x4e, W83627THG_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c index f9768b2..b397f52 100644 --- a/src/mainboard/kontron/kt690/fadt.c +++ b/src/mainboard/kontron/kt690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 39192b0..8895163 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index cb33e3b..d25799f 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/lenovo/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/hda_verb.c index ee54874..4378341 100644 --- a/src/mainboard/lenovo/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FB), /* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), /* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), /* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), /* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), /* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), /* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 154b314..18094c2 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FA), /* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), /* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), /* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), /* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), /* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), /* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 792579a..cc9e02d 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FA), /* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), /* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), /* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), /* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), /* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), /* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 79c093f..a8cf5c5 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -31,7 +31,7 @@ /* Init SIO GPIOs. */ #define SIO_RUNTIME_BASE 0x0E00 -static const u16 sio_init_table[] = { // hi=offset, lo=value +static const u16 sio_init_table[] = { // hi = offset, lo = value 0x4BA0, // GP1x: COM1/2 control = RS232, no term, max 115200 0x2300, // GP10: COM1 termination = push/pull output 0x2400, // GP11: COM2 termination = push/pull output @@ -70,7 +70,7 @@ static const u16 sio_init_table[] = { // hi=offset, lo=value static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) { __outbyte(SMB0_STATUS, 0x1E); // clear error status - __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out + __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction = out __outbyte(SMB0_HOSTCMD, command); // or destination offset __outbyte(SMB0_DATA0, length); // sent before data __inbyte(SMB0_CONTROL); // reset block data array diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index 2e0d9d6..c431451 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -23,7 +23,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x2, /* Device */ @@ -32,8 +32,8 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c index ffd20d0..3d32113 100644 --- a/src/mainboard/lippert/hurricane-lx/mainboard.c +++ b/src/mainboard/lippert/hurricane-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x00 #endif -static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ 0x805C, /* Unlock zero adjust */ diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 0c9e03a..7e3288f 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -76,7 +76,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -84,7 +84,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xBF27, 0xFF28, 0x2D29, // (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1) + 0xBF27, 0xFF28, 0x2D29, // (GP36 = FAN_CTL3 (PWM), GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE 0x06C8, // config GP12,11 as output, GP10 as input diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c index 1a569e2..e4084b5 100644 --- a/src/mainboard/lippert/literunner-lx/mainboard.c +++ b/src/mainboard/lippert/literunner-lx/mainboard.c @@ -34,7 +34,7 @@ /* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */ #define SIO_GP2X_CONFIG 0x00 -static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index efe322c..2f6aa46 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -115,7 +115,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -123,7 +123,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) + 0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0FB9, // enable pullups on SPI, RS485_EN, COM3_R/TX_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x03C1, // enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN @@ -131,7 +131,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x07C8, // config GP12-10 as output 0x03C9, // config GP21-20 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) + 0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use) }; /* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c index cd83768..1d35ebe 100644 --- a/src/mainboard/lippert/roadrunner-lx/mainboard.c +++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x20 #endif -static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ 0x805C, /* Unlock zero adjust */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index d70e2c1..7e0e2a5 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -52,7 +52,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset 0x9072, // watchdog triggers PWROK, counts seconds @@ -60,13 +60,13 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins - 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) + 0xBF27, 0xFF28, 0x2529, // (GP36 = FAN_CTL3, GP13 = PWROK1) 0x46B8, 0x0CB9, // enable pullups on RS485_EN 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) 0x26C8, // config GP15,12,11 as output; GP14 as input 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) + 0x0DF8, // map GP LED Blinking 1 to GP15 = LIVE_LED (deactivate Simple-I/O to use) }; /* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb index 8619e84..5f5b15b 100644 --- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb +++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb @@ -21,7 +21,7 @@ chip northbridge/amd/lx register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 + register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1 << 31 + Device 0x0F << 11 + Function 3 << 8 register "unwanted_vpci[1]" = "0" # End of list has a zero device pci 8.0 on end # Slot4 device pci 9.0 on end # Slot3 diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c index 4decd0e..b0bc74e 100644 --- a/src/mainboard/lippert/spacerunner-lx/mainboard.c +++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x01 #endif -static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index b3a13ad..85503c5 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -116,7 +116,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -124,12 +124,12 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) + 0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x07C8, // config GP12-10 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) + 0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use) }; /* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index b9c532f..6b51fd2 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -39,7 +39,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) { __outbyte(SMB0_STATUS, 0x1E); // clear error status - __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out + __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction = out __outbyte(SMB0_HOSTCMD, command); // or destination offset __outbyte(SMB0_DATA0, length); // sent before data __inbyte(SMB0_CONTROL); // reset block data array @@ -96,7 +96,7 @@ static void init(struct device *dev) * effect a power cycle and switch to the alternate BIOS chip. * Should be done as late as possible. */ printk(BIOS_INFO, "Sending BIOS alive message\n"); - const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS + const u8 i_am_alive[] = { 0x03 }; //bit2 = SEL_DP0: 0 = DDI2, 1 = LVDS if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive))) printk(BIOS_ERR, "smb_write_blk failed: %d\n", i); diff --git a/src/mainboard/msi/ms6119/irq_tables.c b/src/mainboard/msi/ms6119/irq_tables.c index 496c01f..b97ee90 100644 --- a/src/mainboard/msi/ms6119/irq_tables.c +++ b/src/mainboard/msi/ms6119/irq_tables.c @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x9c, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x14 << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index 2590bb9..458f6ed 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -30,14 +30,14 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x20, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x00<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */ - {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* IDE */ - {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* UHCI */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* AGP bridge */ + {0x00,(0x0e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x14 << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x00 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */ + {0x00,(0x07 << 3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* IDE */ + {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* UHCI */ + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* AGP bridge */ } }; diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c index 2daf255..087d714 100644 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ b/src/mainboard/msi/ms6178/irq_tables.c @@ -30,10 +30,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x1a, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x1f<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x1e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x1f << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 775fdc6c..fccb200 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biederman<ebiderman(a)lnxi.com> + * Copyright (C) 2001 Eric W.Biederman <ebiderman(a)lnxi.com> * * Copyright (C) 2006 AMD * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -76,11 +76,11 @@ static void *smp_write_config_table(void *v) //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf); //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { + for(i = 0; i < 3; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // } @@ -94,52 +94,52 @@ static void *smp_write_config_table(void *v) if(dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts + dword |= (1 << 4); // enable interrupts pci_write_config32(dev, 0x6c, dword); } } //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // } //pci slot (on bcm5785) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); // } //onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // } //onboard Broadcom - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // + for(i = 0; i < 2; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // } // First PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); // } // Second PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); // } // Third PCI-E x1 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); // } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index f6f6859..16eb36f 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -72,8 +72,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" -#define RC0 (0x10<<8) -#define RC1 (0x01<<8) +#define RC0 (0x10 << 8) +#define RC1 (0x01 << 8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 int i; - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { activate_spd_rom(sysinfo->ctrl+i); dump_smbus_registers(); } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index cbad735..4619737 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -99,15 +99,15 @@ static void *smp_write_config_table(void *v) //NIC2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 04c5c36..7d360e3 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -70,10 +70,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) //set GPIO to input mode #define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -98,13 +98,13 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. -#define RC0 (2<<8) -#define RC1 (1<<8) +#define RC0 (2 << 8) +#define RC1 (1 << 8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 39a24dd..0614e1f 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) printk(BIOS_SPEW, "get_bus_conf()\n"); - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -80,7 +80,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -99,7 +99,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -112,10 +112,10 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); } m->apicid_mcp55 = apicid_base+0; } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index eff19c7..7d83c46 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3af4785..e22ec11 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -83,7 +83,7 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } @@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); /* Need to use TMICT to synchronize FID/VID. */ diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index d000b1a..76bb73c 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -58,8 +58,8 @@ static void *smp_write_config_table(void *v) /* Initialize interrupt mapping*/ dword = pci_read_config32(dev, 0x74); - dword &= ~(1<<15); - dword |= 1<<2; + dword &= ~(1 << 15); + dword |= 1 << 2; pci_write_config32(dev, 0x74, dword); dword = 0x43c6c643; diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index cfe5beb..d0966ee 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -81,11 +81,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c index e8ef598..0351b99 100644 --- a/src/mainboard/rca/rm4100/irq_tables.c +++ b/src/mainboard/rca/rm4100/irq_tables.c @@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x24c0, /* Device */ @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ - {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ - {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ - {0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ - {0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ - {0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ - {0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ + {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ + {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ + {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ + {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ + {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ } }; diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index 90ab6b0..a970323 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -30,24 +30,24 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge - {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, - {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, - {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, - {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, - {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, - {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 - {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, - {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } }; diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 6a9b26c..d5a2b70 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -240,7 +240,7 @@ void m3885_configure_multikey(void) m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4)); /* Write Matrix to bank 0 */ - for (i=0; i < ARRAY_SIZE(matrix); i++) { + for (i = 0; i < ARRAY_SIZE(matrix); i++) { m3885_set_proc_ram(i + 0x80, matrix[i]); } @@ -257,7 +257,7 @@ void m3885_configure_multikey(void) printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs); } else { printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs); - for (i=0; i < ARRAY_SIZE(function_ram); i++) { + for (i = 0; i < ARRAY_SIZE(function_ram); i++) { m3885_set_proc_ram(i + offs, function_ram[i]); } } @@ -269,7 +269,7 @@ void m3885_configure_multikey(void) m3885_set_variable(0x0c, kstate5_flags); maxvars = m3885_get_variable(0x00); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); - for (i=0; i<ARRAY_SIZE(variables); i+=3) { + for (i = 0; i < ARRAY_SIZE(variables); i+=3) { if(variables[i + 0] > maxvars) continue; reg8 = m3885_get_variable(variables[i + 0]); diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h index 0fb8294..d2dcb14 100644 --- a/src/mainboard/roda/rk886ex/m3885.h +++ b/src/mainboard/roda/rk886ex/m3885.h @@ -21,50 +21,50 @@ #define M3885_CMDAT2 0x06 #define M3885_CMDAT3 0x07 -#define M3885_GPIO_LEVEL (0<<7) -#define M3885_GPIO_PULSE (1<<7) +#define M3885_GPIO_LEVEL (0 << 7) +#define M3885_GPIO_PULSE (1 << 7) -#define M3885_GPIO_READ (0<<5) -#define M3885_GPIO_SET (1<<5) -#define M3885_GPIO_CLEAR (2<<5) -#define M3885_GPIO_TOGGLE (3<<5) +#define M3885_GPIO_READ (0 << 5) +#define M3885_GPIO_SET (1 << 5) +#define M3885_GPIO_CLEAR (2 << 5) +#define M3885_GPIO_TOGGLE (3 << 5) -#define M3885_GPIO_P14 (0x00<<0) -#define M3885_GPIO_P15 (0x01<<0) -#define M3885_GPIO_P16 (0x02<<0) -#define M3885_GPIO_P17 (0x03<<0) +#define M3885_GPIO_P14 (0x00 << 0) +#define M3885_GPIO_P15 (0x01 << 0) +#define M3885_GPIO_P16 (0x02 << 0) +#define M3885_GPIO_P17 (0x03 << 0) -#define M3885_GPIO_P54 (0x04<<0) -#define M3885_GPIO_P55 (0x05<<0) -#define M3885_GPIO_P56 (0x06<<0) -#define M3885_GPIO_P57 (0x07<<0) +#define M3885_GPIO_P54 (0x04 << 0) +#define M3885_GPIO_P55 (0x05 << 0) +#define M3885_GPIO_P56 (0x06 << 0) +#define M3885_GPIO_P57 (0x07 << 0) -#define M3885_GPIO_P20 (0x08<<0) -#define M3885_GPIO_P21 (0x09<<0) -#define M3885_GPIO_P22 (0x0a<<0) -#define M3885_GPIO_P23 (0x0b<<0) -#define M3885_GPIO_P24 (0x0c<<0) -#define M3885_GPIO_P25 (0x0d<<0) -#define M3885_GPIO_P26 (0x0e<<0) -#define M3885_GPIO_P27 (0x0f<<0) +#define M3885_GPIO_P20 (0x08 << 0) +#define M3885_GPIO_P21 (0x09 << 0) +#define M3885_GPIO_P22 (0x0a << 0) +#define M3885_GPIO_P23 (0x0b << 0) +#define M3885_GPIO_P24 (0x0c << 0) +#define M3885_GPIO_P25 (0x0d << 0) +#define M3885_GPIO_P26 (0x0e << 0) +#define M3885_GPIO_P27 (0x0f << 0) -#define M3885_GPIO_P40 (0x10<<0) -#define M3885_GPIO_P41 (0x11<<0) -#define M3885_GPIO_P42 (0x12<<0) -#define M3885_GPIO_P43 (0x13<<0) -#define M3885_GPIO_P44 (0x14<<0) -#define M3885_GPIO_P45 (0x15<<0) -#define M3885_GPIO_P46 (0x16<<0) -#define M3885_GPIO_P47 (0x17<<0) +#define M3885_GPIO_P40 (0x10 << 0) +#define M3885_GPIO_P41 (0x11 << 0) +#define M3885_GPIO_P42 (0x12 << 0) +#define M3885_GPIO_P43 (0x13 << 0) +#define M3885_GPIO_P44 (0x14 << 0) +#define M3885_GPIO_P45 (0x15 << 0) +#define M3885_GPIO_P46 (0x16 << 0) +#define M3885_GPIO_P47 (0x17 << 0) -#define M3885_GPIO_P60 (0x18<<0) -#define M3885_GPIO_P61 (0x19<<0) -#define M3885_GPIO_P62 (0x1a<<0) -#define M3885_GPIO_P63 (0x1b<<0) -#define M3885_GPIO_P64 (0x1c<<0) -#define M3885_GPIO_P65 (0x1d<<0) -#define M3885_GPIO_P66 (0x1e<<0) -#define M3885_GPIO_P67 (0x1f<<0) +#define M3885_GPIO_P60 (0x18 << 0) +#define M3885_GPIO_P61 (0x19 << 0) +#define M3885_GPIO_P62 (0x1a << 0) +#define M3885_GPIO_P63 (0x1b << 0) +#define M3885_GPIO_P64 (0x1c << 0) +#define M3885_GPIO_P65 (0x1d << 0) +#define M3885_GPIO_P66 (0x1e << 0) +#define M3885_GPIO_P67 (0x1f << 0) void m3885_configure_multikey(void); u8 m3885_gpio(u8 value); diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 1ef2497..1959c32 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -35,7 +35,7 @@ static void backlight_enable(void) /* P56 is Brightness Up, and it needs a Pulse instead of a * Level */ - for (i=0; i < 28; i++) { + for (i = 0; i < 28; i++) { //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56); m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56); } @@ -49,10 +49,10 @@ static void dump_runtime_registers(void) int i; printk(BIOS_DEBUG, "SuperIO runtime register block:\n"); - for (i=0; i<0x10; i++) + for (i = 0; i < 0x10; i++) printk(BIOS_DEBUG, "%02x ", i); printk(BIOS_DEBUG, "\n"); - for (i=0; i<0x10; i++) + for (i = 0; i < 0x10; i++) printk(BIOS_DEBUG, "%02x ", inb(0x600 +i)); printk(BIOS_DEBUG, "\n"); } diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f3af5fa..8de4665 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -68,7 +68,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT + lpt_en = 1 << 2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -113,7 +113,7 @@ static void early_superio_config(void) { device_t dev; - dev=PNP_DEV(0x2e, 0x00); + dev = PNP_DEV(0x2e, 0x00); pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 8e8b936..9d07e64 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -233,9 +233,9 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio41 = GPIO_LEVEL_LOW, .gpio42 = GPIO_LEVEL_LOW, .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ - .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ - .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ + .gpio44 = GPIO_LEVEL_HIGH, /* CTL2 = 1 for USB0 SDP */ + .gpio45 = GPIO_LEVEL_LOW, /* CTL3 = 0 for USB0 SDP */ + .gpio46 = GPIO_LEVEL_HIGH, /* CTL2 = 1 for USB1 SDP */ .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ .gpio49 = GPIO_LEVEL_LOW, @@ -299,7 +299,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ + .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3 = 0 for SDP */ .gpio74 = GPIO_LEVEL_LOW, .gpio75 = GPIO_LEVEL_LOW, }; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 738f1ff..7f7999c 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -144,9 +144,9 @@ static void setup_sio_gpios(void) /* * GPIO45 as LED_POWER# */ - it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - (0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */, + it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); /* diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 215af8f..00148f2 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -36,16 +36,16 @@ void mainboard_smi_sleep(u8 slp_typ) switch (slp_typ) { case ACPI_S3: case ACPI_S4: - it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - (0x1<<5) /* polarity */, (0x1<<5) /* 1=pullup */, - (0x1<<5) /* output */, 0x00, /* 0=Alternate function */ + it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */, + (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, + (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: - it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - (0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */, + it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index c8cc66b..15d949e 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -145,7 +145,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { 0x10EC0262, /* Vendor ID/Device IDA */ 0x0000, /* SubSystem ID */ 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1=yes, 2=no) */ + 0x01, /* Front panel support (1 = yes, 2 = no) */ 0x000B, /* Number of Rear Jacks = 11 */ 0x0002 /* Number of Front Jacks = 2 */ }, diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c index 7d7221d..360a427 100644 --- a/src/mainboard/siemens/sitemp_g1p1/fadt.c +++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c @@ -57,7 +57,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -86,11 +86,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 41811e4..8c65972 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -657,7 +657,7 @@ static void update_subsystemid( device_t dev ) dev->subsystem_device = 0x4077; // U1P0 = 0x4077 } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); - for( i=0; slot[i].bus < 255; i++) { + for( i = 0; slot[i].bus < 255; i++) { device_t d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 634f974..a7f2c96 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if( (cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index eeae519..d4fdfc1 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -139,50 +139,50 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 //Slot 1 PCIE x16 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } //Onboard Firewire - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19 //Slot 2 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4); } if(pci1234[2] & 0xf) { //Onboard ck804b NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53 //Slot 3 PCIE x16 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); } } //Channel B of 8131 //Slot 4 PCI-X 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4); } //Slot 5 PCIX 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29 } //OnBoard LSI SCSI - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 + for(i = 0; i < 2; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30 } //Channel A of 8131 //Slot 6 PCIX 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24 } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index ecb7fe7..d0f569c 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -33,9 +33,9 @@ static void sio_gpio_setup(void) unsigned value; /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1))); } #endif @@ -55,12 +55,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) //set GPIO to input mode #define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -79,7 +79,7 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<29)|(1<<0); + dword |= (1 << 29)|(1 << 0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c index 89bb9eb..0493d38 100644 --- a/src/mainboard/sunw/ultra40m2/mptable.c +++ b/src/mainboard/sunw/ultra40m2/mptable.c @@ -58,8 +58,8 @@ static void *smp_write_config_table(void *v) /* Initialize interrupt mapping*/ dword = pci_read_config32(dev, 0x74); - dword &= ~(1<<15); - dword |= 1<<2; + dword &= ~(1 << 15); + dword |= 1 << 2; pci_write_config32(dev, 0x74, dword); dword = 0x43c6c643; diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 7a5ce93..a7489da 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -78,11 +78,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index bf8f0da..a76cf1b 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -91,25 +91,25 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4); } if(bus_pcix[0]) { - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + for(i = 0; i < 2; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 } } diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index aeff991..d85ae5b 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -77,7 +77,7 @@ static void sio_setup(void) uint8_t byte; enable_smbus(); -// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ +// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); @@ -94,8 +94,8 @@ static void sio_setup(void) } /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */ -#define RC0 (2<<8) -#define RC1 (1<<8) +#define RC0 (2 << 8) +#define RC1 (1 << 8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index eda7dc6..7ca1091 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -92,25 +92,25 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04 << 2)|i, apicid_mcp55, 0x10 + (0+i)%4); } if(bus_pcix[0]) { - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + for(i = 0; i < 2; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4 << 2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4 << 2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 } } diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index eb73817..b137b6b 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -69,19 +69,19 @@ static void sio_setup(void) uint8_t byte; enable_smbus(); -// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ - smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ +// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ + smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 6739105..8a0a6ec 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -79,7 +79,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -98,7 +98,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index e1ca607..631ff7d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 7be3209..7766f3a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -71,7 +71,7 @@ static void sio_setup(void) uint8_t byte; enable_smbus(); - // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ + // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ /* set FAN ctrl to DC mode */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index c568334..ac978a1 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -53,7 +53,7 @@ static UINT8 select_socket(UINT8 socket_id) gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL); value = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK); value |= socket_id; - value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0=Output Enabled, 1=Tristate + value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value); return gpio56_to_53; diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index f4fe61e..ae6991f 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 68af428..7af085d 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xAC); dword = dword & ~(7 << 26); dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 5a7157b..813fa77 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -81,7 +81,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -104,7 +104,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index e4dd3a8..9a60194 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ - for(j=7;j>=2; j--) { + for(j = 7;j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 4661f45..f82ddd1 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -77,19 +77,19 @@ static void sio_setup(void) uint32_t dword; uint8_t byte; enable_smbus(); -// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ - smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ +// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ + smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c index 330dc54..fda488f 100644 --- a/src/mainboard/supermicro/h8scm/fadt.c +++ b/src/mainboard/supermicro/h8scm/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 5b809c3..5ef7f3d 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) dword = (u32 *)pci_read_config32(dev, 0xAC); dword = dword & ~(7 << 26); dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); #endif diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index 08910cc..b50410a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 9ae9476..75a4544 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -72,7 +72,7 @@ static void *smp_write_config_table(void *v) dword = (u32 *)((pci_read_config32(dev, 0xac) & ~(7 << 26)) | (6 << 26)); - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, (u32)dword); /* diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 7312683..f2c79b4 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c index f9768b2..b397f52 100644 --- a/src/mainboard/technexion/tim5690/fadt.c +++ b/src/mainboard/technexion/tim5690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 39192b0..8895163 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index b94b06c..e534617 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c index 50f510d..360a769 100644 --- a/src/mainboard/technexion/tim5690/speaker.c +++ b/src/mainboard/technexion/tim5690/speaker.c @@ -38,9 +38,9 @@ void speaker_init(uint8_t time) { * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. */ #ifdef __PRE_RAM__ - pmio_write(0x60, (pmio_read(0x60) | (1<<5))); + pmio_write(0x60, (pmio_read(0x60) | (1 << 5))); #else - pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); + pm_iowrite(0x60, (pm_ioread(0x60) | (1 << 5))); #endif /* __PRE_RAM__ */ /* SB600 RRG. diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c index 1fa4935..213034a 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ b/src/mainboard/technexion/tim5690/tn_post_code.c @@ -36,7 +36,7 @@ void technexion_post_code_init(void) { uint8_t reg8_data; - device_t dev=0; + device_t dev = 0; // SMBus Module and ACPI Block (Device 20, Function 0) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); @@ -44,80 +44,80 @@ void technexion_post_code_init(void) // LED[bit0]:GPIO0 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pmio_read(0x60); - reg8_data |= (1<<7); // 1: GPIO if not used by SATA + reg8_data |= (1 << 7); // 1: GPIO if not used by SATA pmio_write(0x60, reg8_data); reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1<<0)) & ~(1<<4)); + reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4)); pci_write_config8(dev, 0x80, reg8_data); // LED[bit1]:GPIO1 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); pci_write_config8(dev, 0x80, reg8_data); // LED[bit2]:GPIO4 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pmio_read(0x5e); - reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA + reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA pmio_write(0x5e, reg8_data); reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1<<0); + reg8_data |= (1 << 0); pci_write_config8(dev, 0xa8, reg8_data); reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1<<0); + reg8_data &= ~(1 << 0); pci_write_config8(dev, 0xa9, reg8_data); // LED[bit3]:GPIO6 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pmio_read(0x60); - reg8_data |= (1<<7); // 1: GPIO if not used by SATA + reg8_data |= (1 << 7); // 1: GPIO if not used by SATA pmio_write(0x60, reg8_data); reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1<<2); + reg8_data |= (1 << 2); pci_write_config8(dev, 0xa8, reg8_data); reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1<<2); + reg8_data &= ~(1 << 2); pci_write_config8(dev, 0xa9, reg8_data); // LED[bit4]:GPIO7 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1<<3); + reg8_data |= (1 << 3); pci_write_config8(dev, 0xa8, reg8_data); reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1<<3); + reg8_data &= ~(1 << 3); pci_write_config8(dev, 0xa9, reg8_data); // LED[bit5]:GPIO8 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1<<4); + reg8_data |= (1 << 4); pci_write_config8(dev, 0xa8, reg8_data); reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1<<4); + reg8_data &= ~(1 << 4); pci_write_config8(dev, 0xa9, reg8_data); // LED[bit6]:GPIO10 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pci_read_config8(dev, 0xab); - reg8_data = ((reg8_data | (1<<0)) & ~(1<<1)); + reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1)); pci_write_config8(dev, 0xab, reg8_data); // LED[bit7]:GPIO66 // This is reference SB600 RRG 4.1.1 GPIO reg8_data = pmio_read(0x68); - reg8_data &= ~(1<<5); // 0: GPIO + reg8_data &= ~(1 << 5); // 0: GPIO pmio_write(0x68, reg8_data); reg8_data = pci_read_config8(dev, 0x7e); - reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); pci_write_config8(dev, 0x7e, reg8_data); } @@ -129,7 +129,7 @@ void technexion_post_code_init(void) void technexion_post_code(uint8_t udata8) { uint8_t u8_data; - device_t dev=0; + device_t dev = 0; // SMBus Module and ACPI Block (Device 20, Function 0) #ifdef __PRE_RAM__ @@ -143,80 +143,80 @@ void technexion_post_code(uint8_t udata8) // LED[bit0]:GPIO0 u8_data = pci_read_config8(dev, 0x80); if (udata8 & 0x1) { - u8_data |= (1<<0); + u8_data |= (1 << 0); } else { - u8_data &= ~(1<<0); + u8_data &= ~(1 << 0); } pci_write_config8(dev, 0x80, u8_data); // LED[bit1]:GPIO1 u8_data = pci_read_config8(dev, 0x80); if (udata8 & 0x2) { - u8_data |= (1<<1); + u8_data |= (1 << 1); } else { - u8_data &= ~(1<<1); + u8_data &= ~(1 << 1); } pci_write_config8(dev, 0x80, u8_data); // LED[bit2]:GPIO4 u8_data = pci_read_config8(dev, 0xa8); if (udata8 & 0x4) { - u8_data |= (1<<0); + u8_data |= (1 << 0); } else { - u8_data &= ~(1<<0); + u8_data &= ~(1 << 0); } pci_write_config8(dev, 0xa8, u8_data); // LED[bit3]:GPIO6 u8_data = pci_read_config8(dev, 0xa8); if (udata8 & 0x8) { - u8_data |= (1<<2); + u8_data |= (1 << 2); } else { - u8_data &= ~(1<<2); + u8_data &= ~(1 << 2); } pci_write_config8(dev, 0xa8, u8_data); // LED[bit4]:GPIO7 u8_data = pci_read_config8(dev, 0xa8); if (udata8 & 0x10) { - u8_data |= (1<<3); + u8_data |= (1 << 3); } else { - u8_data &= ~(1<<3); + u8_data &= ~(1 << 3); } pci_write_config8(dev, 0xa8, u8_data); // LED[bit5]:GPIO8 u8_data = pci_read_config8(dev, 0xa8); if (udata8 & 0x20) { - u8_data |= (1<<4); + u8_data |= (1 << 4); } else { - u8_data &= ~(1<<4); + u8_data &= ~(1 << 4); } pci_write_config8(dev, 0xa8, u8_data); // LED[bit6]:GPIO10 u8_data = pci_read_config8(dev, 0xab); if (udata8 & 0x40) { - u8_data |= (1<<0); + u8_data |= (1 << 0); } else { - u8_data &= ~(1<<0); + u8_data &= ~(1 << 0); } pci_write_config8(dev, 0xab, u8_data); // LED[bit7]:GPIO66 u8_data = pci_read_config8(dev, 0x7e); if (udata8 & 0x80) { - u8_data |= (1<<1); + u8_data |= (1 << 1); } else { - u8_data &= ~(1<<1); + u8_data &= ~(1 << 1); } pci_write_config8(dev, 0x7e, u8_data); diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c index f9768b2..b397f52 100644 --- a/src/mainboard/technexion/tim8690/fadt.c +++ b/src/mainboard/technexion/tim8690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ @@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 20-2B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 939becf..9e1c58d 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -59,7 +59,7 @@ static void enable_onboard_nic(void) byte |= ( 1 << 7); pci_write_config8(sm_dev, 0x9a, byte); - byte=pm_ioread(0x59); + byte = pm_ioread(0x59); byte &= ~( 1<< 5); pm_iowrite(0x59,byte); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 39192b0..8895163 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index e052d92..b1805a9 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c index e8ef598..0351b99 100644 --- a/src/mainboard/thomson/ip1000/irq_tables.c +++ b/src/mainboard/thomson/ip1000/irq_tables.c @@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x24c0, /* Device */ @@ -30,13 +30,13 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ - {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ - {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ - {0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ - {0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ - {0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ - {0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ + {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ + {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ + {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ + {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ + {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ } }; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index c387ac6..bdcc1fa 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -67,7 +67,7 @@ static void flash_gpios(void) if ((manufacturer_id == 0x20) && ((device_id == 0x2c) || (device_id == 0x2d))) { printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", - (device_id==0x2c)?'4':'8'); + (device_id == 0x2c)?'4':'8'); u8 fgpi = read8((u8 *)0xffbc0100); printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n", (fgpi & (1 << 0)) ? 'X' : ' ', diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 0bc852e..d13f737 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -77,7 +77,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -96,7 +96,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index c878160..9b46ad6 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index c80e2d6..8c01272 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -82,11 +82,11 @@ static void sio_setup(void) dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); /*serial 0 */ - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 9d633a3..29ab03d 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -78,7 +78,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -97,7 +97,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 157b363..87d06b8 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index bd64cab..e095b79 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -84,11 +84,11 @@ static void sio_setup(void) dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); /*serial 0 */ - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 0fa9742..119821f 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -53,13 +53,13 @@ static UINT8 select_socket(UINT8 socket_id) */ gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL); value = gpio52_to_49 | GPIO_OUT_BIT_GPIO49; // Output of GPIO49 is always forced to "1" - value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0=Output Enabled, 1=Tristate + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, value); value = pci_read_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL); value &= ~(GPIO_OUT_BIT_GPIO48); value |= (~(socket_id & 1)) << 3; // Output of GPIO48 is inverse of SocketId - value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0=Output Enabled, 1=Tristate + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, value); return gpio52_to_49; diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c index 330dc54..fda488f 100644 --- a/src/mainboard/tyan/s8226/fadt.c +++ b/src/mainboard/tyan/s8226/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 68af428..7af085d 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) dword = pci_read_config32(dev, 0xAC); dword = dword & ~(7 << 26); dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ + /* dword |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); #endif diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c index 13c7b66..19832fe 100644 --- a/src/mainboard/via/epia-cn/irq_tables.c +++ b/src/mainboard/via/epia-cn/irq_tables.c @@ -31,15 +31,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x66, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x14 << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0d << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0e << 3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x13 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index a28bf78..39dd3fc 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -46,7 +46,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); - /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -55,7 +55,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80); - /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c index 53a4d79..0c2e165 100644 --- a/src/mainboard/via/pc2500e/irq_tables.c +++ b/src/mainboard/via/pc2500e/irq_tables.c @@ -30,16 +30,16 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x3e, /* Checksum */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, } }; diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 1a5685f..3d9ffb5 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -77,17 +77,17 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 //Slot PCIE x16 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } //Slot PCIE x4 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00 << 2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); } //Onboard SM720 VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6 << 2)|0, apicid_ck804, 0x13); // 19 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 20eb92e..3372f32 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -57,7 +57,7 @@ static void sio_setup(void) /* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); /* Serial 0, Serial 1 */ - dword |= (1<<0) | (1<<1); + dword |= (1 << 0) | (1 << 1); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); }
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Patch set updated for coreboot: northbridge/amd: Improve code formatting
by HAOUAS Elyes
18 Sep '16
18 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16634
-gerrit commit 425034e38545e570869ec951b61fd6067e6c7581 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 18 08:50:54 2016 +0200 northbridge/amd: Improve code formatting Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/common/common.c | 2 +- src/northbridge/amd/agesa/family10/amdfam10.h | 4 +- src/northbridge/amd/agesa/family10/northbridge.c | 37 ++-- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 14 +- src/northbridge/amd/agesa/family12/northbridge.c | 22 +-- .../amd/agesa/family14/acpi/northbridge.asl | 20 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 18 +- src/northbridge/amd/agesa/family15/northbridge.c | 35 ++-- .../amd/agesa/family15rl/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 27 ++- .../amd/agesa/family15tn/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 27 ++- .../amd/agesa/family16kb/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 27 ++- src/northbridge/amd/agesa/oem_s3.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 24 +-- src/northbridge/amd/amdfam10/amdfam10.h | 6 +- src/northbridge/amd/amdfam10/amdfam10_util.asl | 18 +- src/northbridge/amd/amdfam10/debug.c | 12 +- src/northbridge/amd/amdfam10/early_ht.c | 4 +- src/northbridge/amd/amdfam10/get_pci1234.c | 8 +- src/northbridge/amd/amdfam10/ht_config.c | 24 +-- src/northbridge/amd/amdfam10/northbridge.c | 29 ++- src/northbridge/amd/amdfam10/raminit.h | 4 +- src/northbridge/amd/amdfam10/raminit_amdmct.c | 8 +- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 4 +- src/northbridge/amd/amdfam10/reset_test.c | 4 +- src/northbridge/amd/amdfam10/setup_resource_map.c | 4 +- src/northbridge/amd/amdht/AsPsNb.c | 12 +- src/northbridge/amd/amdht/comlib.c | 4 +- src/northbridge/amd/amdht/h3finit.c | 22 +-- src/northbridge/amd/amdht/h3finit.h | 4 +- src/northbridge/amd/amdht/h3ncmn.c | 46 ++--- src/northbridge/amd/amdk8/acpi.c | 26 +-- src/northbridge/amd/amdk8/coherent_ht.c | 124 ++++++------ src/northbridge/amd/amdk8/debug.c | 10 +- src/northbridge/amd/amdk8/early_ht.c | 4 +- src/northbridge/amd/amdk8/exit_from_self.c | 2 +- src/northbridge/amd/amdk8/f.h | 6 +- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 12 +- src/northbridge/amd/amdk8/incoherent_ht.c | 98 ++++----- src/northbridge/amd/amdk8/misc_control.c | 12 +- src/northbridge/amd/amdk8/northbridge.c | 32 +-- src/northbridge/amd/amdk8/raminit.c | 42 ++-- src/northbridge/amd/amdk8/raminit_f.c | 198 +++++++++---------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 110 +++++------ src/northbridge/amd/amdk8/raminit_test.c | 4 +- src/northbridge/amd/amdk8/setup_resource_map.c | 8 +- src/northbridge/amd/amdk8/util.asl | 14 +- src/northbridge/amd/amdmct/amddefs.h | 4 +- src/northbridge/amd/amdmct/mct/mct.h | 202 +++++++++---------- src/northbridge/amd/amdmct/mct/mct_d.c | 156 +++++++-------- src/northbridge/amd/amdmct/mct/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 12 +- src/northbridge/amd/amdmct/mct/mctardk3.c | 2 +- src/northbridge/amd/amdmct/mct/mctardk4.c | 2 +- src/northbridge/amd/amdmct/mct/mctchi_d.c | 4 +- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 52 ++--- src/northbridge/amd/amdmct/mct/mctecc_d.c | 16 +- src/northbridge/amd/amdmct/mct/mctgr.c | 6 +- src/northbridge/amd/amdmct/mct/mctmtr_d.c | 28 +-- src/northbridge/amd/amdmct/mct/mctndi_d.c | 10 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 20 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 52 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct/mcttmrl.c | 20 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 128 ++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 12 +- src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 46 ++--- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 16 +- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 28 +-- src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 56 +++--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 20 +- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 74 +++---- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 110 +++++------ src/northbridge/amd/amdmct/wrappers/mcti.h | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 20 +- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx2/northbridgeinit.c | 90 ++++----- src/northbridge/amd/gx2/pll_reset.c | 6 +- src/northbridge/amd/gx2/raminit.c | 12 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 22 +-- .../amd/pi/00630F01/acpi/northbridge.asl | 4 +- src/northbridge/amd/pi/00630F01/dimmSpd.c | 4 +- src/northbridge/amd/pi/00630F01/northbridge.c | 36 ++-- .../amd/pi/00660F01/acpi/northbridge.asl | 16 +- src/northbridge/amd/pi/00660F01/northbridge.c | 23 ++- .../amd/pi/00730F01/acpi/northbridge.asl | 10 +- src/northbridge/amd/pi/00730F01/northbridge.c | 35 ++-- 102 files changed, 1527 insertions(+), 1535 deletions(-) diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c index ab8f687..8dd2ac0 100644 --- a/src/northbridge/amd/agesa/common/common.c +++ b/src/northbridge/amd/agesa/common/common.c @@ -54,7 +54,7 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) memcpy((char*)info->Buffer, spd_file, spd_file_length); u16 crc = spd_ddr3_calc_crc(info->Buffer, spd_file_length); - if (crc == 0){ + if (crc == 0) { printk(BIOS_EMERG, "Error: Unable to calculate CRC on SPD\n"); return AGESA_UNSUPPORTED; } diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h index b1dab41..27f78a3 100644 --- a/src/northbridge/amd/agesa/family10/amdfam10.h +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -87,8 +87,8 @@ #endif #ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 53ddc0e..dd94094 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -100,7 +100,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if ((sysconf.conf_io_addrx[index+4] == 0)) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -116,7 +116,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -167,10 +167,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -182,7 +182,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -193,10 +193,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -218,7 +218,7 @@ static unsigned int read_nb_cfg_54(void) { msr_t msr; msr = rdmsr(NB_CFG_MSR); - return (( msr.hi >> (54-32)) & 1); + return ((msr.hi >> (54-32)) & 1); } static void get_fx_devs(void) @@ -505,9 +505,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -609,7 +608,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -685,7 +684,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -775,11 +774,11 @@ static void amdfam10_domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -877,7 +876,7 @@ static void sysconf_init(device_t dev) // first node unsigned ht_c_index; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; } @@ -1004,7 +1003,7 @@ static void cpu_bus_scan(device_t dev) nodes = sysconf.nodes; #if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1027,7 +1026,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next); @@ -1072,7 +1071,7 @@ static void cpu_bus_scan(device_t dev) jj = cores_found; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 7afa39d..3c91d2d 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev; /* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -124,7 +124,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1526972..f89c2cc 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,7 +41,7 @@ static device_t __f0_dev[FX_DEVS]; static device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; static device_t get_node_pci(u32 nodeid, u32 fn) { @@ -136,10 +136,10 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, result = 2; if (res) { result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; } } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -397,10 +397,10 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate )) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif - break; // XXX this break looks questionable + break; // XXX this break looks questionable } } @@ -485,7 +485,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -604,11 +604,11 @@ static void domain_set_resources(device_t dev) mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index a1b4acb..e95c95a 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -30,7 +30,7 @@ Device(AGPB) { Name(_ADR, 0x00010000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APR1) } /* APIC mode */ + If(PMOD) { Return(APR1) } /* APIC mode */ Return (PR1) /* PIC Mode */ } } /* end AGPB */ @@ -40,7 +40,7 @@ Device(HDMI) { Name(_ADR, 0x00010001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APR1) } /* APIC mode */ + If(PMOD) { Return(APR1) } /* APIC mode */ Return (PR1) /* PIC Mode */ } } /* end HDMI */ @@ -52,7 +52,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -62,7 +62,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -72,7 +72,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -82,7 +82,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -91,7 +91,7 @@ Device(PE20) { Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ + If(PMOD) { Return(APE0) } /* APIC mode */ Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ @@ -100,7 +100,7 @@ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ + If(PMOD) { Return(APE1) } /* APIC mode */ Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ @@ -109,7 +109,7 @@ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ + If(PMOD) { Return(APE2) } /* APIC mode */ Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ @@ -118,7 +118,7 @@ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ + If(PMOD) { Return(APE3) } /* APIC mode */ Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 6db2b95..28c16fb 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev; /* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -124,7 +124,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -158,7 +158,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi ********************************************************************/ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev; switch(vendev) { case 0x10029809: @@ -168,7 +168,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x10029805: case 0x10029804: case 0x10029803: - new_vendev=0x10029802; + new_vendev = 0x10029802; break; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 0c14bdd..ef6692a 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -80,9 +80,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -138,7 +138,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -410,9 +410,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -636,7 +635,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -703,7 +702,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -824,11 +823,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -984,7 +983,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1062,10 +1061,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1087,14 +1086,14 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } #if CONFIG_CPU_AMD_SOCKET_G34 u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); #else u32 apic_id = (i * core_max) + j + lapicid_start; #endif - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl index 46f8940..9a1fa9e 100644 --- a/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -70,7 +70,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -80,7 +80,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -90,7 +90,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d1560b7..578b8dd 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -80,9 +80,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -410,9 +410,8 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -630,7 +629,7 @@ static void domain_read_resources(struct device *dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -697,7 +696,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -818,11 +817,11 @@ static void domain_set_resources(struct device *dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -972,7 +971,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1053,7 +1052,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 46f8940..9a1fa9e 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -70,7 +70,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -80,7 +80,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -90,7 +90,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7b57cc3..0bd6cfb 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -79,9 +79,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -409,9 +409,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -629,7 +628,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -696,7 +695,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -971,7 +970,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1052,7 +1051,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index 4e6d13e..f74b31a 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28302ef..bdd9dfa 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -79,9 +79,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -409,9 +409,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -644,7 +643,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -711,7 +710,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -834,11 +833,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -988,7 +987,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1069,7 +1068,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 4f2788e..fcf8ada 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -23,7 +23,7 @@ #include <AGESA.h> typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type S3DataTypeMTRR ///< MTRR storage } S3_DATA_TYPE; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 51da7d6..e67a127 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -96,7 +96,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return; - if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current) *p = (u8) nodes; p += 8; - for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) p[i*nodes+j] = 10; else p[i*nodes+j] = 16; @@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_name("BUSN"); acpigen_write_package(HC_NUMS); - for (i=0; i<HC_NUMS; i++) { + for (i = 0; i < HC_NUMS; i++) { acpigen_write_dword(sysconf.ht_c_conf_bus[i]); } // minus the opcode @@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_NUMS * 4); - for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain + for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask } @@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_NUMS * 2); - for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain + for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_io_addrx[i]); acpigen_write_dword(sysconf.conf_io_addr[i]); } @@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x00000000); } // minus the opcode @@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } // minus the opcode @@ -311,7 +311,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_name_byte("CBST", CBST); - if ((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { + if ((CONFIG_CBB == 0xff) && (sysconf.nodes > 32)) { CBS2 = 0x0f; CBB2 = (u8)(CONFIG_CBB-1); } else { diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 4c3aec6..2ef22ee 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -967,8 +967,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "nums.h" #ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif @@ -977,7 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" #include "../amdmct/wrappers/mcti.h" -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" #else #include "../amdmct/mct/mct_d.h" diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl index bf0d177..6e2118d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl @@ -56,9 +56,9 @@ Scope (\_SB) Method (DADD, 2, NotSerialized) { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) + Store(Arg1, Local0) + Store(Arg0, Local1) + Add(ShiftLeft(Local1,16), Local0, Local0) Return (Local0) } @@ -66,7 +66,7 @@ Scope (\_SB) Method (GHCE, 1, NotSerialized) // check if the HC enabled { Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } Else { Return (0x00) } } @@ -74,7 +74,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0) + Store (ShiftRight(And (Local1, 0xfc), 0x02), Local0) Return (Local0) } @@ -82,7 +82,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0x700), 0x08), Local0) + Store (ShiftRight(And (Local1, 0x700), 0x08), Local0) Return (Local0) } @@ -92,7 +92,7 @@ Scope (\_SB) Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Store (And (ShiftRight(Local1, Local2), 0xff), Local0) Return (Local0) } @@ -176,7 +176,7 @@ Scope (\_SB) Store (0x00, Local0) Store (0x00, Local4) Store (0x00, Local3) - While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit ) + While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem) *2 (base, limit) { Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) Increment (Local0) @@ -237,7 +237,7 @@ Scope (\_SB) Store (0x00, Local0) Store (0x00, Local4) Store (0x00, Local3) - While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit) + While (LLess (Local0, 0x40)) // 0x20 ht links * 2 (base, limit) { Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) Increment (Local0) diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index e01c44d..327a0e6 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -95,7 +95,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) printk(BIOS_DEBUG, "\n%04x:",i); } val = pci_read_config32(dev, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -121,7 +121,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -262,7 +262,7 @@ static void dump_smbus_registers(void) printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( smbus_read_byte(device, 0) < 0 ) continue; + if (smbus_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; @@ -287,7 +287,7 @@ static inline void dump_io_resources(u32 port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { u8 val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -305,8 +305,8 @@ static inline void dump_mem(u32 start, u32 end) { u32 i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { - if ((i & 0xf)==0) { + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index a1b411f..812935e 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -96,7 +96,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { + if (next_unitid >= 0x18) { if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -158,7 +158,7 @@ static void enumerate_ht_chain(void) out: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { + if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { u16 flags; flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index a6f679e..11f1589 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -73,7 +73,7 @@ void get_pci1234(void) //2. so at the same time we need update hsdn with hcdn_reg here // printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num); - for (j=0;j<sysconf.ht_c_num;j++) { + for (j = 0; j < sysconf.ht_c_num; j++) { u32 dwordx; dwordx = sysconf.ht_c_conf_bus[j]; // printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]); @@ -86,7 +86,7 @@ void get_pci1234(void) if ((dwordx & 1)) { // We need to find out the number of HC // for exact match - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -94,7 +94,7 @@ void get_pci1234(void) } } // for 0xffc match or same node - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -104,7 +104,7 @@ void get_pci1234(void) } } - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 1)) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 9603223..226d9a8 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -56,7 +56,7 @@ void set_config_map_reg(struct bus *link) tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } @@ -67,7 +67,7 @@ void clear_config_map_reg(struct bus *link) u32 i; u32 ht_c_index = get_ht_c_index(link); - for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } @@ -86,13 +86,13 @@ static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) { u32 ht_c_index = 0; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { return ht_c_index; } @@ -127,7 +127,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -142,7 +142,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -185,7 +185,7 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - if ( sysconf.mmio_addr_num<(index+1)) + if (sysconf.mmio_addr_num<(index+1)) sysconf.mmio_addr_num = index+1; } @@ -198,10 +198,10 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -213,7 +213,7 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -224,9 +224,9 @@ void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 42647b1..6ff343c 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -65,7 +65,7 @@ static device_t __f0_dev[FX_DEVS]; device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; device_t get_node_pci(u32 nodeid, u32 fn) { @@ -605,9 +605,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -719,7 +718,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -879,7 +878,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { struct dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -982,11 +981,11 @@ static void amdfam10_domain_set_resources(device_t dev) // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1348,7 +1347,7 @@ static void sysconf_init(device_t dev) // first node unsigned ht_c_index; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; } @@ -1369,7 +1368,7 @@ static void sysconf_init(device_t dev) // first node { sysconf.enabled_apic_ext_id = 1; } - #if (CONFIG_APIC_ID_OFFSET>0) + #if (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (sysconf.bsp_apicid == 0) { /* bsp apic id is not changed */ @@ -1492,7 +1491,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - while (dev_mc){ + while (dev_mc) { printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); @@ -1516,7 +1515,7 @@ static void cpu_bus_scan(device_t dev) nodes = sysconf.nodes; #if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1556,7 +1555,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next; @@ -1637,7 +1636,7 @@ static void cpu_bus_scan(device_t dev) jj = cores_found; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { u32 apic_id; if (dual_node) { @@ -1664,7 +1663,7 @@ static void cpu_bus_scan(device_t dev) } } -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 7c7065df..bfc0da0 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -17,7 +17,7 @@ #define RAMINIT_H #if 0 -#if CONFIG_DIMM_SUPPORT==0x0110 +#if CONFIG_DIMM_SUPPORT == 0x0110 //FBDIMM REG /* each channel can have 8 fbdimm */ #define DIMM_SOCKETS 8 @@ -38,7 +38,7 @@ struct mem_controller { #endif #endif -//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004 +//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F * 2 for socket M2/M3 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 6d063ab..86f0788 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -524,7 +524,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 return freq; } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #include "amdfam10.h" #include "../amdmct/wrappers/mcti.h" #include "../amdmct/amddefs.h" @@ -633,7 +633,7 @@ int mctRead_SPD(u32 smaddr, u32 reg) void mctSMBhub_Init(u32 node) { struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); + struct mem_controller *ctrl = &(sysinfo->ctrl[node]); activate_spd_rom(ctrl); } @@ -642,9 +642,9 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) { int j; struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); + struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; } diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index df3850b..0461323 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -56,7 +56,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const int j; int index = 0; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = NODE_PCI(i, 0); @@ -70,7 +70,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const ctrl->spd_switch_addr = spd_addr[index++]; - for (j=0; j < 8; j++) { + for (j = 0; j < 8; j++) { ctrl->spd_addr[j] = spd_addr[index++]; } diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index bdf70b5..7ddf93f 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -116,8 +116,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b if ((config_map & 3) != 3) { continue; } - if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8) ) - ) == val ) + if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8)) + ) == val) { return (config_map >> 16) & 0xff; } diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 6de7a8c..7e71cf7 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -72,9 +72,9 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset if (IS_ENABLED(RES_DEBUG)) printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i/4, register_values[i], - register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), + register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], - register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) + register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); switch (register_values[i]) { case RES_PCI_IO: //PCI diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c index e34fa4c..2e6c103 100644 --- a/src/northbridge/amd/amdht/AsPsNb.c +++ b/src/northbridge/amd/amdht/AsPsNb.c @@ -43,13 +43,13 @@ u8 getMinNbCOF(void) numOfNode = getNumOfNodeNb(); /* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */ - for (i=0; i < numOfNode; i++) + for (i = 0; i < numOfNode; i++) { /* stub function for APIC ID virtualization for large MP system later */ deviceId = translateNodeIdToDeviceIdNb(i); - /* read all P-state spec registers for NbDid=1 */ - for (j=0; j < 5; j++) + /* read all P-state spec registers for NbDid = 1 */ + for (j = 0; j < 5; j++) { AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */ /* get NbDid */ @@ -86,13 +86,13 @@ u8 getMinNbCOF(void) nextNbFid = nextNbFid >> 1; */ } } - if ( i == 0) + if (i == 0) nbFid = nextNbFid; - else if ( nbFid > nextNbFid ) + else if (nbFid > nextNbFid) nbFid = nextNbFid; } - /* add the base and convert to 100MHz divide by 2 if DID=1 */ + /* add the base and convert to 100MHz divide by 2 if DID = 1 */ if (nbDid) nbFid = (u8) (nbFid + 4); else diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 64092ff..7a15325 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -120,7 +120,7 @@ void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length) ASSERT(pDst != NULL); ASSERT(pSrc != NULL); - while (length--){ + while (length--) { // *(((u8*)pDst)++) = *(((u8*)pSrc)++); *((u8*)pDst) = *((u8*)pSrc); pDst++; @@ -134,7 +134,7 @@ void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length) ASSERT(length <= 32768); ASSERT(pBuf != NULL); - while (length--){ + while (length--) { //*(((u8*)pBuf)++) = val; *(((u8*)pBuf)) = val; pBuf++; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bfda13d..b4838b4 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -671,7 +671,7 @@ static void htDiscoveryFloodFill(sMainData *pDat) pDat->TotalLinks++; - if ( !pDat->sysMatrix[currentNode][token] ) + if (!pDat->sysMatrix[currentNode][token]) { pDat->sysDegree[currentNode]++; pDat->sysDegree[token]++; @@ -745,8 +745,8 @@ static BOOL isoMorph(u8 i, sMainData *pDat) { for (k = 0; k < nodecnt; k++) { - if ( pDat->sysMatrix[j][k] != - pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]] ) + if (pDat->sysMatrix[j][k] != + pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]]) return FALSE; } } @@ -1356,12 +1356,12 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i].SelRegang = FALSE; pDat->PortList[i+1].SelRegang = FALSE; - if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) + if ((pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) continue; /* Only process CPU to CPU links */ for (j = i+2; j < pDat->TotalLinks*2; j += 2) { - if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) + if ((pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU)) continue; /* Only process CPU to CPU links */ if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) @@ -1506,7 +1506,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBBAUpstreamWidth = 16; #endif - if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) + if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) { if (pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits) { @@ -1639,7 +1639,7 @@ static void hammerSublinkFixup(sMainData *pDat) { if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */ (loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */ - (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */ + (loFreq != 2)) /* {13, 2} 2400MHz / 400MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 11) @@ -1651,19 +1651,19 @@ static void hammerSublinkFixup(sMainData *pDat) { if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */ (loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */ - (loFreq != 0) ) /* { 9, 0} 1600MHz / 200MHz 8:1 */ + (loFreq != 0)) /* { 9, 0} 1600MHz / 200MHz 8:1 */ downgrade = TRUE; } else if (hiFreq == 7) { if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */ - (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */ + (loFreq != 0)) /* { 7, 0} 1200MHz / 200MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 5) { if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */ - (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */ + (loFreq != 0)) /* { 5, 0} 800MHz / 200MHz 4:1 */ downgrade = TRUE; } else if (hiFreq == 2) @@ -1807,7 +1807,7 @@ static void tuning(sMainData *pDat) /* For each node, invoke northbridge specific buffer tunings or * system specific customizations. */ - for (i=0; i < pDat->NodesDiscovered + 1; i++) + for (i = 0; i < pDat->NodesDiscovered + 1; i++) { if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL) || !pDat->HtBlock->AMD_CB_CustomizeBuffers(i)) diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index ab2dace..c973792 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -358,7 +358,7 @@ typedef struct { * * --------------------------------------------------------------------------------------- */ - BOOL (*AMD_CB_CustomizeTrafficDistribution)( void ); + BOOL (*AMD_CB_CustomizeTrafficDistribution)(void); /**---------------------------------------------------------------------------------------- @@ -379,7 +379,7 @@ typedef struct { * * --------------------------------------------------------------------------------------- */ - BOOL (*AMD_CB_CustomizeBuffers)( u8 node ); + BOOL (*AMD_CB_CustomizeBuffers)(u8 node); /**---------------------------------------------------------------------------------------- * diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cbe90e0..0d0055b 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * @param[in] link = the link on that Node to examine * @param[in] *nb = this northbridge * @return true - The link has the following status - * linkCon=1, Link is connected - * InitComplete=1, Link initialization is complete - * NC=0, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * linkCon = 1, Link is connected + * InitComplete = 1, Link initialization is complete + * NC = 0, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * *****************************************************************************/ @@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; #else return 0; @@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 3, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -662,7 +662,7 @@ static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 31, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -1122,11 +1122,11 @@ static u8 readSbLink(cNorthBridge *nb) * @param[in] link = the Link on that node to examine * @param[in] *nb = this northbridge * @return = true - The link has the following status - * LinkCon=1, Link is connected - * InitComplete=1,Link initilization is complete - * NC=1, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * LinkCon = 1, Link is connected + * InitComplete = 1,Link initilization is complete + * NC = 1, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * * --------------------------------------------------------------------------------------- @@ -1143,7 +1143,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - /* Verify linkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT; } @@ -1922,7 +1922,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links01); - /* DstNode = 1, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0107; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0), makePCIBusFromNode(0), @@ -1939,7 +1939,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links10); - /* DstNode = 0, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0007; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1), makePCIBusFromNode(1), @@ -2088,13 +2088,13 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_FIFOPTR_3XDC); - for (i=0; i < nb->maxLinks; i++) + for (i = 0; i < nb->maxLinks; i++) { temp = 0; if (nb->verifyLinkIsCoherent(node, i, nb)) { temp = 0x26; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } else @@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (nb->verifyLinkIsNonCoherent(node, i, nb)) { temp = 0x25; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } } @@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3 * (and, one assumes, from there on). */ - for (i=0; i < (pDat->NodesDiscovered +1); i++) + for (i = 0; i < (pDat->NodesDiscovered +1); i++) { AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i), makePCIBusFromNode(i), @@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } } - for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) + for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) { isOuter = FALSE; /* Check for outer node by scanning the config maps on node 0 for one @@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (node == (u8)temp) { /* This is an outer node. Tune it appropriately. */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (isErrata153) { @@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (isErrata153) { /* Tuning for inner node coherent links */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (nb->verifyLinkIsCoherent(node, j, nb)) { diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 992a85e..906dc0b 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -101,7 +101,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return; - if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,29 +158,29 @@ static unsigned long acpi_fill_slit(unsigned long current) p += 8; #if 0 - for (i=0;i<sysconf.hc_possible_num;i++) { - if ((sysconf.pci1234[i]&1) !=1 ) continue; + for (i = 0; i < sysconf.hc_possible_num; i++) { + if ((sysconf.pci1234[i]&1) !=1) continue; outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif - for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) { + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) { p[i*nodes+j] = 10; } else { #if 0 int k; u8 latency_factor = 0; int k_start, k_end; - if (i<j) { + if (i < j) { k_start = i; k_end = j; } else { k_start = j; k_end = i; } - for (k=k_start;k<=k_end; k++) { + for (k = k_start; k <= k_end; k++) { if (outer_node[k]) { latency_factor = 1; break; @@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCLK"); acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x0); } @@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCDN"); acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } acpigen_pop_len(); @@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_write_name(name); acpigen_write_package(dlen); - for (i=0; i<dlen; i++) { + for (i = 0; i < dlen; i++) { dword = pci_read_config32(dev, offset+i*4); acpigen_write_dword(dword); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7e33feb..887a23b 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -139,7 +139,7 @@ static void disable_probes(void) printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... "); - val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); + val = pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; @@ -193,7 +193,7 @@ static void enable_routing(u8 node) /* Enable routing table */ printk(BIOS_SPEW, "Enabling routing table for node %d", node); - val=pci_read_config32(NODE_HT(node), 0x6c); + val = pci_read_config32(NODE_HT(node), 0x6c); val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); @@ -241,7 +241,7 @@ static void rename_temp_node(u8 node) printk(BIOS_SPEW, "Renaming current temporary node to %d", node); - val=pci_read_config32(NODE_HT(7), 0x60); + val = pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); @@ -401,7 +401,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo uint8_t linkn; uint32_t val; val = 1; - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { uint8_t regpos; uint32_t reg; regpos = 0x98 + 0x20 * linkn; @@ -423,10 +423,10 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) if (((source &1)!=(dest &1)) #if CROSS_BAR_47_56 - && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here + && ((source < 4)||(source > 5)) //(6,7) (7,6) should still be here //(6,5) (7,4) should be here #endif - ){ + ) { val |= (1<<16); } else { /*for CROSS_BAR_47_56 47, 56, should be here too @@ -437,7 +437,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) val |= ((val_s>>16) - (1<<(linkn+1)))<<16; } - fill_row(temp,dest, val ); + fill_row(temp,dest, val); } #if CROSS_BAR_47_56 @@ -453,7 +453,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num) { int i; - for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); } } @@ -470,7 +470,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { int i; - for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); } } @@ -535,7 +535,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif #if !CROSS_BAR_47_56 u8 gateway; u8 diff; - if (source<dest) { + if (source < dest) { gateway = source + 2; } else { gateway = source - 2; @@ -552,7 +552,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif diff = ((source&1)!=(dest &1)); #endif - if (diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ + if (diff && (val_s!=(val&0xff))) { /* use another connect as response*/ val_s -= val & 0xff; #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED uint8_t byte; @@ -562,14 +562,14 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif byte = val_s; byte = get_linkn_last_count(byte); if ((byte>>2)>1) { /* make sure not the corner*/ - if (source<dest) { + if (source < dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 #if 0 - if (source==7) { + if (source == 7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 - } else if (source==6){ + } else if (source == 6) { val_s-=link_connection(temp, 7); // for 6,3 via 4 } else #endif @@ -614,10 +614,10 @@ static void setup_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif @@ -641,10 +641,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_remote_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif } @@ -658,7 +658,7 @@ static void setup_uniprocessor(void) printk(BIOS_SPEW, "Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; - if (tmp>0) return; + if (tmp > 0) return; #endif disable_probes(); } @@ -668,10 +668,10 @@ static int optimize_connection_group(const u8 *opt_conn, int num) { int needs_reset = 0; int i; - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), - NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); + NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i]))); } return needs_reset; } @@ -689,7 +689,7 @@ static unsigned setup_smp2(void) val = get_row(0,0); byte = (val>>16) & 0xfe; - if (byte<0x2) { /* no coherent connection so get out.*/ + if (byte < 0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } @@ -717,7 +717,7 @@ static unsigned setup_smp2(void) val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); - if ((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/ + if ((byte>>2) == 3) { /* Oh! we need to treat it as node2. So use another link*/ val = get_row(0,0); byte = (val>>16) & 0xfe; #if TRY_HIGH_FIRST == 1 @@ -760,14 +760,14 @@ static unsigned setup_smp4(void) u8 byte; uint32_t val; - nodes=4; + nodes = 4; /* Setup and check temporary connection from Node 0 to Node 2 */ val = get_row(0,0); byte = ((val>>16) & 0xfe) - link_connection(0,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have two coherent for 4p and above*/ + if ((byte>>2) == 0) { /* We should have two coherent for 4p and above*/ nodes = 2; return nodes; } @@ -841,7 +841,7 @@ static unsigned setup_smp4(void) #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED /* We need to find out which link is to node3 */ - if ((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ + if ((byte>>2) == 2) { /* one to node3, one to node0, one to node4*/ val = get_row(7,3); if ((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/ val = get_row(2,2); @@ -865,7 +865,7 @@ static unsigned setup_smp4(void) val = get_row(7,3); byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent links on node 3 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(3,5) link=", byte); setup_remote_row_direct(3, 5, byte); @@ -875,7 +875,7 @@ static unsigned setup_smp4(void) byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent link on node 2 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(2,4) link=", byte); setup_row_direct(2, 4, byte); @@ -931,14 +931,14 @@ static unsigned setup_smp6(void) u8 byte; uint32_t val; - nodes=6; + nodes = 6; /* Setup and check temporary connection from Node 0 to Node 4 through 2*/ val = get_row(2,2); byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent link on node 2 for 6p and above*/ nodes = 4; return nodes; } @@ -948,7 +948,7 @@ static unsigned setup_smp6(void) val = get_row(3,3); byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent links on node 3 for 6p and above*/ nodes = 4; return nodes; } @@ -975,7 +975,7 @@ static unsigned setup_smp6(void) setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1003,7 +1003,7 @@ static unsigned setup_smp6(void) enable_routing(4); setup_temp_row(0,1); - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } verify_connection(7); @@ -1031,7 +1031,7 @@ static unsigned setup_smp6(void) #if CONFIG_MAX_PHYSICAL_CPUS > 6 /* We need to find out which link is to node5 */ - if ((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ + if ((byte>>2) == 2) { /* one to node5, one to node2, one to node6*/ val = get_row(7,5); if ((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ val = get_row(4,4); @@ -1054,7 +1054,7 @@ static unsigned setup_smp6(void) val = get_row(7,5); byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent links on node 5 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(5,7) link=", byte); setup_remote_row_direct(5, 7, byte); @@ -1065,7 +1065,7 @@ static unsigned setup_smp6(void) byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent link on node 4 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(4,6) link=", byte); setup_row_direct(4, 6, byte); @@ -1115,7 +1115,7 @@ static unsigned setup_smp6(void) /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) * It will be done by clear_dead_links */ - for (byte=0; byte<4; byte++) { + for (byte = 0; byte < 4; byte++) { clear_temp_row(byte); } #endif @@ -1134,7 +1134,7 @@ static unsigned setup_smp8(void) u8 byte; uint32_t val; - nodes=8; + nodes = 8; /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ val = get_row(4,4); @@ -1143,7 +1143,7 @@ static unsigned setup_smp8(void) #else byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); /* Max link to 6*/ - if ((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + if ((byte>>2) == 0) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; return nodes; } @@ -1170,7 +1170,7 @@ static unsigned setup_smp8(void) val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent links on node 5 for 6p and above*/ nodes = 6; return nodes; } @@ -1203,7 +1203,7 @@ static unsigned setup_smp8(void) setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); - for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1241,7 +1241,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } setup_temp_row(5,6); @@ -1249,7 +1249,7 @@ static unsigned setup_smp8(void) verify_connection(7); val = get_row(7,6); // to chect it if it is node6 before renaming - if ( (val>>16) == 1) { // it is real node 7 so swap it + if ((val>>16) == 1) { // it is real node 7 so swap it /* We need to recompute link to 6 */ val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,3); @@ -1262,7 +1262,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); #if 0 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } #endif @@ -1282,7 +1282,7 @@ static unsigned setup_smp8(void) #if !CROSS_BAR_47_56 setup_temp_row(0,1); - for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1302,7 +1302,7 @@ static unsigned setup_smp8(void) setup_row_direct(4, 7, byte); /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); } @@ -1327,7 +1327,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 7, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1511,7 +1511,7 @@ static unsigned verify_mp_capabilities(unsigned nodes) mask = 0x06; /* BigMPCap */ - for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { mask &= pci_read_config32(NODE_MC(node), 0xe8); } @@ -1525,7 +1525,7 @@ static unsigned verify_mp_capabilities(unsigned nodes) break; #endif case 0x00: /* Non SMP */ - if (nodes >1 ) { + if (nodes >1) { printk(BIOS_ERR, "Going back to UP\n"); return 1; } @@ -1542,7 +1542,7 @@ static void clear_dead_routes(unsigned nodes) int last_row; int node, row; #if CONFIG_MAX_PHYSICAL_CPUS == 8 - if (nodes==8) return;/* don't touch (7,7)*/ + if (nodes == 8) return;/* don't touch (7,7)*/ #endif last_row = nodes; if (nodes == 1) { @@ -1555,9 +1555,9 @@ static void clear_dead_routes(unsigned nodes) } /* Update the local row */ - for ( node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { uint32_t val = 0; - for (row =0; row<nodes; row++) { + for (row =0; row < nodes; row++) { val |= get_row(node, row); } fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); @@ -1571,7 +1571,7 @@ static unsigned verify_dualcore(unsigned nodes) unsigned node, totalcpus, tmp; totalcpus = 0; - for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; totalcpus += (tmp + 1); } @@ -1626,7 +1626,7 @@ static void coherent_ht_finalize(unsigned nodes) /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ - val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); + val = pci_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); @@ -1666,14 +1666,14 @@ static int apply_cpu_errata_fixes(unsigned nodes) if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); - pci_write_config32(dev, 0x70, cmd ); + pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); - pci_write_config32(dev, 0x7c, cmd ); + pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } /* Clock Power/Timing Low */ @@ -1694,7 +1694,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) cmd_ref = 0x04e20707; /* Registered */ cmd = pci_read_config32(dev, 0xd4); if (cmd != cmd_ref) { - pci_write_config32(dev, 0xd4, cmd_ref ); + pci_write_config32(dev, 0xd4, cmd_ref); needs_reset = 1; /* Needed? */ } } @@ -1765,14 +1765,14 @@ static int optimize_link_coherent_ht(void) nodes = get_nodes(); #if CONFIG_MAX_PHYSICAL_CPUS > 1 - if (nodes>1) { + if (nodes > 1) { needs_reset |= optimize_connection( NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), - NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0))); } #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if (nodes>2) { + if (nodes > 2) { /* optimize physical connections - by LYH */ static const u8 opt_conn4[] = { 0,2, @@ -1784,7 +1784,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 - if (nodes>4) { + if (nodes > 4) { static const uint8_t opt_conn6[] ={ 2, 4, 3, 5, @@ -1797,7 +1797,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if (nodes>6) { + if (nodes > 6) { static const uint8_t opt_conn8[] ={ 4, 6, #if CROSS_BAR_47_56 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 18fc858..a8431f4 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -71,7 +71,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -185,7 +185,7 @@ static void dump_smbus_registers(void) printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( smbus_read_byte(device, 0) < 0 ) continue; + if (smbus_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; @@ -211,7 +211,7 @@ static inline void dump_io_resources(unsigned port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { uint8_t val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -229,8 +229,8 @@ static inline void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { - if ((i & 0xf)==0) { + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index d07da2a..638511a 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -64,7 +64,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. + if (next_unitid >= 0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -127,7 +127,7 @@ out: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { + if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index 858a0c0..6da042f 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -144,7 +144,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); } while (((dcm & DCM_MemClrStatus) == - 0) /* || ((dcm & DCM_DramEnabled) == 0) */ ); + 0) /* || ((dcm & DCM_DramEnabled) == 0) */); if (loops >= TIMEOUT_LOOPS) { printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index ce039af..a679150 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -537,9 +537,9 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) if (sysinfo->nodes == 1) return; // in case only one CPU installed - for (i=1; i<sysinfo->nodes; i++) { + for (i = 1; i < sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->mem_trained[i]==0x00) continue; + if (sysinfo->mem_trained[i]== 0x00) continue; mask |= (1<<i); @@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) i%=sysinfo->nodes; } - for (i=0; i<sysinfo->nodes; i++) { + for (i = 0; i < sysinfo->nodes; i++) { printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); switch(sysinfo->mem_trained[i]) { case 0: //don't need train diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 9cf4083..32f56b5 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -51,7 +51,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + printk(BIOS_DEBUG, "node.link = bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif @@ -170,7 +170,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * Total: 12 * * Just put all the possible HT Node/link to the list tp pci1234[] in - * src/mainboard/<vendor>/<mainboard>get_bus_conf.c + * src/mainboard/<vendor>/<mainboard > get_bus_conf.c * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and * socket 3 on a 4 way system? Treat that as an HC, too! @@ -211,7 +211,7 @@ void get_sblk_pci1234(void) dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { uint32_t dwordx; dwordx = pci_read_config32(dev, 0xe0 + j*4); dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ @@ -225,7 +225,7 @@ void get_sblk_pci1234(void) /* We need to find out the number of HC * for exact match */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -234,7 +234,7 @@ void get_sblk_pci1234(void) } /* For 0xff0 match or same node */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -244,7 +244,7 @@ void get_sblk_pci1234(void) } } - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((sysconf.pci1234[i] & 1) != 1) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index bc50b66..971c4a5 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -118,7 +118,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) uint32_t id; freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, unfiltered freq_cap = 0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ id = pci_read_config32(dev, 0); @@ -148,7 +148,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) #endif } - printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, filtered freq_cap = 0x%x\n", pos, freq_cap); #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 freq_cap &= 0x3f; @@ -221,7 +221,7 @@ static int ht_optimize_link( /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1 = 0x%x, freq_cap2 = 0x%x\n", freq_cap1, freq_cap2); /* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -230,11 +230,11 @@ static int ht_optimize_link( old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset); /* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -243,45 +243,45 @@ static int ht_optimize_link( /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1 = 0x%x, width_cap2 = 0x%x\n", width_cap1, width_cap2); /* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input width = 0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input|output width = 0x%x\n", width); /* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev1 input|output width = 0x%x\n", width); /* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev2 input|output width = 0x%x\n", width); /* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev2 input|output width = 0x%x\n", width); /* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -374,7 +374,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (offset_unitid) { - if (next_unitid>= (bus ? 0x20:0x18) ) { + if (next_unitid>= (bus ? 0x20:0x18)) { if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -428,9 +428,9 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, /* Remeber the location of the last device */ udev = dev; upos = pos; - uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS; + uoffs = (offs != PCI_HT_SLAVE0_OFFS) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS; - } while (last_unitid != next_unitid ); + } while (last_unitid != next_unitid); #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: @@ -438,7 +438,7 @@ out: end_of_chain: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { + if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; @@ -448,7 +448,7 @@ end_of_chain: ; #if CONFIG_RAMINIT_SYSINFO // Here need to change the dev in the array int i; - for (i=0;i<sysinfo->link_pair_num;i++) + for (i = 0; i < sysinfo->link_pair_num; i++) { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { @@ -514,9 +514,9 @@ static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt link_type = dword & 0xff; - if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + if ((link_type & 7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/ dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); - dword &= ~( 0xff<<(linkn *8) ); + dword &= ~(0xff<<(linkn *8)); dword |= val << (linkn *8); if (dword != dword_old) { @@ -551,10 +551,10 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) devn = offset_unit_id(i == 0) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; - reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted - if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) { + reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted + if ((reg & 0xffff) == PCI_VENDOR_ID_AMD) { val = 0x25; - } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) { + } else if ((reg & 0xffff) == PCI_VENDOR_ID_NVIDIA) { val = 0x25;//??? } else { continue; @@ -581,9 +581,9 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, dword = pci_read_config32(dev, regpos); link_type = dword & 0xff; - if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + if ((link_type & 0x7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/ regpos = 0x90 + (linkn * 0x20); - dword = pci_read_config32(dev, regpos ); + dword = pci_read_config32(dev, regpos); if (dword != val) { pci_write_config32(dev, regpos, val); @@ -615,8 +615,8 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, busn = (reg & 0xff0000)>>16; //busn for (devn = 0; devn < 0x20; devn++) { - reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? - if ( (reg & 0xffff) == vendorid ) { + reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? + if ((reg & 0xffff) == vendorid) { reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); break; } @@ -659,14 +659,14 @@ static int ht_setup_chains(uint8_t ht_c_num) reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); //We need setup 0x94, 0xb4, and 0xd4 according to the reg - devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 - regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; + devpos = ((reg & 0xf0)>>4)+0x18; // nodeid;it will decide 0x18 or 0x19 + regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; + dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ; dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; - pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); + pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword); /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(busn, offset_unit_id(i == 0)); @@ -712,29 +712,29 @@ static int ht_setup_chains_x(void) /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ - print_linkn_in("SBLink=", ((reg>>8) & 3) ); + /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */ + print_linkn_in("SBLink=", ((reg>>8) & 3)); #if CONFIG_RAMINIT_SYSINFO sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; #endif - tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); + tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); - next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ + next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ #if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ - tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit + tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg); - tempreg = 3 | ( 3<<4) | (0<<12); //base + tempreg = 3 | (3<<4) | (0<<12); //base pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg); next_io_base = 0x3+0x1; #endif /* clean others */ - for (ht_c_num=1;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); #if CONFIG_K8_ALLOCATE_IO_RANGE @@ -744,11 +744,11 @@ static int ht_setup_chains_x(void) #endif } - for (nodeid=0; nodeid<nodes; nodeid++) { + for (nodeid = 0; nodeid < nodes; nodeid++) { pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { unsigned regpos; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(dev, regpos); @@ -756,7 +756,7 @@ static int ht_setup_chains_x(void) print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); tempreg = 3 | (nodeid <<4) | (linkn<<8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ break; @@ -774,7 +774,7 @@ static int ht_setup_chains_x(void) /* io range allocation */ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); next_io_base += 0x3+0x1; #endif @@ -783,7 +783,7 @@ static int ht_setup_chains_x(void) } /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/ - for (nodeid = 1; nodeid<nodes; nodeid++) { + for (nodeid = 1; nodeid < nodes; nodeid++) { int i; pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); @@ -812,8 +812,8 @@ static int ht_setup_chains_x(void) } /* recount ht_c_num*/ - uint8_t i=0; - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + uint8_t i = 0; + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xf) != 0x0)) { i++; @@ -840,15 +840,15 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) unsigned link_pair_num = sysinfo->link_pair_num; printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); - for (i=0; i< link_pair_num; i++) { + printk(BIOS_SPEW, "sysinfo->link_pair_num = 0x%x\n", link_pair_num); + for (i = 0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed = 0x%x\n", i, reset_needed); } reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed = 0x%x\n", reset_needed); return reset_needed; diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index a2b4651..3cbeb04 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -120,7 +120,7 @@ static void misc_control_init(struct device *dev) */ cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + pci_write_config32(dev, 0x44, cmd); #if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { @@ -129,11 +129,11 @@ static void misc_control_init(struct device *dev) */ cmd = pci_read_config32(dev, 0x80); cmd &= ~(1<<0); - pci_write_config32(dev, 0x80, cmd ); + pci_write_config32(dev, 0x80, cmd); cmd = pci_read_config32(dev, 0x84); cmd &= ~(1<<24); cmd &= ~(1<<8); - pci_write_config32(dev, 0x84, cmd ); + pci_write_config32(dev, 0x84, cmd); /* Errata 66 * Limit the number of downstream posted requests to 1 @@ -142,14 +142,14 @@ static void misc_control_init(struct device *dev) if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); - pci_write_config32(dev, 0x70, cmd ); + pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); - pci_write_config32(dev, 0x7c, cmd ); + pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } /* Clock Power/Timing Low */ @@ -175,7 +175,7 @@ static void misc_control_init(struct device *dev) } cmd = pci_read_config32(dev, 0xd4); if (cmd != cmd_ref) { - pci_write_config32(dev, 0xd4, cmd_ref ); + pci_write_config32(dev, 0xd4, cmd_ref); needs_reset = 1; /* Needed? */ } } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d80c565..2f71b8c 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -42,7 +42,7 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 static device_t __f0_dev[MAX_FX_DEVS]; static device_t __f1_dev[MAX_FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; static void get_fx_devs(void) { @@ -178,7 +178,7 @@ static void amdk8_scan_chain(struct bus *link) config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | + ((nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | (0xff << 24); @@ -489,8 +489,8 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate) ) #endif break; @@ -505,7 +505,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) /* allocate a temp resource for the legacy VGA buffer */ resource = new_resource(dev, IOINDEX(4, link->link_num)); - if (!resource){ + if (!resource) { printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev)); return; } @@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { u32 limitk_pri = 0; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); @@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) hole_sizek = (4*1024*1024) - hole_startk; - for (i=7;i>node_id;i--) { + for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) carry_over = (4*1024*1024) - hole_startk; - for (i=7;i>node_id;i--) { + for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -962,7 +962,7 @@ static void amdk8_domain_set_resources(device_t dev) #if CONFIG_GFXUMA - printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d : uma_memory_base/1024 = 0x%08llx, mmio_basek = 0x%08lx, basek = 0x%08x, limitk = 0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); #else @@ -970,11 +970,11 @@ static void amdk8_domain_set_resources(device_t dev) #endif /* See if I need to split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -984,7 +984,7 @@ static void amdk8_domain_set_resources(device_t dev) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (reset_memhole) #if !CONFIG_K8_REV_F_SUPPORT - if (!is_cpu_pre_e0() ) + if (!is_cpu_pre_e0()) #endif sizek += hoist_memory(mmio_basek,i); #endif @@ -1210,7 +1210,7 @@ static void cpu_bus_scan(device_t dev) // ----> you can mixed single core e0 and dual core e0 at any sequence // That is the typical case - if (j == 0 ){ + if (j == 0) { #if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else @@ -1222,10 +1222,10 @@ static void cpu_bus_scan(device_t dev) if (e0_later_single_core) { printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); - j=1; + j = 1; } - if (siblings > j ) { + if (siblings > j) { } else { siblings = j; @@ -1243,7 +1243,7 @@ static void cpu_bus_scan(device_t dev) jj = siblings; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index aab9fa7..ec90756 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -645,7 +645,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) value = spd_read_byte(device, 5); /* number of physical banks */ if (value < 0) goto hw_err; if (value == 1) goto out; - if ((value != 2) && (value != 4 )) { + if ((value != 2) && (value != 4)) { goto val_err; } #if CONFIG_QRANK_DIMM_SUPPORT @@ -748,7 +748,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) { static const unsigned cs_map_aa[] = { - /* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */ + /* (row = 12, col = 8)(14, 12) ---> (0, 0) (2, 4) */ 0, 1, 3, 6, 0, 0, 2, 4, 7, 9, 0, 0, 5, 8,10, @@ -760,7 +760,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map &= ~(0xf << (index * 4)); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map &= ~(0xf << ( (index + 2) * 4)); + map &= ~(0xf << ((index + 2) * 4)); } #endif @@ -771,7 +771,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map |= (sz.side1 - (25 + 3)) << (index *4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); + map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4); } #endif } @@ -779,7 +779,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); + map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4); } #endif } @@ -824,7 +824,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, limit = (limit_k << 2); limit &= 0xffff0000; limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); + limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; base |= (0 << 8) | (1<<1) | (1<<0); @@ -940,8 +940,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) } value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - cs_mode =( value >> ((index>>1)*4)) & 0xf; - if (cs_mode == 0 ) continue; + cs_mode =(value >> ((index>>1)*4)) & 0xf; + if (cs_mode == 0) continue; if (common_cs_mode == 0) { common_cs_mode = cs_mode; } @@ -960,7 +960,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) } /* Find the bits of csbase that we need to interleave on */ - if (is_cpu_pre_d0()){ + if (is_cpu_pre_d0()) { csbase_inc = 1 << csbase_low_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ @@ -974,8 +974,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) else { csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { - if ( (bits==3) && (common_cs_mode > 8)) { -// printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n"); + if ((bits == 3) && (common_cs_mode > 8)) { +// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1223,7 +1223,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 5, /* *Physical Banks */ 6, /* *Module Data Width low */ 7, /* *Module Data Width high */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 11, /* *SDRAM Type */ 13, /* *SDRAM Width */ 17, /* *Logical Banks */ @@ -1390,7 +1390,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_ /* Following table comes directly from BKDG (unbuffered DIMM support) - [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty + [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1 = present 0 = empty X uses same layout but 1 means double rank 0 is single rank/empty Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to @@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ if (!is_cpu_pre_e0()) { - if (min_cycle_time==0x50) { + if (min_cycle_time == 0x50) { value |= 1<<31; } } @@ -1927,7 +1927,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa dimm = 1<<(DCL_x4DIMM_SHIFT+i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif @@ -2239,7 +2239,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, carry_over = (4*1024*1024) - hole_startk; - for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -2294,7 +2294,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) * we need to decrease it. */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2315,7 +2315,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2480,7 +2480,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node - 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node) + 5. for node interleaving we need to set mem hole to every node (need recalcute hole offset in f0 for every node) */ } @@ -2495,7 +2495,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -2505,7 +2505,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, if (spd_addr == (void *)0) continue; - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 67f3433..9d2f95d 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -222,7 +222,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in /* DRAM Control Register * F2:0x78 - * [ 3: 0] RdPtrInit ( Read Pointer Initial Value) + * [ 3: 0] RdPtrInit (Read Pointer Initial Value) * 0x03-0x00: reserved * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO) * 000 = reserved @@ -361,7 +361,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 01 = 3 bus clocks * 10 = 4 bus clocks * 11 = 5 bus clocks - * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, + * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel A, * BIOS should set it to reduce the power consumption) * Bit F(1207) M2 Package S1g1 Package * 0 N/A MA1_CLK1 N/A @@ -400,22 +400,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 10 = 2 bus clocks * 11 = 3 bus clocks * [13:12] Twrwr (Write to Write Timing) - * 00 = 1 bus clocks ( 0 idle cycle on the bus) - * 01 = 2 bus clocks ( 1 idle cycle on the bus) - * 10 = 3 bus clocks ( 2 idle cycles on the bus) + * 00 = 1 bus clocks (0 idle cycle on the bus) + * 01 = 2 bus clocks (1 idle cycle on the bus) + * 10 = 3 bus clocks (2 idle cycles on the bus) * 11 = Reserved - * [15:14] Trdrd ( Read to Read Timing) - * 00 = 2 bus clocks ( 1 idle cycle on the bus) - * 01 = 3 bus clocks ( 2 idle cycles on the bus) - * 10 = 4 bus clocks ( 3 idle cycles on the bus) - * 11 = 5 bus clocks ( 4 idle cycles on the bus) + * [15:14] Trdrd (Read to Read Timing) + * 00 = 2 bus clocks (1 idle cycle on the bus) + * 01 = 3 bus clocks (2 idle cycles on the bus) + * 10 = 4 bus clocks (3 idle cycles on the bus) + * 11 = 5 bus clocks (4 idle cycles on the bus) * [17:16] Tref (Refresh Rate) * 00 = Undefined behavior * 01 = Reserved * 10 = Refresh interval of 7.8 microseconds * 11 = Refresh interval of 3.9 microseconds * [19:18] Reserved - * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, + * [22:20] Trfc0 (Auto-Refresh Row Cycle Time for the Logical DIMM0, * based on DRAM density and speed) * 000 = 75 ns (all speeds, 256Mbit) * 001 = 105 ns (all speeds, 512Mbit) @@ -425,11 +425,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 101 = reserved * 110 = reserved * 111 = reserved - * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, + * [25:23] Trfc1 (Auto-Refresh Row Cycle Time for the Logical DIMM1, * based on DRAM density and speed) - * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, + * [28:26] Trfc2 (Auto-Refresh Row Cycle Time for the Logical DIMM2, * based on DRAM density and speed) - * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, + * [31:29] Trfc3 (Auto-Refresh Row Cycle Time for the Logical DIMM3, * based on DRAM density and speed) */ PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8), @@ -438,7 +438,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 0: 0] InitDram (Initialize DRAM) * 1 = write 1 cause DRAM controller to execute the DRAM * initialization, when done it read to 0 - * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command ) + * [ 1: 1] ExitSelfRef (Exit Self Refresh Command) * 1 = write 1 causes the DRAM controller to bring the DRAMs out * for self refresh mode * [ 3: 2] Reserved @@ -448,19 +448,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 10 = 150 ohms * 11 = 50 ohms * [ 6: 6] Reserved - * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode) + * [ 7: 7] DramDrvWeak (DRAM Drivers Weak Mode) * 0 = Normal drive strength mode. * 1 = Weak drive strength mode * [ 8: 8] ParEn (Parity Enable) * 1 = Enable address parity computation output, PAR, * and enables the parity error input, ERR * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) - * 1 = Enable high temperature ( two times normal ) + * 1 = Enable high temperature (two times normal) * self refresh rate - * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes) + * [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes) * 0 = 64-byte mode * 1 = 32-byte mode - * [11:11] Width128 ( Width of DRAM interface) + * [11:11] Width128 (Width of DRAM interface) * 0 = the controller DRAM interface is 64-bits wide * 1 = the controller DRAM interface is 128-bits wide * [12:12] X4Dimm (DIMM 0 is x4) @@ -469,19 +469,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [15:15] X4Dimm (DIMM 3 is x4) * 0 = DIMM is not x4 * 1 = x4 DIMM present - * [16:16] UnBuffDimm ( Unbuffered DIMMs) + * [16:16] UnBuffDimm (Unbuffered DIMMs) * 0 = Buffered DIMMs * 1 = Unbuffered DIMMs * [18:17] Reserved - * [19:19] DimmEccEn ( DIMM ECC Enable ) + * [19:19] DimmEccEn (DIMM ECC Enable) * 1 = ECC checking is being enabled for all DIMMs on the DRAM - * controller ( Through F3 0x44[EccEn]) + * controller (Through F3 0x44[EccEn]) * [31:20] Reserved */ PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010, /* DRAM Config High Register * F2:0x94 - * [ 0: 2] MemClkFreq ( Memory Clock Frequency) + * [ 0: 2] MemClkFreq (Memory Clock Frequency) * 000 = 200MHz * 001 = 266MHz * 010 = 333MHz @@ -490,25 +490,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 3: 3] MemClkFreqVal (Memory Clock Frequency Valid) * 1 = BIOS need to set the bit when setting up MemClkFreq to * the proper value - * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) + * [ 7: 4] MaxAsyncLat (Maximum Asynchronous Latency) * 0000 = 0 ns * ... * 1111 = 15 ns * [11: 8] Reserved - * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 + * [12:12] RDqsEn (Read DQS Enable) This bit is only be set if x8 * registered DIMMs are present in the system * 0 = DM pins function as data mask pins * 1 = DM pins function as read DQS pins * [13:13] Reserved - * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit + * [14:14] DisDramInterface (Disable the DRAM interface) When this bit * is set, the DRAM controller is disabled, and interface in low power * state * 0 = Enabled (default) * 1 = Disabled - * [15:15] PowerDownEn ( Power Down Mode Enable ) + * [15:15] PowerDownEn (Power Down Mode Enable) * 0 = Disabled (default) * 1 = Enabled - * [16:16] PowerDown ( Power Down Mode ) + * [16:16] PowerDown (Power Down Mode) * 0 = Channel CKE Control * 1 = Chip Select CKE Control * [17:17] FourRankSODimm (Four Rank SO-DIMM) @@ -526,17 +526,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * i.e., these signals are driven for two MEMCLK cycles * rather than one * [21:21] Reserved - * [22:22] BankSwizzleMode ( Bank Swizzle Mode), + * [22:22] BankSwizzleMode (Bank Swizzle Mode), * 0 = Disabled (default) * 1 = Enabled * [23:23] Reserved - * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum) + * [27:24] DcqBypassMax (DRAM Controller Queue Bypass Maximum) * 0000 = No bypass; the oldest request is never bypassed * 0001 = The oldest request may be bypassed no more than 1 time * ... * 1111 = The oldest request may be bypassed no more than 15\ * times - * [31:28] FourActWindow ( Four Bank Activate Window) , not more than + * [31:28] FourActWindow (Four Bank Activate Window) , not more than * 4 banks in a 8 bank device are activated * 0000 = No tFAW window restriction * 0001 = 8 MEMCLK cycles @@ -552,11 +552,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * when set, this bit indicates that the memory clear function * is complete. Only clear by reset. BIOS should not write or * read the DRAM until this bit is set by hardware - * [ 1: 1] DisableJitter ( Disable Jitter) + * [ 1: 1] DisableJitter (Disable Jitter) * When set the DDR compensation circuit will not change the * values unless the change is more than one step from the * current value - * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count) + * [ 3: 2] RdWrQByp (Read/Write Queue Bypass Count) * 00 = 2 * 01 = 4 * 10 = 8 @@ -565,11 +565,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1 When bit enables support for mismatched DIMMs when using * 128-bit DRAM interface, the Width128 no effect, only for * AM2 and s1g1 - * [ 5: 5] DCC_EN ( Dynamic Idle Cycle Counter Enable) + * [ 5: 5] DCC_EN (Dynamic Idle Cycle Counter Enable) * When set to 1, indicates that each entry in the page tables * dynamically adjusts the idle cycle limit based on page * Conflict/Page Miss (PC/PM) traffic - * [ 8: 6] ILD_lmt ( Idle Cycle Limit) + * [ 8: 6] ILD_lmt (Idle Cycle Limit) * 000 = 0 cycles * 001 = 4 cycles * 010 = 8 cycles @@ -578,16 +578,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 101 = 64 cycles * 110 = 128 cycles * 111 = 256 cycles - * [ 9: 9] DramEnabled ( DRAM Enabled) + * [ 9: 9] DramEnabled (DRAM Enabled) * When Set, this bit indicates that the DRAM is enabled, this * bit is set by hardware after DRAM initialization or on an exit * from self refresh. The DRAM controller is initialized after the - * hardware-controlled initialization process ( initiated by the + * hardware-controlled initialization process (initiated by the * F2 0x90[DramInit]) completes or when the BIOS-controlled * initialization process completes (F2 0x7c(EnDramInit] is * written from 1 to 0) * [23:10] Reserved - * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, + * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel B, * BIOS should set it to reduce the power consumption) * Bit F(1207) M2 Package S1g1 Package * 0 N/A MA1_CLK1 N/A @@ -785,7 +785,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) rank == 4 two side , and four ranks total Some one side two ranks, because of stacked */ - if ((value != 1) && (value != 2) && (value != 4 )) { + if ((value != 1) && (value != 2) && (value != 4)) { goto val_err; } sz->rank = value; @@ -797,9 +797,9 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) if (value < 0) goto hw_err; value &= 0xff; value = log2(value); - if (value <=4 ) value += 8; // add back to 1G to high + if (value <=4) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines - if ( value != (sz->per_rank)) { + if (value != (sz->per_rank)) { printk(BIOS_ERR, "Bad RANK Size --\n"); goto val_err; } @@ -836,12 +836,12 @@ static void set_dimm_size(const struct mem_controller *ctrl, /* Make certain side1 of the dimm is at least 128MB */ if (sz->per_rank >= 27) { - base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + base0 = (1 << ((sz->per_rank - 27) + 19)) | 1; } /* Make certain side2 of the dimm is at least 128MB */ if (sz->rank > 1) { // 2 ranks or 4 ranks - base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + base1 = (1 << ((sz->per_rank - 27) + 19)) | 1; } /* Double the size if we are using dual channel memory */ @@ -932,7 +932,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, struct mem_info *meminfo) { static const uint8_t cs_map_aaa[24] = { - /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ + /* (bank = 2, row = 13, col = 9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ //Bank2 0, 1, 3, 0, 2, 6, @@ -954,7 +954,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, map &= ~(0xf << (index * 4)); #if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { - map &= ~(0xf << ( (index + 2) * 4)); + map &= ~(0xf << ((index + 2) * 4)); } #endif @@ -965,7 +965,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, map |= temp_map << (index*4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { - map |= temp_map << ( (index + 2) * 4); + map |= temp_map << ((index + 2) * 4); } #endif } @@ -1018,7 +1018,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, limit = (limit_k << 2); limit &= 0xffff0000; limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); + limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; base |= (0 << 8) | (1<<1) | (1<<0); @@ -1136,7 +1136,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, } value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - cs_mode =( value >> ((index>>1)*4)) & 0xf; + cs_mode =(value >> ((index>>1)*4)) & 0xf; if (common_cs_mode == 0xff) { common_cs_mode = cs_mode; } @@ -1351,8 +1351,8 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, if (is_opteron(ctrl)) { #if 0 - if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) { - meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffered dimm + if (registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1))) { + meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm // die("Mixed buffered and registered dimms not supported"); } //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM @@ -1441,7 +1441,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i * Keep them at the end to see other mismatches (if any). */ 18, /* *Supported CAS Latencies */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; @@ -1647,7 +1647,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if ( cpuid1.edx & 0x02 ) { + if (cpuid1.edx & 0x02) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -1663,9 +1663,9 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) index = fid_start>>25; } - if (index>12) return divisor; + if (index > 12) return divisor; - if (i>3) return divisor; + if (i > 3) return divisor; return dv_a[index * 4+i]; @@ -1748,7 +1748,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig printk_raminit("\t\tvalue2: %08x\n", value); /* Only increase the latency if we decrease the clock */ - if (value >= *min_cycle_time ) { + if (value >= *min_cycle_time) { if (value < new_cycle_time) { new_cycle_time = value; new_latency = latency; @@ -1763,7 +1763,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig } - if (new_latency > 6){ + if (new_latency > 6) { return 1; } @@ -2052,7 +2052,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask, unsigned TT_REG, - unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX ) + unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX) { unsigned clocks, old_clocks; uint32_t dtl; @@ -2181,7 +2181,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl, value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us.... if (value < 0) return -1; - if (value == 1 ) { + if (value == 1) { value = 3; } else { value = 2; @@ -2267,7 +2267,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, mask_single_rank |= 1<<i; } - if (meminfo->sz[i].col==10) { + if (meminfo->sz[i].col == 10) { mask_page_1k |= 1<<i; } @@ -2278,17 +2278,17 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, rank = meminfo->sz[i].rank; #endif - if (value==4) { + if (value == 4) { mask_x4 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x4 |= 1<<(i+2); } #endif - } else if (value==16) { + } else if (value == 16) { mask_x16 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x16 |= 1<<(i+2); } #endif @@ -2340,7 +2340,7 @@ static void set_DramTerm(const struct mem_controller *ctrl, if (param->divisor == 100) { //DDR2 800 if (meminfo->is_Width128) { - if (count_ones(meminfo->dimm_mask & 0x0f)==2) { + if (count_ones(meminfo->dimm_mask & 0x0f) == 2) { odt = 3; //50 ohms } } @@ -2503,7 +2503,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2524,23 +2524,23 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * { uint32_t dword; uint32_t dwordx; -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ unsigned SlowAccessMode = 0; #endif -#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT == 0x0104 /* DDR2 and REG */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; switch (meminfo->memclk_set) { case DCH_MemClkFreq_266MHz: - if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { dwordx = 0x002f2700; } break; case DCH_MemClkFreq_333MHz: - if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there? dwordx = 0x002f2f00; } @@ -2553,7 +2553,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT == 0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2593,7 +2593,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT == 0x0004 /* DDR2 and unbuffered */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; @@ -2609,7 +2609,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * if (dimm_mask == 0x03) { SlowAccessMode = 1; dword = 0x00111322; - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) { switch (meminfo->single_rank_mask) { case 0x03: dwordx = 0x00002f00; //x8 single Rank @@ -2620,14 +2620,14 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * default: dwordx = 0x00372f00; //x8 single Rank and double Rank mixed } - } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { + } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed - } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { + } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed } } else { - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank dwordx = 0x002f2f00; } else { dwordx = 0x002b2f00; @@ -2639,7 +2639,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * if (dimm_mask == 0x03) { SlowAccessMode = 1; dword = 0x00111322; - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) { switch (meminfo->single_rank_mask) { case 0x03: dwordx = 0x00302220; //x8 single Rank @@ -2676,7 +2676,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2707,7 +2707,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CONFIG_CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE == 0x10 //only need to set for reg and x8 uint32_t dch; @@ -2749,7 +2749,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, for (i = 0; i < DIMM_SOCKETS; i++) { int rc; if (!(meminfo->dimm_mask & (1 << i)) && - !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) { + !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { continue; } printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i); @@ -2844,7 +2844,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); - printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { @@ -2852,24 +2852,24 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2881,7 +2881,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo); - printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2911,17 +2911,17 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, carry_over = (4*1024*1024) - hole_startk; - for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); - limit += (carry_over << 2 ); - base += (carry_over << 2 ); + limit += (carry_over << 2); + base += (carry_over << 2); for (j = 0; j < controllers; j++) { pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit); - pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base ); + pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base); } } limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); @@ -2966,7 +2966,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2985,7 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ - for (i=0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -3038,7 +3038,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); /* if no memory installed, disabled the interface */ - if (sysinfo->meminfo[i].dimm_mask==0x00){ + if (sysinfo->meminfo[i].dimm_mask == 0x00) { dch |= DCH_DisDramInterface; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); @@ -3046,7 +3046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dch |= DCH_MemClkFreqVal; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); /* address timing and Output driver comp Control */ - set_misc_timing(ctrl+i, sysinfo->meminfo+i ); + set_misc_timing(ctrl+i, sysinfo->meminfo+i); } } @@ -3108,7 +3108,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "Initializing memory: "); int loops = 0; @@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* Wait until it is safe to touch memory */ do { dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); - } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); + } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 if (cpu_f0_f1[i]) { @@ -3136,7 +3136,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); - if (tsc.lo<tsc0[i].lo) { + if (tsc.lo < tsc0[i].lo) { tsc.hi--; } tsc.lo -= tsc0[i].lo; @@ -3176,7 +3176,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; sysinfo->mem_trained[i] = 0x80; // mem need to be trained @@ -3226,7 +3226,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -3236,7 +3236,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, if (spd_addr == (void *)0) continue; - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 9f0b8db..42a77da 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -60,7 +60,7 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct int i; sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); } @@ -91,7 +91,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_id if (hole_reg & 1) { unsigned hole_startk; hole_startk = (hole_reg & (0xff<<24)) >> 10; - if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + if ((dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { dword += ((4*1024*1024 - hole_startk)<<2); } } @@ -197,7 +197,7 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; - if (p==1) { buf = buf_b; } + if (p == 1) { buf = buf_b; } else { buf = buf_a; } set_FSBASE (addr>>24); @@ -243,7 +243,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned unsigned result = DQS_FAIL; if (Pass == DQS_FIRST_PASS) { - if (pattern==1) { + if (pattern == 1) { test_buf = (uint32_t *)TestPattern1; } else { @@ -285,13 +285,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); - if (value == value_test){ + if (value == value_test) { result = DQS_PASS; } } if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted - if (result==DQS_PASS) { + if (result == DQS_PASS) { result = DQS_FAIL; } else { @@ -409,7 +409,7 @@ static uint16_t get_exact_T1000(unsigned i) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if ( cpuid1.edx & 0x02 ) { + if (cpuid1.edx & 0x02) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -425,7 +425,7 @@ static uint16_t get_exact_T1000(unsigned i) index = fid_start>>25; } - if (index>12) return T1000_a[i]; + if (index > 12) return T1000_a[i]; return TT_a[index * 4+i]; @@ -437,14 +437,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) uint32_t dword; dword = 0x00000000; - for (i=1; i<=3; i++) { + for (i = 1; i <= 3; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); } dword = 0x2f2f2f2f; - for (i=5; i<=7; i++) { + for (i = 5; i <= 7; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); @@ -554,14 +554,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? - if (Pass==DQS_FIRST_PASS) { - for (i=0;i<16;i++) { + if (Pass == DQS_FIRST_PASS) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; } } else { - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; } @@ -581,13 +581,13 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st channel = 1; } - for ( ; (channel < 2) && (!Errors); channel++) + for (; (channel < 2) && (!Errors); channel++) { print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); /* for each rank */ /* there are four receiver pairs, loosely associated with CS */ - for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + for (receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; @@ -642,7 +642,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; } - while ( RcvrEnDly < 0xaf) { // Sweep Delay value here + while (RcvrEnDly < 0xaf) { // Sweep Delay value here print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); if (RcvrEnDly & 1) { @@ -841,7 +841,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif - return (CTLRMaxDelay==0xae)?1:0; + return (CTLRMaxDelay == 0xae)?1:0; } @@ -859,7 +859,7 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); shift = bytelane; - while (shift>3) { + while (shift > 3) { shift-=4; } shift <<= 3; // 8 bit @@ -879,13 +879,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe dword = 0; dqs_delay &= 0xff; - for (i=0;i<4;i++) { + for (i = 0; i < 4; i++) { dword |= dqs_delay<<(i*8); } index = 1 + channel * 0x20 + direction * 4; - for (i=0; i<2; i++) { + for (i = 0; i < 2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); } @@ -898,7 +898,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d) if (size_d & 1) { //need round up min_d++; } - return ( min_d + (size_d>>1)); + return (min_d + (size_d>>1)); } static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay) @@ -1026,10 +1026,10 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) ); } -static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) +static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern) { - if (pattern == 0){ + if (pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { @@ -1056,7 +1056,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign } bytelane = 0; - for (i=0;i<9*64/4;i++) { + for (i = 0; i < 9*64/4; i++) { __asm__ volatile ( "movl %%fs:(%1), %0\n\t" :"=b"(value): "a" (addr_lo) @@ -1066,7 +1066,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); - for (j=0;j<4*8;j+=8) { + for (j = 0; j < 4*8; j+=8) { if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } @@ -1116,8 +1116,8 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); - for (DQSDelay=0; DQSDelay<48; DQSDelay++) { - MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { + MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff = All positions passing (1= PASS) } for (ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 @@ -1138,7 +1138,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } - for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); @@ -1150,7 +1150,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5); ReadDQSTestPattern(TestAddr<<8, Pattern); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass + MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1 = pass print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO(TestAddr); FlushDQSTestPattern(TestAddr<<8, Pattern); @@ -1166,7 +1166,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, RnkDlySeqPassMax = 0; RnkDlyFilterMax = 0; RnkDlyFilterMin = 0; - for (DQSDelay=0; DQSDelay<48; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); @@ -1176,7 +1176,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) { RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -1194,7 +1194,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, else { print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); - if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ + if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW) { Errors |= SB_SMALLDQS; } else { @@ -1371,15 +1371,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in //SetupDqsPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); - if (is_Width128){ + if (is_Width128) { pattern = 1; - for (i=0;i<16*18;i++) { + for (i = 0; i < 16*18; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; - for (i=0; i<16*9;i++) { + for (i = 0; i < 16*9; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; } @@ -1397,7 +1397,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in channel = 1; } - while ( (channel<2) && (!Errors)) { + while ((channel < 2) && (!Errors)) { print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; @@ -1417,7 +1417,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in } channel++; - if (!is_Width128){ + if (!is_Width128) { //FIXME: 64MuxMode?? channel++; // skip channel if 64-bit mode } @@ -1458,7 +1458,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; InterFactor = 0xff - InterFactor; } @@ -1470,7 +1470,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay >>= 8; // /255 - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay += DQSDelay1; } else { @@ -1496,11 +1496,11 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info ByteLane = 8; for (channel = 0; channel < 2; channel++) { - for (i=0;i<2;i++) { + for (i = 0; i < 2; i++) { Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay); save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay); } @@ -1546,7 +1546,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; uint32_t dword; @@ -1568,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); dword = tsc1[i].lo + tsc0[i].lo; - if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + if ((dword < tsc1[i].lo) || (dword < tsc0[i].lo)) { tsc1[i].hi++; } tsc1[i].lo = dword; @@ -1583,7 +1583,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; if (!cpu_f0_f1[i]) continue; @@ -1591,7 +1591,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl do { tsc = rdtsc(); - } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); + } while ((tsc1[i].hi > tsc.hi) || ((tsc1[i].hi == tsc.hi) && (tsc1[i].lo > tsc.lo))); print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); } @@ -1661,8 +1661,8 @@ static unsigned int range_to_mtrr(unsigned int reg, #if CONFIG_MEM_TRAIN_SEQ != 1 printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + (type == MTRR_TYPE_UNCACHEABLE)?"UC": + ((type == MTRR_TYPE_WRBACK)?"WB":"Other") ); #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); @@ -1737,7 +1737,7 @@ static void clear_mtrr_dqs(unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - for (i=0x204;i<0x210;i++) { + for (i = 0x204; i < 0x210; i++) { wrmsr(i, msr); } @@ -1890,7 +1890,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } @@ -1901,7 +1901,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; @@ -1919,7 +1919,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if (train_DqsPos(ctrl+i, sysinfo)) goto out; @@ -1932,7 +1932,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; @@ -1948,7 +1948,7 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); } @@ -2004,7 +2004,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - if (train_DqsRcvrEn(ctrl, 2, sysinfo)){ + if (train_DqsRcvrEn(ctrl, 2, sysinfo)) { sysinfo->mem_trained[i]=0x83; // goto out; } @@ -2021,7 +2021,7 @@ out: #endif if (v) { - for (ii=0;ii<4;ii++) { + for (ii = 0; ii < 4; ii++) { print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 597b689..9e2d8a9 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -15,13 +15,13 @@ static int is_cpu_pre_c0(void) return 0; } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ +#define PCI_ADDR(BUS, DEV, FN, WHERE) (\ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x07) << 8) | \ ((WHERE) & 0xFF)) -#define PCI_DEV(BUS, DEV, FN) ( \ +#define PCI_DEV(BUS, DEV, FN) (\ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x7) << 8)) diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index fa03e4a..e6e79c8 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -50,9 +50,9 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int #if RES_DEBUG printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], - register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), + register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], - register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) + register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); #endif switch (register_values[i]) { @@ -103,7 +103,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int reg = read32(where); reg &= register_values[i+2]; reg |= register_values[i+3]; - write32( where, reg); + write32(where, reg); } break; #endif @@ -174,7 +174,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) reg = read32(where); reg &= register_values[i+1]; reg |= register_values[i+2]; - write32( where, reg); + write32(where, reg); #if 0 reg = read32(where); prink(BIOS_DEBUG, " RB %08x\n", reg); diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl index 6a9b69f..83d741e 100644 --- a/src/northbridge/amd/amdk8/util.asl +++ b/src/northbridge/amd/amdk8/util.asl @@ -44,9 +44,9 @@ Scope (\_SB) Method (DADD, 2, NotSerialized) { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) + Store(Arg1, Local0) + Store(Arg0, Local1) + Add(ShiftLeft(Local1,16), Local0, Local0) Return (Local0) } @@ -54,7 +54,7 @@ Scope (\_SB) Method (GHCE, 1, NotSerialized) // check if the HC enabled { Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } Else { Return (0x00) } } @@ -62,7 +62,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0) Return (Local0) } @@ -70,7 +70,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0) Return (Local0) } @@ -80,7 +80,7 @@ Scope (\_SB) Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Store (And (ShiftRight(Local1, Local2), 0xff), Local0) Return (Local0) } diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index bbdd2ed..9d3e86a 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -74,8 +74,8 @@ #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2) #define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) #define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index 61b2b2b..3847688 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -23,16 +23,16 @@ #define PT_M2 1 #define PT_S1 2 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 4 /* j loop constraint. 4=CL 6.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 4 /* k loop constraint. 9=400 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 4 /* j loop constraint. 4 = CL 6.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 4 /* k loop constraint. 9 = 400 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -208,7 +208,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /* For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /* For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -218,14 +218,14 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM1Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM1Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /* Number of DIMMs loading CH A*/ @@ -233,16 +233,16 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /* Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -252,16 +252,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -271,27 +271,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -319,9 +319,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM 0 - 3 Receiver Enable Delay*/ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -399,72 +399,72 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /* Platform Configuration */ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /* Dram Timing */ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /* Dram Configuration */ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /* Dram Power */ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /* Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -472,8 +472,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /* ECC */ #define NV_ECC 50 /* Dram ECC enable*/ @@ -484,14 +484,14 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /*Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_Parity 60 /* Parity Enable*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /* global function */ @@ -505,11 +505,11 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Get_ChannelPS_Cfg0( unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, +void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL); -void Get_ChannelPS_Cfg1( unsigned MAAdimms, unsigned Speed, unsigned MAAload, +void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); -void Get_ChannelPS_Cfg2( unsigned MAAdimms, unsigned Speed, unsigned MAAload, +void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); u8 MCTDefRet(void); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 16e67df..c521ee7 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -195,7 +195,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. Complete Hypertransport Bus Configuration * 2. SMBus Controller Initialized * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to * entry * 6. All var MTRRs reset to zero @@ -308,7 +308,7 @@ restartinit: MCTMemClr_D(pMCTstat,pDCTstatA); } - mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 + mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0)); // Node 0 print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; @@ -434,7 +434,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); } @@ -452,7 +452,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 2; DIMM++) { - if (DIMM==0) { + if (DIMM == 0) { index = 0; /* CHA Write Data Timing Low */ } else { if (pDCTstat->Speed >= 4) { @@ -461,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, break; } } - for (Dir=0;Dir<2;Dir++) {//RD/WR + for (Dir = 0;Dir < 2;Dir++) {//RD/WR p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); @@ -474,7 +474,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78 + Channel * 0x100; val = Get_NB32(dev, reg); val &= ~(0x3ff<<22); @@ -497,7 +497,7 @@ static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, * or normal ECC memory conditioning. */ - //FIXME: this function depends on pDCTstat Array ( with Node id ) - Is this really a problem? + //FIXME: this function depends on pDCTstat Array (with Node id) - Is this really a problem? u32 dev; u8 Node; @@ -650,7 +650,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(dev, reg); Set_NB32(devx, reg, val); reg += 4; - } while ( reg < 0x80); + } while (reg < 0x80); } else { break; /* stop at first absent Node */ } @@ -672,7 +672,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, u8 Node; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { // FIXME: callback to wrapper: mctDoWarmResetMemClr_D } else { // NV_DQSTrainCTL == 1 for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -723,7 +723,7 @@ static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, u8 Node; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { // callback to wrapper: mctDoWarmResetMemClr_D } else { // NV_DQSTrainCTL == 1 for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -745,7 +745,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, u32 reg; /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit){ + if (pDCTstat->DCTSysLimit) { reg = 0x110; do { @@ -834,7 +834,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst u32 reg_off = dct * 0x100; val = 1<<DisDramInterface; Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val); - /*To maximize power savings when DisDramInterface=1b, + /*To maximize power savings when DisDramInterface = 1b, all of the MemClkDis bits should also be set.*/ val = 0xFF000000; Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); @@ -997,7 +997,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, pDCTstat->CASL = pDCTstat->DIMMCASL; /* if "manual" memclock mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1; } @@ -1013,10 +1013,10 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0; - for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i); @@ -1062,13 +1062,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, if (Trc < val) Trc = val; - /* dev density=rank size/#devs per rank */ + /* dev density = rank size/#devs per rank */ byte = mctRead_SPD(smbaddr, SPD_BANKSZ); val = ((byte >> 5) | (byte << 3)) & 0xFF; val <<= 2; - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ + byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density = 2^(rows+columns+banks) */ if (byte == 4) { val >>= 4; } else if (byte == 8) { @@ -1260,7 +1260,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i]; mctAdjustAutoCycTmg_D(); @@ -1329,7 +1329,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16; val = 0; - for (i=4;i>0;i--) { + for (i = 4; i > 0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -1385,7 +1385,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, proposedFreq = 533; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); if (word < proposedFreq) proposedFreq = word; @@ -1426,9 +1426,9 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, CL1min = 0xFF; T1min = 0xFF; - for (k=K_MAX; k >= K_MIN; k--) { + for (k = K_MAX; k >= K_MIN; k--) { for (j = J_MIN; j <= J_MAX; j++) { - if (Sys_Capability_D(pMCTstat, pDCTstat, j, k) ) { + if (Sys_Capability_D(pMCTstat, pDCTstat, j, k)) { /* 1. check to see if DIMMi is populated. 2. check if DIMMi supports CLj and Tjk */ for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { @@ -1480,7 +1480,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); } - if ( pDCTstat->_2Tmode == 2) { + if (pDCTstat->_2Tmode == 2) { dev = pDCTstat->dev_dct; reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */ val = Get_NB32(dev, reg); @@ -1547,20 +1547,20 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Speed == 3) { if (pDCTstat->MAdimms[dct] == 4) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } else if (pDCTstat->Speed == 4){ + } else if (pDCTstat->Speed == 4) { if (pDCTstat->MAdimms[dct] != 1) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else { // FIXME: Skip for Ax versions if (pDCTstat->MAdimms[dct] == 4) { - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else if (pDCTstat->MAdimms[dct] == 4) { if (pDCTstat->Speed == 4) { - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } @@ -1604,7 +1604,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) - if ( mctGet_NVbits(NV_ECC)) + if (mctGet_NVbits(NV_ECC)) DramConfigLo |= 1 << DimmEcEn; DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); @@ -1633,7 +1633,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */ /* Check for Quadrank DIMM presence */ - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { byte = mctGet_NVbits(NV_4RANKType); if (byte == 2) DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */ @@ -1641,7 +1641,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ } - if (0) /* call back not needed mctOverrideDcqBypMax_D ) */ + if (0) /* call back not needed mctOverrideDcqBypMax_D) */ val = mctGet_NVbits(NV_BYPMAX); else val = 0x0f; // recommended setting (default) @@ -1676,7 +1676,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, 1. We will assume that MemClkDis field has been preset prior to this point. 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks ==0 */ + NV_AllMemClks <>0 AND SB_DiagClks == 0 */ /* Dram Timing Low (owns Clock Enable bits) */ @@ -1795,7 +1795,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, /* 13 Rows is smallest dev size */ byte |= Rows - 13; /* CCCBRR internal encode */ - for (dword=0; dword < 12; dword++) { + for (dword = 0; dword < 12; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -1810,7 +1810,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0; - byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ if (Banks == 8) byte -= 2; /* 3 banks - 5 */ else @@ -1881,7 +1881,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { smbaddr = Get_DIMMAddress_D(pDCTstat, i); smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); @@ -1952,7 +1952,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, _DSpareEn = 0; - /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -1967,7 +1967,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -1981,13 +1981,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/ val = Get_NB32(dev, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/ val = Get_NB32(dev, reg); val >>= 19; @@ -2003,7 +2003,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2) + reg_off; if (_DSpareEn) { @@ -2022,7 +2022,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /* bank present but disabled?*/ - if ( pDCTstat->CSTestFail & (1 << p)) { + if (pDCTstat->CSTestFail & (1 << p)) { /* DRAM CS Base b Address Register offset */ reg = (p << 2) + 0x40 + reg_off; val = 1 << TestFail; @@ -2102,7 +2102,7 @@ static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat, byte = mctRead_SPD(DIMMi, word); /* DIMMi speed */ if (Tk < byte) { ret = 1; - } else if (byte == 0){ + } else if (byte == 0) { pDCTstat->ErrStatus |= 1<<SB_NoCycTime; ret = 1; } else { @@ -2121,12 +2121,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */ u16 i, j, k; @@ -2159,7 +2159,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, print_tx("\t DIMMPresence: smbaddr=", smbaddr); if (smbaddr) { Checksum = 0; - for (Index=0; Index < 64; Index++){ + for (Index = 0; Index < 64; Index++) { int status; status = mctRead_SPD(smbaddr, Index); if (status < 0) @@ -2250,7 +2250,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /*Check if SPD diag bit 'analysis probe installed' is set */ byte = mctRead_SPD(smbaddr, SPD_ATTRIB); - if ( byte & JED_PROBEMSK ) + if (byte & JED_PROBEMSK) pDCTstat->Status |= 1<<SB_DiagClks; byte = mctRead_SPD(smbaddr, SPD_DMBANKS); @@ -2260,7 +2260,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, byte++; /* ranks */ if (byte > 2) { /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if ( pDCTstat->DimmQRPresent == 0) { + if (pDCTstat->DimmQRPresent == 0) { MaxDimms <<= 1; } if (i < DimmSlots) { @@ -2274,7 +2274,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, if (devwidth == 16) bytex = 4; else if (devwidth == 4) - bytex=16; + bytex = 16; if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ @@ -2330,7 +2330,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } } if (pDCTstat->DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) { + if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { /* all DIMMs are ECC capable */ pDCTstat->Status |= 1<<SB_ECCDIMMs; } @@ -2418,7 +2418,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, } else { /* Configure DCT1 if unganged and enabled*/ if (!pDCTstat->GangedMode) { - if ( pDCTstat->DIMMValidDCT[1] > 0) { + if (pDCTstat->DIMMValidDCT[1] > 0) { print_t("\tmct_initDCT: DCTInit_D 1\n"); err_code = pDCTstat->ErrCode; /* save DCT0 errors */ pDCTstat->ErrCode = 0; @@ -2497,7 +2497,7 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat, if (byte != bytex) { pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); } else { - if ( mctGet_NVbits(NV_Unganged) ) + if (mctGet_NVbits(NV_Unganged)) pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) { @@ -2595,7 +2595,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98 + (i * 0x100); Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */ Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */ @@ -2615,7 +2615,7 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) print_tx("mct_SyncDCTsReady: Node ", pDCTstat->Node_ID); dev = pDCTstat->dev_dct; - if ((pDCTstat->DIMMValidDCT[0] ) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */ + if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */ do { val = Get_NB32(dev, 0x110); } while (!(val & (1 << DramEnabled))); @@ -2629,7 +2629,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!pDCTstat->GangedMode) { - if (dct == 0 ) { + if (dct == 0) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; if (pDCTstat->DIMMValidDCT[dct] == 0) pDCTstat->ErrCode = SC_StopError; @@ -2648,7 +2648,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, { u8 ret; - if ( dct == 0) { + if (dct == 0) { SPDCalcWidth_D(pMCTstat, pDCTstat); ret = mct_setMode(pMCTstat, pDCTstat); } else { @@ -2752,7 +2752,7 @@ static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, { u8 ret; - if ( dct == 0) + if (dct == 0) ret = DIMMPresence_D(pMCTstat, pDCTstat); else ret = pDCTstat->ErrCode; @@ -2777,7 +2777,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; Set_OtherTiming(pMCTstat, pDCTstat, 0); } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) { + if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; Set_OtherTiming(pMCTstat, pDCTstat, 1); } @@ -3022,8 +3022,8 @@ static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); byte = val & 0xFF; if (byte < Smallest_0) @@ -3153,8 +3153,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x00E000E0; byte = (val >> 5) & 0xFF; @@ -3192,11 +3192,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -3308,14 +3308,14 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, /* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map; /* get base/limit from Node0 */ reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); - Drambase = val >> ( 16 + 3); + Drambase = val >> (16 + 3); reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); @@ -3335,7 +3335,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, val |= Dramlimit; Set_NB32(devx, reg, val); - if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) { + if (pMCTstat->GStatus & (1 << GSB_HWHole)) { reg = 0xF0; val = Get_NB32(devx, reg); val |= (1 << DramMemHoistValid); @@ -3476,7 +3476,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait(dev, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -3652,8 +3652,8 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, u32 dev = pDCTstat->dev_dct; // FIXME: skip for Ax - if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz - for (i=0; i < 2; i++) { + if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz + for (i = 0; i < 2; i++) { reg_off = 0x100 * i; Set_NB32(dev, 0x98 + reg_off, 0x0D000030); Set_NB32(dev, 0x9C + reg_off, 0x00000806); @@ -3667,7 +3667,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax - if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz + if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz *dqs_pos = 32; } } @@ -3783,10 +3783,10 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) + * - a) Disable Compensation (F2[1, 0]9C_x08[30]) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30] ) + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 @@ -3970,7 +3970,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { mct_Wait(10000); /* Wait 50 us*/ val = Get_NB32(dev, 0x110); - if ( val & (1 << DramEnabled)) { + if (val & (1 << DramEnabled)) { /* If 50 us expires while DramEnable =0 then do the following */ val = Get_NB32(dev, 0x90 + reg_off); val &= ~(1 << Width128); /* Program Width128 = 0 */ @@ -3990,9 +3990,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { /* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index b580457..4e1a909 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -30,16 +30,16 @@ #define PT_S1 2 #define PT_GR 3 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -289,7 +289,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -306,7 +306,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -316,15 +316,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -332,17 +332,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -352,16 +352,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -371,27 +371,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -415,9 +415,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -483,15 +483,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; // NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller) - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ // NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/ #define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/ @@ -587,73 +587,73 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -661,8 +661,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -674,13 +674,13 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fd39b38..fbfe988 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -39,7 +39,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi) __asm__ volatile ( "rdtsc" : "=a" (*lo), "=d"(*hi) - ); + ); } @@ -61,7 +61,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for (i=31; i>0; i--) { + for (i = 31; i > 0; i--) { if (x & (1<<i)) { ret = i; break; @@ -78,7 +78,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -88,9 +88,9 @@ static u32 bsf(u32 x) return ret; } -#define _MFENCE asm volatile ( "mfence") +#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ( "sfence" ) +#define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") @@ -343,7 +343,7 @@ static u32 stream_to_int(u8 const *p) val = 0; - for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index 327acbc..e290333 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -187,7 +187,7 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, } while (*p != 0xFF) { - if ((MAAdimms == *(p+10)) || (*(p+10 ) == 0xFE)) { + if ((MAAdimms == *(p+10)) || (*(p+10) == 0xFE)) { if ((*p == Speed) || (*p == 0xFE)) { if (MAAload <= *(p+1)) { *AddrTmgCTL = stream_to_int((u8*)(p+2)); diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index cac2342..7e1d91a 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -96,7 +96,7 @@ static const u8 Table_ATC_ODC_D_Ax[] = { }; -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index d5956b1..705bd91 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -37,7 +37,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, /* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ // FIXME: Check for Cx - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ beforeInterleaveChannels_D(pDCTstatA, &enabled); if (DctSelIntLvAddr & 1) { @@ -71,7 +71,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, if (dct1_size == dct0_size) { dct1_size = 0; DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size ) { + } else if (dct1_size > dct0_size) { dct1_size = dct0_size; DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ } diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index e8d26da..4da021b 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -47,7 +47,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */ val = Get_NB32(dev, reg); - if ( val & (1<<CSEnable)) { + if (val & (1<<CSEnable)) { EnChipSels++; reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */ val = Get_NB32(dev, reg); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 67ff823..e0c7761 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -221,12 +221,12 @@ static void SetEccDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, u8 channel; u8 direction; - for (channel = 0; channel < 2; channel++){ + for (channel = 0; channel < 2; channel++) { for (direction = 0; direction < 2; direction++) { pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -251,7 +251,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); DQSDelay1 = pDCTstat->DQSDelay; - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; } else { DQSDelay = DQSDelay1 - DQSDelay0; @@ -263,7 +263,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, DQSDelay >>= 8; // /256 - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay1 - DQSDelay; } else { DQSDelay += DQSDelay1; @@ -320,7 +320,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ continue; - for ( DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { + for (DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { pDCTstat->DQSDelay = DQSWrDelay; pDCTstat->Direction = DQS_WRITEDIR; mct_SetDQSDelayAllCSR_D(pMCTstat, pDCTstat, cs_start); @@ -362,7 +362,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -383,7 +383,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -411,11 +411,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1 << SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -458,10 +458,10 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, dqsDelay_end = 32; } - /* Bitmapped status per delay setting, 0xff=All positions + /* Bitmapped status per delay setting, 0xff = All positions * passing (1= PASS). Set the entire array. */ - for (DQSDelay=0; DQSDelay<64; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 64; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xFF; } @@ -481,7 +481,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, } print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ if (pDCTstat->Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); @@ -504,7 +504,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ - tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */ + tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0 = fail, 1 = pass */ if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) { goto skipLocMiddle; @@ -538,7 +538,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) { RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -552,7 +552,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, Errors |= 1 << SB_NODQSPOS; /* no passing window */ } else { print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4); - if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)){ + if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)) { Errors |= 1 << SB_SMALLDQS; } else { u8 middle_dqs; @@ -631,7 +631,7 @@ static u8 MiddleDQS_D(u8 min, u8 max) size = max-min; if (size % 2) size++; // round up if the size isn't even. - return ( min + (size >> 1)); + return (min + (size >> 1)); } @@ -679,10 +679,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, reg_off = 0; } - if (ChipSel < MAX_CS_SUPPORTED){ + if (ChipSel < MAX_CS_SUPPORTED) { reg = 0x40 + (ChipSel << 2) + reg_off; val = Get_NB32(dev, reg); - if (val & ( 1 << 0)) + if (val & (1 << 0)) ret = 1; } @@ -775,8 +775,8 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS } bytelane = 0; /* bytelane counter */ - bitmap = 0xFF; /* bytelane test bitmap, 1=pass */ - for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ + bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ + for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); value_test = *test_buf; @@ -797,7 +797,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS if (!bitmap) break; - if (bytelane == 0){ + if (bytelane == 0) { if (pattern == 1) { //dual channel addr_lo += 8; //skip over other channel's data test_buf += 2; @@ -815,7 +815,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo) { /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0){ + if (pDCTstat->Pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { FlushDQSTestPattern_L18(addr_lo); @@ -1036,7 +1036,7 @@ static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, for (ChipSel = cs_start; ChipSel < (cs_start + 2); ChipSel++) { - if ( mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { for (ByteLane = 0; ByteLane < 8; ByteLane++) { pDCTstat->ByteLane = ByteLane; mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -1088,9 +1088,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val &= ~0x0F; - /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { + if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; dword = Get_NB32(dev, reg); dword &= 0xfffff800; @@ -1104,7 +1104,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase; /* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 5c1dc3a..59ebd77 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -40,7 +40,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -121,10 +121,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if (pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); @@ -176,7 +176,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -239,8 +239,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if ((val & 3)==3) { /* Node has dram populated*/ - if ( isDramECCEn_D(pDCTstat)) { + if ((val & 3) == 3) { /* Node has dram populated*/ + if (isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -300,8 +300,8 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0){ + for (i = 0; i < ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0) { reg = 0x90 + i * 0x100; /* Dram Config Low */ val = Get_NB32(dev, reg); if (val & (1<<DimmEcEn)) { diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index a13d4e2..41a479b 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -31,12 +31,12 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, DramTimingLo = val; /* Dram Timing Low (owns Clock Enable bits) */ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if (mctGet_NVbits(NV_AllMemClks)==0) { + if (mctGet_NVbits(NV_AllMemClks) == 0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ if (!(pDCTstat->Status & (1<<SB_DiagClks))) { - for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if (val<8) { + if (val < 8) { if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 5e91947..deb0f8a 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -35,11 +35,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */ @@ -83,8 +83,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -115,10 +115,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -177,17 +177,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8; /* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; - val |= ( 1 << 11); /* set MTRR valid*/ + val |= (1 << 11); /* set MTRR valid*/ addr++; _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ val = curLimit; @@ -217,9 +217,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; @@ -238,7 +238,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while ( addr < 0x20C) { + while (addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 32c3199..389d56b 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -72,7 +72,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, NodesWmem++; Base &= 0xFFFF0000; /* Base[39:8] */ - if (pDCTstat->Status & (1 << SB_HWHole )) { + if (pDCTstat->Status & (1 << SB_HWHole)) { /* to get true amount of dram, * subtract out memory hole if HW dram remapping */ @@ -87,7 +87,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); if (DctSelBase) { DctSelBase <<= 8; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { DctSelBase -= HWHoleSz; } @@ -104,7 +104,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, MemSize &= 0xFFFF0000; MemSize += 0x00010000; MemSize -= Base; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { MemSize -= HWHoleSz; } if (Node == 0) { @@ -144,7 +144,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat,pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; @@ -185,7 +185,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if ( Node == 0) { + if (Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 95afebf..081e8ac 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -36,13 +36,13 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) { /* Bug#10695:One MEMCLK Bubble Writes Don't Do X4 X8 Switching Correctly * Solution: BIOS should set DRAM Timing High[Twrwr] > 00b - * ( F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B + * (F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B * FIXME: check if this is still required. */ uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (!(val & (3<<12) )) + if (!(val & (3<<12))) val |= 1<<12; } return val; @@ -69,7 +69,7 @@ void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) val |= 1<<BurstLength32; Set_NB32(dev, reg, val); - reg = 0x88 + reg_off; /* cx=Dram Timing Lo */ + reg = 0x88 + reg_off; /* cx = Dram Timing Lo */ val = Get_NB32(dev, reg); val |= 0x000F0000; /* Trc = 0Fh */ Set_NB32(dev, reg, val); @@ -89,7 +89,7 @@ void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat, * NOTE -- this has been documented with a note at the end of this * section in the BKDG (although, admittedly, the note does not really * stand out). - * Silicon Status: Fixed in Rev B ( confirm) + * Silicon Status: Fixed in Rev B (confirm) * FIXME: check this. */ @@ -149,14 +149,14 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; index = 0; - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { index_reg = 0x98 + 0x100 * Channel; val = Get_NB32_index_wait(dev, index_reg, 0x0d004007); val |= 0x3ff; Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val); } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { if (pDCTstat->GangedMode && Channel) break; reg_off = 0x100 * Channel; @@ -167,11 +167,11 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg_off = 0x100 * Channel; val = 0; index_reg = 0x98 + reg_off; - for ( index = 0x30; index < (0x45 + 1); index++) { + for (index = 0x30; index < (0x45 + 1); index++) { Set_NB32_index_wait(dev, index_reg, index, val); } } @@ -265,7 +265,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) print_tx("NB COF:", valy >> NbDid); val = valy/valx; - if ((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ + if ((val == 3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ ret = 1; return ret; @@ -296,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) } dev = pDCTstat->dev_dct; index = 0x0D00E001; - for (ch=ch_start; ch<ch_end; ch++) { + for (ch = ch_start; ch < ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); val &= ~(0xf0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 510cf0d..a87cea8 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -86,7 +86,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -161,7 +161,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_t("TrainRcvrEn: 1\n"); cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -261,7 +261,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { pDCTstat->DqsRcvEn_Pass = 0; } else { - pDCTstat->DqsRcvEn_Pass=0xFF; + pDCTstat->DqsRcvEn_Pass = 0xFF; } pDCTstat->DqsRcvEn_Saved = 0; @@ -446,7 +446,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -456,7 +456,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -472,10 +472,10 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for (Receiver = 0; Receiver<8; Receiver+=2) { + for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -494,7 +494,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { - if (pDCTstat->DIMMValidDCT[dct] == 0 ) { + if (pDCTstat->DIMMValidDCT[dct] == 0) { return 8; } else { return 0; @@ -526,7 +526,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; } - for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78 + 0x100 * ch; val = Get_NB32(dev, reg); val &= ~(1 << DqsRcvEnTrain); @@ -562,14 +562,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } - /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -661,7 +661,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ valx = (val + 3) << 2; val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - SubTotal *= ((val & 0x1f) + 4 ) * 3; + SubTotal *= ((val & 0x1f) + 4) * 3; SubTotal /= valx; if (SubTotal % valx) { /* round up */ @@ -723,7 +723,7 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, mask_Saved &= mask_Pass; p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; } - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* cmp per byte lane */ if (mask_Pass & (1 << i)) { if (!(mask_Saved & (1 << i))) { @@ -757,7 +757,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { - if (pattern==1) { + if (pattern == 1) { test_buf = (u8 *)TestPattern1_D; } else { test_buf = (u8 *)TestPattern0_D; @@ -769,13 +769,13 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); addr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { addr += 8; /* second channel */ test_buf += 8; } print_debug_dqs_pair("\t\t\t\t\t\t test_buf = ", (u32)test_buf, " | addr_lo = ", addr, 4); - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { value = read32_fs(addr); print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4); @@ -790,7 +790,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { /* if first pass, at least one byte lane pass - * ,then DQS_PASS=1 and will set to related reg. + * ,then DQS_PASS = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0) { result = DQS_PASS; @@ -800,7 +800,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, } else { /* if second pass, at least one byte lane fail - * ,then DQS_FAIL=1 and will set to related reg. + * ,then DQS_FAIL = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0xFF) { result = DQS_FAIL; @@ -843,7 +843,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++) { InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -867,8 +867,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, // FIXME: add Cx support dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); @@ -876,14 +876,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword); } @@ -969,7 +969,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1081,5 +1081,5 @@ void mct_Wait(u32 cycles) saved = lo; do { _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles ); + } while (lo - saved < cycles); } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index e059e1e..c1b1133 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -50,7 +50,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index bd3c503..c7c92ac 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -62,7 +62,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; // print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); // print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); - for ( i=0;i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); @@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ //val += Pass1MemClkDly; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 0eb3c61..a47990a 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -149,7 +149,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); @@ -164,7 +164,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -185,7 +185,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -195,7 +195,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -213,7 +213,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; // for safe - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; @@ -247,7 +247,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8; _EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i]; @@ -292,11 +292,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp>Max) { + if (tmp > Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -382,7 +382,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4 ) * 3; + val = ((val & 0x1f) + 4) * 3; /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ valxx = val << 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 08d8d43..da2a4fe 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2625,7 +2625,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. BSP in Big Real Mode * 2. Stack at SS:SP, located somewhere between A000:0000 and F000:FFFF * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL = -1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry * 6. All var MTRRs reset to zero * 7. State of NB_CFG.DisDatMsk set properly on all CPUs @@ -3819,7 +3819,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); } @@ -3859,7 +3859,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); @@ -3993,7 +3993,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(dev, reg); Set_NB32(devx, reg, val); reg += 4; - } while ( reg < 0x80); + } while (reg < 0x80); } else { break; /* stop at first absent Node */ } @@ -4015,7 +4015,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, uint32_t dword; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /* FIXME: callback to wrapper: mctDoWarmResetMemClr_D */ } else { /* NV_DQSTrainCTL == 1 */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -4080,7 +4080,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Start\n", __func__); /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit){ + if (pDCTstat->DCTSysLimit) { printk(BIOS_DEBUG, "%s: Waiting for memory clear to complete", __func__); do { dword = Get_NB32(dev, 0x110); @@ -4223,7 +4223,7 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p dword &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword); - /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x88, 0xff000000); @@ -4369,16 +4369,16 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 2; i++) + for (i = 0; i < 2; i++) Etr[i] = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0; Tfaw = 0; - for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */ + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB = Dividend/Divisor */ MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); MTB16x /= val; /* transfer to MTB*16 */ @@ -4574,7 +4574,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, pDCTstat->Twtr = val; /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i]; /* Tfaw */ @@ -4647,7 +4647,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */ /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) if (pDCTstat->Trfc[i] == 0x0) pDCTstat->Trfc[i] = 0x1; dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ @@ -4714,7 +4714,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16; val = 0; - for (i=4;i>0;i--) { + for (i = 4; i > 0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -4850,7 +4850,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, proposedFreq = 800; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); if (word < proposedFreq) proposedFreq = word; @@ -4984,7 +4984,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, determine the desired CAS Latency. If tCKproposed is not a standard JEDEC value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the next lower standard tCK value for calculating CLdesired. - CLdesired = ceiling ( tAAmin(all) / tCKproposed ) + CLdesired = ceiling (tAAmin(all) / tCKproposed) where tAAmin is defined in Byte 16. The ceiling function requires that the quotient be rounded up always. */ CLdesired = tAAmin16x / tCKproposed16x; @@ -5163,7 +5163,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) - if ( mctGet_NVbits(NV_ECC)) + if (mctGet_NVbits(NV_ECC)) DramConfigLo |= 1 << DimmEcEn; DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); @@ -5210,7 +5210,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ } - if (0) /* call back not needed mctOverrideDcqBypMax_D ) */ + if (0) /* call back not needed mctOverrideDcqBypMax_D) */ val = mctGet_NVbits(NV_BYPMAX); else val = 0x0f; /* recommended setting (default) */ @@ -5224,7 +5224,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, 1. We will assume that MemClkDis field has been preset prior to this point. 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks ==0 */ + NV_AllMemClks <>0 AND SB_DiagClks == 0 */ /* Dram Timing Low (owns Clock Enable bits) */ DramTimingLo = Get_NB32_DCT(dev, dct, 0x88); @@ -5253,7 +5253,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dword = 0; byte = 0xFF; while (dword < MAX_CS_SUPPORTED) { - if (pDCTstat->CSPresent & (1<<dword)){ + if (pDCTstat->CSPresent & (1<<dword)) { /* re-enable clocks for the enabled CS */ val = p[dword]; byte &= ~val; @@ -5330,11 +5330,11 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValid & (1<<byte)) { byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; - Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */ - Cols = byte & 0x7; /* Cols:0b=9-bit,... */ + Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */ + Cols = byte & 0x7; /* Cols:0b = 9-bit,... */ byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; - Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */ + Banks = (byte >> 4) & 7; /* Banks:0b = 3-bit,... */ byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; Ranks = ((byte >> 3) & 7) + 1; @@ -5351,7 +5351,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, byte |= Rows << 3; /* RRRBCC internal encode */ - for (dword=0; dword < 13; dword++) { + for (dword = 0; dword < 13; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -5367,7 +5367,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0; - byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ byte += 21; /* row:12+col:9 */ byte -= 2; /* 3 banks - 5 */ @@ -5435,7 +5435,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; @@ -5498,7 +5498,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, _DSpareEn = 0; - /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -5513,7 +5513,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -5527,13 +5527,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2); /* Base[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + (q << 1); /*Mask[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); val >>= 19; @@ -5549,7 +5549,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2); if (_DSpareEn) { @@ -5579,7 +5579,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /* bank present but disabled?*/ - if ( pDCTstat->CSTestFail & (1 << p)) { + if (pDCTstat->CSTestFail & (1 << p)) { /* DRAM CS Base b Address Register offset */ reg = (p << 2) + 0x40; val = 1 << TestFail; @@ -5611,12 +5611,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */ u16 i, j, k; u8 smbaddr; @@ -5747,7 +5747,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, byte &= 7; if (byte == 3) { /* 4ranks */ /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if ( pDCTstat->DimmQRPresent == 0) { + if (pDCTstat->DimmQRPresent == 0) { MaxDimms <<= 1; } if (i < DimmSlots) { @@ -5767,7 +5767,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, else if (devwidth == 2) bytex = 4; - byte++; /* al+1=rank# */ + byte++; /* al+1 = rank# */ if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ @@ -5847,7 +5847,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } } if (pDCTstat->DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) { + if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { /* all DIMMs are ECC capable */ pDCTstat->Status |= 1<<SB_ECCDIMMs; } @@ -5961,7 +5961,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, val &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x88, 0xff000000); @@ -6119,7 +6119,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98; Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */ Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */ @@ -6152,7 +6152,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!pDCTstat->GangedMode) { - if (dct == 0 ) { + if (dct == 0) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; if (pDCTstat->DIMMValidDCT[dct] == 0) pDCTstat->ErrCode = SC_StopError; @@ -6172,7 +6172,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, u8 ret; u32 val; - if ( dct == 0) { + if (dct == 0) { SPDCalcWidth_D(pMCTstat, pDCTstat); ret = mct_setMode(pMCTstat, pDCTstat); } else { @@ -6313,7 +6313,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; Set_OtherTiming(pMCTstat, pDCTstat, 0); } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) { + if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; Set_OtherTiming(pMCTstat, pDCTstat, 1); } @@ -6568,8 +6568,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x00E000E0; byte = (val >> 5) & 0xFF; @@ -6607,11 +6607,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -6774,7 +6774,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); - /* set F3x8C[DisFastTprWr] on all DR, if L3Size=0 */ + /* set F3x8C[DisFastTprWr] on all DR, if L3Size = 0 */ if (pDCTstat->LogicalCPUID & AMD_DR_ALL) { if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) { val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C); @@ -6948,7 +6948,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, /* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map; @@ -6975,7 +6975,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, val |= Dramlimit; Set_NB32(devx, reg, val); - if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) { + if (pMCTstat->GStatus & (1 << GSB_HWHole)) { reg = 0xF0; val = Get_NB32(devx, reg); val |= (1 << DramMemHoistValid); @@ -7328,7 +7328,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, } else { dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -7668,7 +7668,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, dword = 0x00000800; else dword = 0x00000000; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { Set_NB32_DCT(dev, i, 0x98, 0x0D000030); Set_NB32_DCT(dev, i, 0x9C, dword); Set_NB32_DCT(dev, i, 0x98, 0x4D040F30); @@ -7958,11 +7958,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= mct_DramTermDyn_RDimm(pMCTstat, pDCTstat, byte); } - /* Qoff=0, output buffers enabled */ + /* Qoff = 0, output buffers enabled */ /* Tcwl */ DramMRS |= (pDCTstat->Speed - 4) << 20; - /* ASR=1, auto self refresh */ - /* SRT=0 */ + /* ASR = 1, auto self refresh */ + /* SRT = 0 */ DramMRS |= 1 << 18; } @@ -7989,10 +7989,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) + * - a) Disable Compensation (F2[1, 0]9C_x08[30]) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30] ) + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 @@ -8275,9 +8275,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { /* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding @@ -8311,7 +8311,7 @@ uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) for (Index = 0; Index < byte_use; Index ++) { byte = pDCTstat->spd_data.spd_bytes[dimm][Index]; CRC ^= byte << 8; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (CRC & 0x8000) { CRC <<= 1; CRC ^= 0x1021; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e1d9da5..c42e452 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -33,16 +33,16 @@ #define PT_C3 5 #define PT_FM2 6 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -336,7 +336,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -353,7 +353,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -363,15 +363,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -379,17 +379,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -399,16 +399,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -418,27 +418,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -462,9 +462,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -545,15 +545,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */ - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */ - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -852,7 +852,7 @@ struct amd_s3_persistent_data { #define SB_SWNodeHole 8 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 9 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 10 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 12 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 13 /* Indicator the default setting for extend PCI configuration support*/ @@ -862,73 +862,73 @@ struct amd_s3_persistent_data { ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -936,8 +936,8 @@ struct amd_s3_persistent_data { #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -949,13 +949,13 @@ struct amd_s3_persistent_data { #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index a7fac8f..74fadde 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -37,7 +37,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi) __asm__ volatile ( "rdtsc" : "=a" (*lo), "=d"(*hi) - ); + ); } static inline void _cpu_id(u32 addr, u32 *val) @@ -57,7 +57,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for (i=31; i>0; i--) { + for (i = 31; i > 0; i--) { if (x & (1<<i)) { ret = i; break; @@ -73,7 +73,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -83,9 +83,9 @@ static u32 bsf(u32 x) return ret; } -#define _MFENCE asm volatile ( "mfence") +#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ( "sfence" ) +#define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") @@ -301,7 +301,7 @@ static u32 stream_to_int(u8 *p) val = 0; - for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c index 3f01308..d6480ab 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c @@ -50,7 +50,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, * : ODC_CTL - Output Driver Compensation Control Register Value * : CMDmode - CMD mode */ -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c index 6c25f2c..30cf10e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c @@ -33,8 +33,8 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, /* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ - /* Manually set: typ=5, otherwise typ=7. */ - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + /* Manually set: typ = 5, otherwise typ = 7. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ if (DctSelIntLvAddr & 1) { DctSelIntLvAddr >>= 1; @@ -67,7 +67,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, if (dct1_size == dct0_size) { dct1_size = 0; DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size ) { + } else if (dct1_size > dct0_size) { dct1_size = dct0_size; DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 3f56765..e42a127 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -45,7 +45,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); - if ( val & (1<<CSEnable)) { + if (val & (1<<CSEnable)) { EnChipSels++; reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */ val = Get_NB32_DCT(dev, dct, reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 06a70e6..64c53c6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -247,12 +247,12 @@ static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, u8 channel; u8 direction; - for (channel = 0; channel < 2; channel++){ + for (channel = 0; channel < 2; channel++) { for (direction = 0; direction < 2; direction++) { pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -294,7 +294,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); DQSDelay1 = pDCTstat->DQSDelay; - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; } else { DQSDelay = DQSDelay1 - DQSDelay0; @@ -306,7 +306,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, DQSDelay >>= 8; /* 256 */ - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay1 - DQSDelay; } else { DQSDelay += DQSDelay1; @@ -493,7 +493,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, } print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2); @@ -556,7 +556,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D(); /* Read and compare pattern */ - bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ /* If all lanes have already failed testing bypass remaining re-read attempt(s) */ if (bytelane_test_results == 0x0) @@ -650,7 +650,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D(); /* Read and compare pattern from the base test address */ - bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ /* Store any lanes that passed testing for later use */ for (lane = 0; lane < 8; lane++) @@ -661,7 +661,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, if ((!dual_rank) || (dual_rank && (Receiver & 0x1))) { #ifdef PRINT_PASS_FAIL_BITMAPS - for (iter = 0; iter < 64; iter++) { + for (iter = 0; iter < 64; iter++) { if (dqs_read_results_array[0][lane][iter]) printk(BIOS_DEBUG, "+"); else @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -834,7 +834,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1583,7 +1583,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1843,7 +1843,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1863,7 +1863,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1890,11 +1890,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1<<SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -1966,10 +1966,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, else dct = 0; - if (ChipSel < MAX_CS_SUPPORTED){ + if (ChipSel < MAX_CS_SUPPORTED) { reg = 0x40 + (ChipSel << 2); val = Get_NB32_DCT(dev, dct, reg); - if (val & ( 1 << 0)) + if (val & (1 << 0)) ret = 1; } @@ -2058,7 +2058,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat } bytelane = 0; /* bytelane counter */ - bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */ + bitmap = 0xFFFF; /* bytelane test bitmap, 1 = pass */ MEn1Results = 0xFFFF; BeatCnt = 0; for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ @@ -2102,7 +2102,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat if (!bitmap) break; - if (bytelane == 0){ + if (bytelane == 0) { BeatCnt += 4; if (!(pDCTstat->Status & (1 << SB_128bitmode))) { if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */ @@ -2132,7 +2132,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo) { /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0){ + if (pDCTstat->Pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { FlushDQSTestPattern_L18(addr_lo); @@ -2349,9 +2349,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val &= ~0xe007c01f; - /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { + if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; dword = Get_NB32(dev, reg); dword &= 0xfffff800; @@ -2365,7 +2365,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase; /* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 5d31849..16cebed 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -36,7 +36,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -152,10 +152,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if (pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); @@ -210,7 +210,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -325,8 +325,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if ((val & 3)==3) { /* Node has dram populated*/ - if ( isDramECCEn_D(pDCTstat)) { + if ((val & 3) == 3) { /* Node has dram populated*/ + if (isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -353,8 +353,8 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0){ + for (i = 0; i < ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0) { reg = 0x90; /* Dram Config Low */ val = Get_NB32_DCT(dev, i, reg); if (val & (1<<DimmEcEn)) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 8ed2bef..558b3e3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -34,11 +34,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */ @@ -82,8 +82,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ printk(BIOS_DEBUG, "\t CPUMemTyping: Cache32bTOP:%x\n", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -112,10 +112,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -146,7 +146,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -172,17 +172,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8; /* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; - val |= ( 1 << 11); /* set MTRR valid*/ + val |= (1 << 11); /* set MTRR valid*/ addr++; _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ val = curLimit; @@ -213,9 +213,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; @@ -234,7 +234,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while ( addr < 0x20C) { + while (addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index 9a769ad..bf84171 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -68,7 +68,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, NodesWmem++; Base &= 0xFFFF0000; /* Base[39:8] */ - if (pDCTstat->Status & (1 << SB_HWHole )) { + if (pDCTstat->Status & (1 << SB_HWHole)) { /* to get true amount of dram, * subtract out memory hole if HW dram remapping */ @@ -83,7 +83,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); if (DctSelBase) { DctSelBase <<= 8; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { DctSelBase -= HWHoleSz; } @@ -100,7 +100,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, MemSize &= 0xFFFF0000; MemSize += 0x00010000; MemSize -= Base; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { MemSize -= HWHoleSz; } if (Node == 0) { @@ -139,7 +139,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat, pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; @@ -180,7 +180,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if ( Node == 0) { + if (Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 951a712..ac24c6d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -336,14 +336,14 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val); if (is_fam15h()) { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); if ((cw == 2) || (cw == 8) || (cw == 10)) precise_ndelay_fam15(pMCTstat, 6000); } } else { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { mct_Wait(1600); val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 670d640..18af172 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -912,7 +912,7 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat, /* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */ if (Get_NB32_DCT(dev, dct, 0x94) & (1 << RDqsEn)) { u8 bit; - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ bit = (ret >> 21) << 1; if ((dct & 1) != 0) bit ++; @@ -1063,7 +1063,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) printk(BIOS_DEBUG, "%s: Start\n", __func__); /*1.Program MrsAddress[10]=1 - 2.Set SendZQCmd=1 + 2.Set SendZQCmd = 1 */ dword = Get_NB32_DCT(dev, dct, 0x7C); dword &= ~0xFFFFFF; @@ -1071,7 +1071,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) dword |= 1 << SendZQCmd; Set_NB32_DCT(dev, dct, 0x7C, dword); - /* Wait for SendZQCmd=0 */ + /* Wait for SendZQCmd = 0 */ do { dword = Get_NB32_DCT(dev, dct, 0x7C); } while (dword & (1 << SendZQCmd)); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 8024179..345e630 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -76,7 +76,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -560,7 +560,7 @@ static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDC SetUpperFSbase(testaddr); testaddr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { testaddr += 8; /* second channel */ } @@ -636,7 +636,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -986,7 +986,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ wrmsr(HWCR, msr); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -996,7 +996,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1013,10 +1013,10 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1246,7 +1246,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1500,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1510,7 +1510,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1527,10 +1527,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1604,7 +1604,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, ch_end = 2; cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1720,7 +1720,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1730,7 +1730,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1745,7 +1745,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { - if (pDCTstat->DIMMValidDCT[dct] == 0 ) { + if (pDCTstat->DIMMValidDCT[dct] == 0) { return 8; } else { return 0; @@ -1766,7 +1766,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; } - for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78; val = Get_NB32_DCT(dev, ch, reg); val &= ~(1 << DqsRcvEnTrain); @@ -1800,14 +1800,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, } /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } - /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -1852,7 +1852,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); if ((package_type == PT_L1) /* Socket F (1207) */ || (package_type == PT_M2) /* Socket AM3 */ - || (package_type == PT_S1)) { /* Socket S1g<x> */ + || (package_type == PT_S1)) { /* Socket S1g < x> */ cpu_val_n = 10; cpu_val_p = 11; } else { @@ -1950,7 +1950,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++) { InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1972,8 +1972,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* FIXME: add Cx support */ dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); @@ -1981,14 +1981,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword); } @@ -2087,7 +2087,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -2427,5 +2427,5 @@ void mct_Wait(u32 cycles) saved = lo; do { _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles ); + } while (lo - saved < cycles); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index d535735..30cf19b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -49,7 +49,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 2f4d4da..7f67824 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -58,7 +58,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 bn; bn = 8; - for ( i=0;i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; if (val > max) { @@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ /* val += Pass1MemClkDly; */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 15eb67e..b35e79e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -144,7 +144,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); @@ -159,7 +159,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -180,7 +180,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } @@ -207,7 +207,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; @@ -239,7 +239,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8; _EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i]; @@ -284,11 +284,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp>Max) { + if (tmp > Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -371,7 +371,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, valx = (val) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4 ) * 3; + val = ((val & 0x1f) + 4) * 3; /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ valxx = val << 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 44ea6e8..47c5004 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -426,7 +426,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, } } - /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns */ + /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */ mct_Wait(250); if (pDCTstat->Status & (1 << SB_Registered)) { @@ -474,9 +474,9 @@ void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct=0, set */ + Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct=1, set */ + Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */ } } void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, @@ -484,8 +484,8 @@ void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct=0, clear */ + Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct=1, clear */ + Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */ } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 5c30bc5..cb69f60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -140,15 +140,15 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D00000C; + Addr = 0x0D00000C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -157,7 +157,7 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT Value = bitTestReset(Value, 4); /* for x8 only */ Value = bitTestReset(Value, 5); /* for hardware WL training */ AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D030F0C; + Addr = 0x4D030F0C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -453,22 +453,22 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank_count == 1) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank == 0) - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ else - term = 0x00; /* Rtt_Nom=OFF */ + term = 0x00; /* Rtt_Nom = OFF */ } } } else { if (frequency_index < 5) - term = 0x0044; /* Rtt_Nom=RZQ/6=40 Ohm */ + term = 0x0044; /* Rtt_Nom = RZQ/6 = 40 Ohm */ else - term = 0x0204; /* Rtt_Nom=RZQ/8=30 Ohm */ + term = 0x0204; /* Rtt_Nom = RZQ/8 = 30 Ohm */ } return term; @@ -482,15 +482,15 @@ static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ } else { if (rank_count == 1) - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ else - term = 0x200; /* Rtt_WR=RZQ/4=60 Ohm */ + term = 0x200; /* Rtt_WR = RZQ/4 = 60 Ohm */ } } else { - term = 0x400; /* Rtt_WR=RZQ/2=120 Ohm */ + term = 0x400; /* Rtt_WR = RZQ/2 = 120 Ohm */ } return term; @@ -558,7 +558,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -618,7 +618,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; /* All ranks of the target DIMM are set to write levelization mode. */ if (wl) @@ -702,8 +702,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -720,7 +720,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -779,14 +779,14 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required * DDR3-defined function for write levelization. */ - tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */ + tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level = 0, Qoff = 0 */ /* Retrieve normal settings of the MRS control word and clear Rtt_Nom */ if (is_fam15h()) { tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -811,7 +811,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; /* Program MrsAddress[5,1]=output driver impedance control (DIC) */ if (is_fam15h()) { @@ -877,8 +877,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -895,7 +895,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -939,7 +939,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u8 WrLvOdt1=0; + u8 WrLvOdt1 = 0; if (is_fam15h()) { /* On Family15h processors, the value for the specific CS being targetted @@ -954,7 +954,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui cs = (dimm * 2) + rank; /* Fetch preprogammed ODT pattern from configuration registers */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs>3)?0x23c:0x238)); + dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs > 3)?0x23c:0x238)); if ((cs == 7) || (cs == 3)) WrLvOdt1 = ((dword >> 24) & 0xf); else if ((cs == 6) || (cs == 2)) @@ -1045,25 +1045,25 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui } else { - /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ + /* Program WrLvOdtEn = 1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D008000; + Addr = 0x0D008000; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); Value = bitTestSet(Value, 12); AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D088F00; + Addr = 0x4D088F00; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -1371,7 +1371,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 while (ByteLane < lane_count) { /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + if ((pDCTData->WLPass == 2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; tempW -= 0xC; pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 6589a39..97cadcb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -351,12 +351,12 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x11c = pci_read_config32(dev_fn2, 0x11c); data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0); data->f3x44 = pci_read_config32(dev_fn3, 0x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i); } data->msr00000250 = rdmsr_uint64_t(0x00000250); data->msr00000258 = rdmsr_uint64_t(0x00000258); - for (i=0; i<8; i++) + for (i = 0; i < 8; i++) data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8)); data->msr000002ff = rdmsr_uint64_t(0x000002ff); data->msrc0010010 = rdmsr_uint64_t(0xc0010010); @@ -393,7 +393,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x204 = read_config32_dct(dev_fn2, node, channel, 0x204); data->f2x208 = read_config32_dct(dev_fn2, node, channel, 0x208); data->f2x20c = read_config32_dct(dev_fn2, node, channel, 0x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x210[i] = read_config32_dct_nbpstate(dev_fn2, node, channel, i, 0x210); data->f2x214 = read_config32_dct(dev_fn2, node, channel, 0x214); data->f2x218 = read_config32_dct(dev_fn2, node, channel, 0x218); @@ -407,7 +407,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fe003 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe003); data->f2x9cx0d0fe013 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_1f[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f001f | (i << 8)); data->f2x9cx0d0f201f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f201f); data->f2x9cx0d0f211f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f211f); @@ -419,11 +419,11 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc11f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc11f); data->f2x9cx0d0fc21f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc21f); data->f2x9cx0d0f4009 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f4009); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_02[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0002 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_06[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0006 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_0a[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f000a | (i << 8)); data->f2x9cx0d0f2002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2002); @@ -450,7 +450,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc031); data->f2x9cx0d0fc131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc131); data->f2x9cx0d0fc231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); @@ -463,8 +463,8 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x94 = read_config32_dct(dev_fn2, node, channel, 0x94); /* Stage 6 */ - for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx00 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x00); data->f2x9cx0a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0a); @@ -478,33 +478,33 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fe007 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe007); /* Stage 10 */ - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx10[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x10 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx20[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x20 + i); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_3_1[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x01 + i) + (0x100 * j)); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_7_5[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x05 + i) + (0x100 * j)); data->f2x9cx0d = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_13[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0013 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0030 | (i << 8)); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x9cx0d0f2_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2030 | (i << 8)); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f8_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx40[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x40 + i); } @@ -599,28 +599,28 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste continue; /* Restore training parameters */ - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); } /* Restore MaxRdLatency */ if (is_fam15h()) { - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); } else { write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); @@ -682,7 +682,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]); } wrmsr_uint64_t(0x00000250, data->msr00000250); @@ -692,7 +692,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste * destroying CAR while still executing from CAR! * For now, skip restoration... */ - // for (i=0; i<8; i++) + // for (i = 0; i < 8; i++) // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); wrmsr_uint64_t(0x000002ff, data->msr000002ff); wrmsr_uint64_t(0xc0010010, data->msrc0010010); @@ -760,7 +760,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x204, data->f2x204); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x208, data->f2x208); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x20c, data->f2x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x214, data->f2x214); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x218, data->f2x218); @@ -773,7 +773,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x240, data->f2x240); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, data->f2x9cx0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f001f | (i << 8), data->f2x9cx0d0f0_8_0_1f[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f201f, data->f2x9cx0d0f201f); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f211f, data->f2x9cx0d0f211f); @@ -795,7 +795,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc031, data->f2x9cx0d0fc031); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc131, data->f2x9cx0d0fc131); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc231, data->f2x9cx0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); @@ -899,8 +899,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x00, data->f2x9cx00); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0a, data->f2x9cx0a); @@ -920,11 +920,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste dword |= (0x3 << 13); /* DisAutoComp, DisablePredriverCal = 1 */ write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, dword); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0006 | (i << 8), data->f2x9cx0d0f0_8_0_06[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f000a | (i << 8), data->f2x9cx0d0f0_8_0_0a[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0002 | (i << 8), (0x8000 | data->f2x9cx0d0f0_8_0_02[i])); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8006, data->f2x9cx0d0f8006); @@ -1024,25 +1024,25 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d, data->f2x9cx0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0013 | (i << 8), data->f2x9cx0d0f0_f_0_13[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0030 | (i << 8), data->f2x9cx0d0f0_f_0_30[i]); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2030 | (i << 8), data->f2x9cx0d0f2_f_0_30[i]); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f8_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f812f, data->f2x9cx0d0f812f); } @@ -1056,9 +1056,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); } } diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 92979ab..5eaff2c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -63,7 +63,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 143468a..d121f35 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -347,7 +347,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ uint8_t dimm; for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { @@ -473,7 +473,7 @@ static void mctHookAfterDramInit(void) { } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ static void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -481,7 +481,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32))); // is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + if (((pDCTstat->PresetmaxFreq == 1333)||(nbPstate1supported)) &&(!pDCTstat->GangedMode)) { /* DisableCf8ExtCfg */ msr.hi &= ~(3 << (51 - 32)); @@ -491,15 +491,15 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) static void vErratum414(struct DCTStatStruc *pDCTstat) { - int dct=0; + int dct = 0; for (; dct < 2 ; dct++) { int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); - int powerDown = dRAMConfigHi & (1 << PowerDownEn ); - int ddr3 = dRAMConfigHi & (1 << Ddr3Mode ); + int powerDown = dRAMConfigHi & (1 << PowerDownEn); + int ddr3 = dRAMConfigHi & (1 << Ddr3Mode); int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel); - if (powerDown && ddr3 && pchgPDModeSel ) - Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); + if (powerDown && ddr3 && pchgPDModeSel) + Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel)); } } #endif @@ -507,7 +507,7 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -516,7 +516,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt #endif } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index c10428d..9581527 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -78,7 +78,7 @@ static void rd890_enable(device_t dev) 0, (devfn >> 3), (devfn & 0x07), dev->enabled); /* we only do this once */ - if (devfn==0) { + if (devfn == 0) { /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index f21d717..3b02016 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -35,24 +35,24 @@ struct gliutable }; struct gliutable gliu0table[] = { - {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable gliu1table[] = { - {.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ - {.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ + {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, + {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; @@ -64,51 +64,51 @@ struct msrinit }; struct msrinit ClockGatingDefault[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* All On */ struct msrinit ClockGatingAllOn[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}}, - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* Performance */ struct msrinit ClockGatingPerformance[] = { - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable[] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */ - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */ - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */ - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */ - {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */ + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */ + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */ + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */ + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */ + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */ + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */ + {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */ {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ }; @@ -422,7 +422,7 @@ static uint64_t getShadow(void) msr_t msr = { 0, 0 }; msr = rdmsr(GLIU0_P2D_SC_0); - return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; + return (((uint64_t) msr.hi) << 32) | msr.lo; } /* Set the cache RConf registers for the memory hole. diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 303d64a..0bae76d 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -88,7 +88,7 @@ static void pll_reset(void) wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); /* If the "we've already been here" flag is set, don't reconfigure the pll */ - if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) ) + if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED)) { /* we haven't configured the PLL; do it now */ /* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */ @@ -145,8 +145,8 @@ static void pll_reset(void) /* CheckPCIsync: */ /* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */ /* look up the real divider... if we get a 0 we have serious problems */ - if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % - (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) ) + if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % + (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2))) { SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET; } diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index db10138..6e66d7d 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -97,7 +97,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ printk(BIOS_DEBUG, "BEFORT CTZ\n"); dimm_size = __builtin_ctz(dimm_size); - printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n"); + printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n"); if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */ printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); @@ -130,7 +130,7 @@ static void auto_size_dimm(unsigned int dimm) * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), * so lower 3 address bits are dont_cares. So from the table above, * it's easier to see what the old code is doing: if for example, - * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K. + * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K. */ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; @@ -142,10 +142,10 @@ static void auto_size_dimm(unsigned int dimm) } printk(BIOS_DEBUG, ">11address test\n"); spd_byte -= 7; - if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */ - spd_byte = 7; /* which means >16k so set to disabled */ + if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */ + spd_byte = 7; /* which means > 16k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */ printk(BIOS_DEBUG, "RDMSR CF07\n"); msr = rdmsr(MC_CF07_DATA); @@ -230,7 +230,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */ static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0; /************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 2ba4a04..a40a628 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -91,7 +91,7 @@ struct msr_defaults { /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index c540f9a..395d925 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -106,7 +106,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ banner("BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); - banner("TEST DIMM SIZE>8"); + banner("TEST DIMM SIZE > 8"); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); @@ -131,12 +131,12 @@ static void auto_size_dimm(unsigned int dimm) *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) -*; *AP=autoprecharge bit +*; *AP = autoprecharge bit * *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), *;so lower 3 address bits are dont_cares.So from the table above, -*;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), -*;it adds 3 to get 10, then does 2^10=1K. Get it?*/ +*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h), +*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; banner("MAXCOLADDR"); @@ -147,10 +147,10 @@ static void auto_size_dimm(unsigned int dimm) } banner(">12address test"); spd_byte -= 7; - if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ - spd_byte = 7; /* which means >32k so set to disabled */ + if (spd_byte > 5) { /* if the value is above 6 it means > 12 address lines */ + spd_byte = 7; /* which means > 32k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */ banner("RDMSR CF07"); msr = rdmsr(MC_CF07_DATA); @@ -182,7 +182,7 @@ static void checkDDRMax(void) } /* I don't think you need this check. - if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ + if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) { printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); post_code(POST_PLL_MEM_FAIL); hcf(); @@ -242,7 +242,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0; /************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); @@ -730,8 +730,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* Set PMode0 Sensitivity Counter */ - msr.lo = 0; /* pmode 0=0 most aggressive */ - msr.hi = 0x200; /* pmode 1=200h */ + msr.lo = 0; /* pmode 0 = 0 most aggressive */ + msr.hi = 0x200; /* pmode 1 = 200h */ wrmsr(MC_CF_PMCTR, msr); /* Set PMode1 Up delay enable */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index 689203a..c2b3aac 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR3) { Name(_ADR, 0x00030000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS3) } /* APIC mode */ + If(PMOD) { Return(APS3) } /* APIC mode */ Return (PS3) /* PIC Mode */ } /* end _PRT */ } /* end PBR3 */ diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 889db62a..50eee51 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -35,9 +35,9 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA if ((dev == 0) || (config == 0)) return AGESA_ERROR; - if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 0f9e5f5..8a40280 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -88,10 +88,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<node_nums; i++) + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -101,10 +101,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -131,7 +131,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -160,7 +160,7 @@ static u32 amdfam15_nodeid(device_t dev) unsigned busn; busn = dev->bus->secondary; - if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)){ + if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; } else { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -403,8 +403,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate )) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) break; } else @@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -687,7 +687,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -811,11 +811,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -981,7 +981,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1059,10 +1059,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index cde5182..022b347 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -105,7 +105,7 @@ Device(PBRA) { Name(_ADR, 0x00030003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ + If(PMOD) { Return(APSA) } /* APIC mode */ Return (PSA) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -115,7 +115,7 @@ Device(PBRB) { Name(_ADR, 0x00030004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ + If(PMOD) { Return(APSB) } /* APIC mode */ Return (PSB) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -125,7 +125,7 @@ Device(PBRC) { Name(_ADR, 0x00030005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ + If(PMOD) { Return(APSC) } /* APIC mode */ Return (PSC) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index efee0a4..1ca0df9 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -134,7 +134,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -396,9 +396,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) } /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1059,10 +1058,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1081,10 +1080,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index 4e6d13e..f74b31a 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6d5418a..b778da5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -83,9 +83,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -97,7 +97,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -107,10 +107,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -141,7 +141,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -417,9 +417,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -646,7 +645,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -709,7 +708,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -841,11 +840,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1011,7 +1010,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1090,10 +1089,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1112,10 +1111,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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Patch set updated for coreboot: northbridge/amd: Improve code formatting
by HAOUAS Elyes
18 Sep '16
18 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16634
-gerrit commit b8c13d62a7a656bb6be8ba2d3634ac8d2c962869 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 18 08:50:54 2016 +0200 northbridge/amd: Improve code formatting Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/common/common.c | 2 +- src/northbridge/amd/agesa/family10/amdfam10.h | 4 +- src/northbridge/amd/agesa/family10/northbridge.c | 37 ++-- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 14 +- src/northbridge/amd/agesa/family12/northbridge.c | 20 +- .../amd/agesa/family14/acpi/northbridge.asl | 20 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 18 +- src/northbridge/amd/agesa/family15/northbridge.c | 35 ++-- .../amd/agesa/family15rl/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 35 ++-- .../amd/agesa/family15tn/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 35 ++-- .../amd/agesa/family16kb/acpi/northbridge.asl | 10 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 35 ++-- src/northbridge/amd/agesa/oem_s3.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 24 +-- src/northbridge/amd/amdfam10/amdfam10.h | 6 +- src/northbridge/amd/amdfam10/amdfam10_util.asl | 18 +- src/northbridge/amd/amdfam10/debug.c | 12 +- src/northbridge/amd/amdfam10/early_ht.c | 4 +- src/northbridge/amd/amdfam10/get_pci1234.c | 8 +- src/northbridge/amd/amdfam10/ht_config.c | 24 +-- src/northbridge/amd/amdfam10/northbridge.c | 29 ++- src/northbridge/amd/amdfam10/raminit.h | 4 +- src/northbridge/amd/amdfam10/raminit_amdmct.c | 8 +- .../amd/amdfam10/raminit_sysinfo_in_ram.c | 4 +- src/northbridge/amd/amdfam10/reset_test.c | 4 +- src/northbridge/amd/amdfam10/setup_resource_map.c | 4 +- src/northbridge/amd/amdht/AsPsNb.c | 12 +- src/northbridge/amd/amdht/comlib.c | 4 +- src/northbridge/amd/amdht/h3finit.c | 22 +-- src/northbridge/amd/amdht/h3finit.h | 4 +- src/northbridge/amd/amdht/h3ncmn.c | 46 ++--- src/northbridge/amd/amdk8/acpi.c | 26 +-- src/northbridge/amd/amdk8/coherent_ht.c | 124 ++++++------ src/northbridge/amd/amdk8/debug.c | 10 +- src/northbridge/amd/amdk8/early_ht.c | 4 +- src/northbridge/amd/amdk8/exit_from_self.c | 2 +- src/northbridge/amd/amdk8/f.h | 6 +- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 12 +- src/northbridge/amd/amdk8/incoherent_ht.c | 98 ++++----- src/northbridge/amd/amdk8/misc_control.c | 12 +- src/northbridge/amd/amdk8/northbridge.c | 32 +-- src/northbridge/amd/amdk8/raminit.c | 42 ++-- src/northbridge/amd/amdk8/raminit_f.c | 198 +++++++++---------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 110 +++++------ src/northbridge/amd/amdk8/raminit_test.c | 4 +- src/northbridge/amd/amdk8/setup_resource_map.c | 8 +- src/northbridge/amd/amdk8/util.asl | 14 +- src/northbridge/amd/amdmct/amddefs.h | 4 +- src/northbridge/amd/amdmct/mct/mct.h | 202 +++++++++---------- src/northbridge/amd/amdmct/mct/mct_d.c | 156 +++++++-------- src/northbridge/amd/amdmct/mct/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 12 +- src/northbridge/amd/amdmct/mct/mctardk3.c | 2 +- src/northbridge/amd/amdmct/mct/mctardk4.c | 2 +- src/northbridge/amd/amdmct/mct/mctchi_d.c | 4 +- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 52 ++--- src/northbridge/amd/amdmct/mct/mctecc_d.c | 16 +- src/northbridge/amd/amdmct/mct/mctgr.c | 6 +- src/northbridge/amd/amdmct/mct/mctmtr_d.c | 28 +-- src/northbridge/amd/amdmct/mct/mctndi_d.c | 10 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 20 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 52 ++--- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct/mcttmrl.c | 20 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 128 ++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 220 ++++++++++----------- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 12 +- src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 46 ++--- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 16 +- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 28 +-- src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 56 +++--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 20 +- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 10 +- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 74 +++---- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 110 +++++------ src/northbridge/amd/amdmct/wrappers/mcti.h | 2 +- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 20 +- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx2/northbridgeinit.c | 90 ++++----- src/northbridge/amd/gx2/pll_reset.c | 6 +- src/northbridge/amd/gx2/raminit.c | 12 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 22 +-- .../amd/pi/00630F01/acpi/northbridge.asl | 4 +- src/northbridge/amd/pi/00630F01/dimmSpd.c | 4 +- src/northbridge/amd/pi/00630F01/northbridge.c | 36 ++-- .../amd/pi/00660F01/acpi/northbridge.asl | 16 +- src/northbridge/amd/pi/00660F01/northbridge.c | 23 ++- .../amd/pi/00730F01/acpi/northbridge.asl | 10 +- src/northbridge/amd/pi/00730F01/northbridge.c | 35 ++-- 102 files changed, 1538 insertions(+), 1546 deletions(-) diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c index ab8f687..8dd2ac0 100644 --- a/src/northbridge/amd/agesa/common/common.c +++ b/src/northbridge/amd/agesa/common/common.c @@ -54,7 +54,7 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) memcpy((char*)info->Buffer, spd_file, spd_file_length); u16 crc = spd_ddr3_calc_crc(info->Buffer, spd_file_length); - if (crc == 0){ + if (crc == 0) { printk(BIOS_EMERG, "Error: Unable to calculate CRC on SPD\n"); return AGESA_UNSUPPORTED; } diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h index b1dab41..27f78a3 100644 --- a/src/northbridge/amd/agesa/family10/amdfam10.h +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -87,8 +87,8 @@ #endif #ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 53ddc0e..dd94094 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -100,7 +100,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if ((sysconf.conf_io_addrx[index+4] == 0)) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -116,7 +116,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -167,10 +167,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -182,7 +182,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -193,10 +193,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -218,7 +218,7 @@ static unsigned int read_nb_cfg_54(void) { msr_t msr; msr = rdmsr(NB_CFG_MSR); - return (( msr.hi >> (54-32)) & 1); + return ((msr.hi >> (54-32)) & 1); } static void get_fx_devs(void) @@ -505,9 +505,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -609,7 +608,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -685,7 +684,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -775,11 +774,11 @@ static void amdfam10_domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -877,7 +876,7 @@ static void sysconf_init(device_t dev) // first node unsigned ht_c_index; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; } @@ -1004,7 +1003,7 @@ static void cpu_bus_scan(device_t dev) nodes = sysconf.nodes; #if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1027,7 +1026,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next); @@ -1072,7 +1071,7 @@ static void cpu_bus_scan(device_t dev) jj = cores_found; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 7afa39d..3c91d2d 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev; /* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -124,7 +124,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1526972..f0901b4 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,7 +41,7 @@ static device_t __f0_dev[FX_DEVS]; static device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; static device_t get_node_pci(u32 nodeid, u32 fn) { @@ -136,9 +136,9 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, result = 2; if (res) { result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { result = 1; } } @@ -397,10 +397,10 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate )) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif - break; // XXX this break looks questionable + break; // XXX this break looks questionable } } @@ -485,7 +485,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -604,11 +604,11 @@ static void domain_set_resources(device_t dev) mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index a1b4acb..e95c95a 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -30,7 +30,7 @@ Device(AGPB) { Name(_ADR, 0x00010000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APR1) } /* APIC mode */ + If(PMOD) { Return(APR1) } /* APIC mode */ Return (PR1) /* PIC Mode */ } } /* end AGPB */ @@ -40,7 +40,7 @@ Device(HDMI) { Name(_ADR, 0x00010001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APR1) } /* APIC mode */ + If(PMOD) { Return(APR1) } /* APIC mode */ Return (PR1) /* PIC Mode */ } } /* end HDMI */ @@ -52,7 +52,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -62,7 +62,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -72,7 +72,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -82,7 +82,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -91,7 +91,7 @@ Device(PE20) { Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ + If(PMOD) { Return(APE0) } /* APIC mode */ Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ @@ -100,7 +100,7 @@ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ + If(PMOD) { Return(APE1) } /* APIC mode */ Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ @@ -109,7 +109,7 @@ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ + If(PMOD) { Return(APE2) } /* APIC mode */ Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ @@ -118,7 +118,7 @@ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ + If(PMOD) { Return(APE3) } /* APIC mode */ Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 6db2b95..28c16fb 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++){ + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } @@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, device_t dev; /* io range allocation */ - for (i=0; i<nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); @@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) #if 0 u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -124,7 +124,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -158,7 +158,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi ********************************************************************/ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev; switch(vendev) { case 0x10029809: @@ -168,7 +168,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x10029805: case 0x10029804: case 0x10029803: - new_vendev=0x10029802; + new_vendev = 0x10029802; break; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 0c14bdd..ef6692a 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -80,9 +80,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -138,7 +138,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -410,9 +410,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -636,7 +635,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -703,7 +702,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -824,11 +823,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -984,7 +983,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1062,10 +1061,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1087,14 +1086,14 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } #if CONFIG_CPU_AMD_SOCKET_G34 u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); #else u32 apic_id = (i * core_max) + j + lapicid_start; #endif - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl index 46f8940..9a1fa9e 100644 --- a/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -70,7 +70,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -80,7 +80,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -90,7 +90,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d1560b7..3ff7ca0 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -80,9 +80,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -94,7 +94,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -104,10 +104,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -138,7 +138,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -410,9 +410,8 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -630,7 +629,7 @@ static void domain_read_resources(struct device *dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -697,7 +696,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -818,11 +817,11 @@ static void domain_set_resources(struct device *dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -972,7 +971,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1050,10 +1049,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; @@ -1077,10 +1076,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 46f8940..9a1fa9e 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -70,7 +70,7 @@ Device(PBR5) { Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -80,7 +80,7 @@ Device(PBR6) { Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -90,7 +90,7 @@ Device(PBR7) { Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7b57cc3..f07783d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -79,9 +79,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -137,7 +137,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -409,9 +409,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -629,7 +628,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -696,7 +695,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -971,7 +970,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1049,10 +1048,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; @@ -1076,10 +1075,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index 4e6d13e..f74b31a 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28302ef..eac4c60 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -79,9 +79,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -137,7 +137,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -409,9 +409,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -644,7 +643,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -711,7 +710,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -834,11 +833,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -988,7 +987,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1066,10 +1065,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; @@ -1093,10 +1092,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 4f2788e..fcf8ada 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -23,7 +23,7 @@ #include <AGESA.h> typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type S3DataTypeMTRR ///< MTRR storage } S3_DATA_TYPE; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 51da7d6..e67a127 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -96,7 +96,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return; - if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current) *p = (u8) nodes; p += 8; - for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) p[i*nodes+j] = 10; else p[i*nodes+j] = 16; @@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_name("BUSN"); acpigen_write_package(HC_NUMS); - for (i=0; i<HC_NUMS; i++) { + for (i = 0; i < HC_NUMS; i++) { acpigen_write_dword(sysconf.ht_c_conf_bus[i]); } // minus the opcode @@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_NUMS * 4); - for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain + for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask } @@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_NUMS * 2); - for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain + for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain acpigen_write_dword(sysconf.conf_io_addrx[i]); acpigen_write_dword(sysconf.conf_io_addr[i]); } @@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x00000000); } // minus the opcode @@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } // minus the opcode @@ -311,7 +311,7 @@ void northbridge_acpi_write_vars(device_t device) acpigen_write_name_byte("CBST", CBST); - if ((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { + if ((CONFIG_CBB == 0xff) && (sysconf.nodes > 32)) { CBS2 = 0x0f; CBB2 = (u8)(CONFIG_CBB-1); } else { diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 4c3aec6..2ef22ee 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -967,8 +967,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "nums.h" #ifdef __PRE_RAM__ -#if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif @@ -977,7 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" #include "../amdmct/wrappers/mcti.h" -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" #else #include "../amdmct/mct/mct_d.h" diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl index bf0d177..6e2118d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl @@ -56,9 +56,9 @@ Scope (\_SB) Method (DADD, 2, NotSerialized) { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) + Store(Arg1, Local0) + Store(Arg0, Local1) + Add(ShiftLeft(Local1,16), Local0, Local0) Return (Local0) } @@ -66,7 +66,7 @@ Scope (\_SB) Method (GHCE, 1, NotSerialized) // check if the HC enabled { Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } Else { Return (0x00) } } @@ -74,7 +74,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0) + Store (ShiftRight(And (Local1, 0xfc), 0x02), Local0) Return (Local0) } @@ -82,7 +82,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0x700), 0x08), Local0) + Store (ShiftRight(And (Local1, 0x700), 0x08), Local0) Return (Local0) } @@ -92,7 +92,7 @@ Scope (\_SB) Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Store (And (ShiftRight(Local1, Local2), 0xff), Local0) Return (Local0) } @@ -176,7 +176,7 @@ Scope (\_SB) Store (0x00, Local0) Store (0x00, Local4) Store (0x00, Local3) - While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit ) + While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem) *2 (base, limit) { Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) Increment (Local0) @@ -237,7 +237,7 @@ Scope (\_SB) Store (0x00, Local0) Store (0x00, Local4) Store (0x00, Local3) - While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit) + While (LLess (Local0, 0x40)) // 0x20 ht links * 2 (base, limit) { Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) Increment (Local0) diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index e01c44d..327a0e6 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -95,7 +95,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) printk(BIOS_DEBUG, "\n%04x:",i); } val = pci_read_config32(dev, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -121,7 +121,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -262,7 +262,7 @@ static void dump_smbus_registers(void) printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( smbus_read_byte(device, 0) < 0 ) continue; + if (smbus_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; @@ -287,7 +287,7 @@ static inline void dump_io_resources(u32 port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { u8 val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -305,8 +305,8 @@ static inline void dump_mem(u32 start, u32 end) { u32 i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { - if ((i & 0xf)==0) { + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index a1b411f..812935e 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -96,7 +96,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { + if (next_unitid >= 0x18) { if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -158,7 +158,7 @@ static void enumerate_ht_chain(void) out: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { + if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { u16 flags; flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index a6f679e..11f1589 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -73,7 +73,7 @@ void get_pci1234(void) //2. so at the same time we need update hsdn with hcdn_reg here // printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num); - for (j=0;j<sysconf.ht_c_num;j++) { + for (j = 0; j < sysconf.ht_c_num; j++) { u32 dwordx; dwordx = sysconf.ht_c_conf_bus[j]; // printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]); @@ -86,7 +86,7 @@ void get_pci1234(void) if ((dwordx & 1)) { // We need to find out the number of HC // for exact match - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -94,7 +94,7 @@ void get_pci1234(void) } } // for 0xffc match or same node - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -104,7 +104,7 @@ void get_pci1234(void) } } - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 1)) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 9603223..226d9a8 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -56,7 +56,7 @@ void set_config_map_reg(struct bus *link) tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } @@ -67,7 +67,7 @@ void clear_config_map_reg(struct bus *link) u32 i; u32 ht_c_index = get_ht_c_index(link); - for (i=0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } @@ -86,13 +86,13 @@ static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) { u32 ht_c_index = 0; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { return ht_c_index; } @@ -127,7 +127,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<256; index++) { + for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); @@ -142,7 +142,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn) { u32 index; - for (index=0; index<64; index++) { + for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); @@ -185,7 +185,7 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - if ( sysconf.mmio_addr_num<(index+1)) + if (sysconf.mmio_addr_num<(index+1)) sysconf.mmio_addr_num = index+1; } @@ -198,10 +198,10 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -213,7 +213,7 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -224,9 +224,9 @@ void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) + for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 42647b1..6ff343c 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -65,7 +65,7 @@ static device_t __f0_dev[FX_DEVS]; device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; device_t get_node_pci(u32 nodeid, u32 fn) { @@ -605,9 +605,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -719,7 +718,7 @@ static void amdfam10_domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -879,7 +878,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { resource_t limitk_pri = 0; - for (i=0; i<sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { struct dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -982,11 +981,11 @@ static void amdfam10_domain_set_resources(device_t dev) // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1348,7 +1347,7 @@ static void sysconf_init(device_t dev) // first node unsigned ht_c_index; - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; } @@ -1369,7 +1368,7 @@ static void sysconf_init(device_t dev) // first node { sysconf.enabled_apic_ext_id = 1; } - #if (CONFIG_APIC_ID_OFFSET>0) + #if (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (sysconf.bsp_apicid == 0) { /* bsp apic id is not changed */ @@ -1492,7 +1491,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - while (dev_mc){ + while (dev_mc) { printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); @@ -1516,7 +1515,7 @@ static void cpu_bus_scan(device_t dev) nodes = sysconf.nodes; #if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe + if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1556,7 +1555,7 @@ static void cpu_bus_scan(device_t dev) devn = CONFIG_CDB+i; pbus = dev_mc->bus; #if CONFIG_CBB && (NODE_NUMS > 32) - if (i>=32) { + if (i >= 32) { busn--; devn-=32; pbus = pci_domain->link_list->next; @@ -1637,7 +1636,7 @@ static void cpu_bus_scan(device_t dev) jj = cores_found; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { u32 apic_id; if (dual_node) { @@ -1664,7 +1663,7 @@ static void cpu_bus_scan(device_t dev) } } -#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 7c7065df..bfc0da0 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -17,7 +17,7 @@ #define RAMINIT_H #if 0 -#if CONFIG_DIMM_SUPPORT==0x0110 +#if CONFIG_DIMM_SUPPORT == 0x0110 //FBDIMM REG /* each channel can have 8 fbdimm */ #define DIMM_SOCKETS 8 @@ -38,7 +38,7 @@ struct mem_controller { #endif #endif -//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004 +//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F * 2 for socket M2/M3 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 6d063ab..86f0788 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -524,7 +524,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 return freq; } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #include "amdfam10.h" #include "../amdmct/wrappers/mcti.h" #include "../amdmct/amddefs.h" @@ -633,7 +633,7 @@ int mctRead_SPD(u32 smaddr, u32 reg) void mctSMBhub_Init(u32 node) { struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); + struct mem_controller *ctrl = &(sysinfo->ctrl[node]); activate_spd_rom(ctrl); } @@ -642,9 +642,9 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) { int j; struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); + struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; } diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index df3850b..0461323 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -56,7 +56,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const int j; int index = 0; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = NODE_PCI(i, 0); @@ -70,7 +70,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const ctrl->spd_switch_addr = spd_addr[index++]; - for (j=0; j < 8; j++) { + for (j = 0; j < 8; j++) { ctrl->spd_addr[j] = spd_addr[index++]; } diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index bdf70b5..7ddf93f 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -116,8 +116,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b if ((config_map & 3) != 3) { continue; } - if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8) ) - ) == val ) + if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8)) + ) == val) { return (config_map >> 16) & 0xff; } diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 6de7a8c..7e71cf7 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -72,9 +72,9 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset if (IS_ENABLED(RES_DEBUG)) printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i/4, register_values[i], - register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), + register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], - register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) + register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); switch (register_values[i]) { case RES_PCI_IO: //PCI diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c index e34fa4c..2e6c103 100644 --- a/src/northbridge/amd/amdht/AsPsNb.c +++ b/src/northbridge/amd/amdht/AsPsNb.c @@ -43,13 +43,13 @@ u8 getMinNbCOF(void) numOfNode = getNumOfNodeNb(); /* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */ - for (i=0; i < numOfNode; i++) + for (i = 0; i < numOfNode; i++) { /* stub function for APIC ID virtualization for large MP system later */ deviceId = translateNodeIdToDeviceIdNb(i); - /* read all P-state spec registers for NbDid=1 */ - for (j=0; j < 5; j++) + /* read all P-state spec registers for NbDid = 1 */ + for (j = 0; j < 5; j++) { AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */ /* get NbDid */ @@ -86,13 +86,13 @@ u8 getMinNbCOF(void) nextNbFid = nextNbFid >> 1; */ } } - if ( i == 0) + if (i == 0) nbFid = nextNbFid; - else if ( nbFid > nextNbFid ) + else if (nbFid > nextNbFid) nbFid = nextNbFid; } - /* add the base and convert to 100MHz divide by 2 if DID=1 */ + /* add the base and convert to 100MHz divide by 2 if DID = 1 */ if (nbDid) nbFid = (u8) (nbFid + 4); else diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 64092ff..7a15325 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -120,7 +120,7 @@ void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length) ASSERT(pDst != NULL); ASSERT(pSrc != NULL); - while (length--){ + while (length--) { // *(((u8*)pDst)++) = *(((u8*)pSrc)++); *((u8*)pDst) = *((u8*)pSrc); pDst++; @@ -134,7 +134,7 @@ void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length) ASSERT(length <= 32768); ASSERT(pBuf != NULL); - while (length--){ + while (length--) { //*(((u8*)pBuf)++) = val; *(((u8*)pBuf)) = val; pBuf++; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index bfda13d..b4838b4 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -671,7 +671,7 @@ static void htDiscoveryFloodFill(sMainData *pDat) pDat->TotalLinks++; - if ( !pDat->sysMatrix[currentNode][token] ) + if (!pDat->sysMatrix[currentNode][token]) { pDat->sysDegree[currentNode]++; pDat->sysDegree[token]++; @@ -745,8 +745,8 @@ static BOOL isoMorph(u8 i, sMainData *pDat) { for (k = 0; k < nodecnt; k++) { - if ( pDat->sysMatrix[j][k] != - pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]] ) + if (pDat->sysMatrix[j][k] != + pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]]) return FALSE; } } @@ -1356,12 +1356,12 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i].SelRegang = FALSE; pDat->PortList[i+1].SelRegang = FALSE; - if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) + if ((pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) continue; /* Only process CPU to CPU links */ for (j = i+2; j < pDat->TotalLinks*2; j += 2) { - if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) + if ((pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU)) continue; /* Only process CPU to CPU links */ if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) @@ -1506,7 +1506,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBBAUpstreamWidth = 16; #endif - if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) + if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)) { if (pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits) { @@ -1639,7 +1639,7 @@ static void hammerSublinkFixup(sMainData *pDat) { if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */ (loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */ - (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */ + (loFreq != 2)) /* {13, 2} 2400MHz / 400MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 11) @@ -1651,19 +1651,19 @@ static void hammerSublinkFixup(sMainData *pDat) { if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */ (loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */ - (loFreq != 0) ) /* { 9, 0} 1600MHz / 200MHz 8:1 */ + (loFreq != 0)) /* { 9, 0} 1600MHz / 200MHz 8:1 */ downgrade = TRUE; } else if (hiFreq == 7) { if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */ - (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */ + (loFreq != 0)) /* { 7, 0} 1200MHz / 200MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 5) { if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */ - (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */ + (loFreq != 0)) /* { 5, 0} 800MHz / 200MHz 4:1 */ downgrade = TRUE; } else if (hiFreq == 2) @@ -1807,7 +1807,7 @@ static void tuning(sMainData *pDat) /* For each node, invoke northbridge specific buffer tunings or * system specific customizations. */ - for (i=0; i < pDat->NodesDiscovered + 1; i++) + for (i = 0; i < pDat->NodesDiscovered + 1; i++) { if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL) || !pDat->HtBlock->AMD_CB_CustomizeBuffers(i)) diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index ab2dace..c973792 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -358,7 +358,7 @@ typedef struct { * * --------------------------------------------------------------------------------------- */ - BOOL (*AMD_CB_CustomizeTrafficDistribution)( void ); + BOOL (*AMD_CB_CustomizeTrafficDistribution)(void); /**---------------------------------------------------------------------------------------- @@ -379,7 +379,7 @@ typedef struct { * * --------------------------------------------------------------------------------------- */ - BOOL (*AMD_CB_CustomizeBuffers)( u8 node ); + BOOL (*AMD_CB_CustomizeBuffers)(u8 node); /**---------------------------------------------------------------------------------------- * diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cbe90e0..0d0055b 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * @param[in] link = the link on that Node to examine * @param[in] *nb = this northbridge * @return true - The link has the following status - * linkCon=1, Link is connected - * InitComplete=1, Link initialization is complete - * NC=0, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * linkCon = 1, Link is connected + * InitComplete = 1, Link initialization is complete + * NC = 0, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * *****************************************************************************/ @@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; #else return 0; @@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 3, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -662,7 +662,7 @@ static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 31, 0, &leveling); - for (i=0; i<cores; i++) + for (i = 0; i < cores; i++) { if (leveling & ((u32) 1 << i)) { @@ -1122,11 +1122,11 @@ static u8 readSbLink(cNorthBridge *nb) * @param[in] link = the Link on that node to examine * @param[in] *nb = this northbridge * @return = true - The link has the following status - * LinkCon=1, Link is connected - * InitComplete=1,Link initilization is complete - * NC=1, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * LinkCon = 1, Link is connected + * InitComplete = 1,Link initilization is complete + * NC = 1, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * * --------------------------------------------------------------------------------------- @@ -1143,7 +1143,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - /* Verify linkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT; } @@ -1922,7 +1922,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links01); - /* DstNode = 1, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0107; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0), makePCIBusFromNode(0), @@ -1939,7 +1939,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * CPU_HTNB_FUNC_00, REG_HT_TRAFFIC_DIST_0X164), 23, 16, &links10); - /* DstNode = 0, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */ + /* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */ temp = 0x0007; AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1), makePCIBusFromNode(1), @@ -2088,13 +2088,13 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_FIFOPTR_3XDC); - for (i=0; i < nb->maxLinks; i++) + for (i = 0; i < nb->maxLinks; i++) { temp = 0; if (nb->verifyLinkIsCoherent(node, i, nb)) { temp = 0x26; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } else @@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (nb->verifyLinkIsNonCoherent(node, i, nb)) { temp = 0x25; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } } @@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3 * (and, one assumes, from there on). */ - for (i=0; i < (pDat->NodesDiscovered +1); i++) + for (i = 0; i < (pDat->NodesDiscovered +1); i++) { AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i), makePCIBusFromNode(i), @@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } } - for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) + for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) { isOuter = FALSE; /* Check for outer node by scanning the config maps on node 0 for one @@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (node == (u8)temp) { /* This is an outer node. Tune it appropriately. */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (isErrata153) { @@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (isErrata153) { /* Tuning for inner node coherent links */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (nb->verifyLinkIsCoherent(node, j, nb)) { diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 992a85e..906dc0b 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -101,7 +101,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) */ if ((basek+sizek)<1024) return; - if (basek<1024) { + if (basek < 1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,29 +158,29 @@ static unsigned long acpi_fill_slit(unsigned long current) p += 8; #if 0 - for (i=0;i<sysconf.hc_possible_num;i++) { - if ((sysconf.pci1234[i]&1) !=1 ) continue; + for (i = 0; i < sysconf.hc_possible_num; i++) { + if ((sysconf.pci1234[i]&1) !=1) continue; outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif - for (i=0;i<nodes;i++) { - for (j=0;j<nodes; j++) { - if (i==j) { + for (i = 0; i < nodes; i++) { + for (j = 0; j < nodes; j++) { + if (i == j) { p[i*nodes+j] = 10; } else { #if 0 int k; u8 latency_factor = 0; int k_start, k_end; - if (i<j) { + if (i < j) { k_start = i; k_end = j; } else { k_start = j; k_end = i; } - for (k=k_start;k<=k_end; k++) { + for (k = k_start; k <= k_end; k++) { if (outer_node[k]) { latency_factor = 1; break; @@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCLK"); acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x0); } @@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCDN"); acpigen_write_package(HC_POSSIBLE_NUM); - for (i=0;i<sysconf.hc_possible_num;i++) { + for (i = 0; i < sysconf.hc_possible_num; i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } acpigen_pop_len(); @@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_write_name(name); acpigen_write_package(dlen); - for (i=0; i<dlen; i++) { + for (i = 0; i < dlen; i++) { dword = pci_read_config32(dev, offset+i*4); acpigen_write_dword(dword); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7e33feb..887a23b 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -139,7 +139,7 @@ static void disable_probes(void) printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... "); - val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); + val = pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; @@ -193,7 +193,7 @@ static void enable_routing(u8 node) /* Enable routing table */ printk(BIOS_SPEW, "Enabling routing table for node %d", node); - val=pci_read_config32(NODE_HT(node), 0x6c); + val = pci_read_config32(NODE_HT(node), 0x6c); val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); @@ -241,7 +241,7 @@ static void rename_temp_node(u8 node) printk(BIOS_SPEW, "Renaming current temporary node to %d", node); - val=pci_read_config32(NODE_HT(7), 0x60); + val = pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); @@ -401,7 +401,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo uint8_t linkn; uint32_t val; val = 1; - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { uint8_t regpos; uint32_t reg; regpos = 0x98 + 0x20 * linkn; @@ -423,10 +423,10 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) if (((source &1)!=(dest &1)) #if CROSS_BAR_47_56 - && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here + && ((source < 4)||(source > 5)) //(6,7) (7,6) should still be here //(6,5) (7,4) should be here #endif - ){ + ) { val |= (1<<16); } else { /*for CROSS_BAR_47_56 47, 56, should be here too @@ -437,7 +437,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) val |= ((val_s>>16) - (1<<(linkn+1)))<<16; } - fill_row(temp,dest, val ); + fill_row(temp,dest, val); } #if CROSS_BAR_47_56 @@ -453,7 +453,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num) { int i; - for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); } } @@ -470,7 +470,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { int i; - for (i=0; i<num; i+=3) { + for (i = 0; i < num; i+=3) { opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); } } @@ -535,7 +535,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif #if !CROSS_BAR_47_56 u8 gateway; u8 diff; - if (source<dest) { + if (source < dest) { gateway = source + 2; } else { gateway = source - 2; @@ -552,7 +552,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif diff = ((source&1)!=(dest &1)); #endif - if (diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ + if (diff && (val_s!=(val&0xff))) { /* use another connect as response*/ val_s -= val & 0xff; #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED uint8_t byte; @@ -562,14 +562,14 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif byte = val_s; byte = get_linkn_last_count(byte); if ((byte>>2)>1) { /* make sure not the corner*/ - if (source<dest) { + if (source < dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 #if 0 - if (source==7) { + if (source == 7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 - } else if (source==6){ + } else if (source == 6) { val_s-=link_connection(temp, 7); // for 6,3 via 4 } else #endif @@ -614,10 +614,10 @@ static void setup_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif @@ -641,10 +641,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { setup_remote_row_indirect(conn[i], conn[i+1]); #else - for (i=0; i<num; i+=4) { + for (i = 0; i < num; i+=4) { setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif } @@ -658,7 +658,7 @@ static void setup_uniprocessor(void) printk(BIOS_SPEW, "Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; - if (tmp>0) return; + if (tmp > 0) return; #endif disable_probes(); } @@ -668,10 +668,10 @@ static int optimize_connection_group(const u8 *opt_conn, int num) { int needs_reset = 0; int i; - for (i=0; i<num; i+=2) { + for (i = 0; i < num; i+=2) { needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), - NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); + NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i]))); } return needs_reset; } @@ -689,7 +689,7 @@ static unsigned setup_smp2(void) val = get_row(0,0); byte = (val>>16) & 0xfe; - if (byte<0x2) { /* no coherent connection so get out.*/ + if (byte < 0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } @@ -717,7 +717,7 @@ static unsigned setup_smp2(void) val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); - if ((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/ + if ((byte>>2) == 3) { /* Oh! we need to treat it as node2. So use another link*/ val = get_row(0,0); byte = (val>>16) & 0xfe; #if TRY_HIGH_FIRST == 1 @@ -760,14 +760,14 @@ static unsigned setup_smp4(void) u8 byte; uint32_t val; - nodes=4; + nodes = 4; /* Setup and check temporary connection from Node 0 to Node 2 */ val = get_row(0,0); byte = ((val>>16) & 0xfe) - link_connection(0,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have two coherent for 4p and above*/ + if ((byte>>2) == 0) { /* We should have two coherent for 4p and above*/ nodes = 2; return nodes; } @@ -841,7 +841,7 @@ static unsigned setup_smp4(void) #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED /* We need to find out which link is to node3 */ - if ((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ + if ((byte>>2) == 2) { /* one to node3, one to node0, one to node4*/ val = get_row(7,3); if ((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/ val = get_row(2,2); @@ -865,7 +865,7 @@ static unsigned setup_smp4(void) val = get_row(7,3); byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent links on node 3 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(3,5) link=", byte); setup_remote_row_direct(3, 5, byte); @@ -875,7 +875,7 @@ static unsigned setup_smp4(void) byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent link on node 2 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(2,4) link=", byte); setup_row_direct(2, 4, byte); @@ -931,14 +931,14 @@ static unsigned setup_smp6(void) u8 byte; uint32_t val; - nodes=6; + nodes = 6; /* Setup and check temporary connection from Node 0 to Node 4 through 2*/ val = get_row(2,2); byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent link on node 2 for 6p and above*/ nodes = 4; return nodes; } @@ -948,7 +948,7 @@ static unsigned setup_smp6(void) val = get_row(3,3); byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent links on node 3 for 6p and above*/ nodes = 4; return nodes; } @@ -975,7 +975,7 @@ static unsigned setup_smp6(void) setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1003,7 +1003,7 @@ static unsigned setup_smp6(void) enable_routing(4); setup_temp_row(0,1); - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } verify_connection(7); @@ -1031,7 +1031,7 @@ static unsigned setup_smp6(void) #if CONFIG_MAX_PHYSICAL_CPUS > 6 /* We need to find out which link is to node5 */ - if ((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ + if ((byte>>2) == 2) { /* one to node5, one to node2, one to node6*/ val = get_row(7,5); if ((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ val = get_row(4,4); @@ -1054,7 +1054,7 @@ static unsigned setup_smp6(void) val = get_row(7,5); byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent links on node 5 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(5,7) link=", byte); setup_remote_row_direct(5, 7, byte); @@ -1065,7 +1065,7 @@ static unsigned setup_smp6(void) byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); - if ((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + if ((byte>>2) == 1) { /* We should have three coherent link on node 4 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(4,6) link=", byte); setup_row_direct(4, 6, byte); @@ -1115,7 +1115,7 @@ static unsigned setup_smp6(void) /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) * It will be done by clear_dead_links */ - for (byte=0; byte<4; byte++) { + for (byte = 0; byte < 4; byte++) { clear_temp_row(byte); } #endif @@ -1134,7 +1134,7 @@ static unsigned setup_smp8(void) u8 byte; uint32_t val; - nodes=8; + nodes = 8; /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ val = get_row(4,4); @@ -1143,7 +1143,7 @@ static unsigned setup_smp8(void) #else byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); /* Max link to 6*/ - if ((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + if ((byte>>2) == 0) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; return nodes; } @@ -1170,7 +1170,7 @@ static unsigned setup_smp8(void) val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); byte = get_linkn_last_count(byte); - if ((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2) == 0) { /* We should have three coherent links on node 5 for 6p and above*/ nodes = 6; return nodes; } @@ -1203,7 +1203,7 @@ static unsigned setup_smp8(void) setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); - for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1241,7 +1241,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } setup_temp_row(5,6); @@ -1249,7 +1249,7 @@ static unsigned setup_smp8(void) verify_connection(7); val = get_row(7,6); // to chect it if it is node6 before renaming - if ( (val>>16) == 1) { // it is real node 7 so swap it + if ((val>>16) == 1) { // it is real node 7 so swap it /* We need to recompute link to 6 */ val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,3); @@ -1262,7 +1262,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); #if 0 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } #endif @@ -1282,7 +1282,7 @@ static unsigned setup_smp8(void) #if !CROSS_BAR_47_56 setup_temp_row(0,1); - for (byte=0; byte<6; byte+=2) { + for (byte = 0; byte < 6; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1302,7 +1302,7 @@ static unsigned setup_smp8(void) setup_row_direct(4, 7, byte); /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte,byte+2); } @@ -1327,7 +1327,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 7, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for (byte=0; byte<4; byte+=2) { + for (byte = 0; byte < 4; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1511,7 +1511,7 @@ static unsigned verify_mp_capabilities(unsigned nodes) mask = 0x06; /* BigMPCap */ - for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { mask &= pci_read_config32(NODE_MC(node), 0xe8); } @@ -1525,7 +1525,7 @@ static unsigned verify_mp_capabilities(unsigned nodes) break; #endif case 0x00: /* Non SMP */ - if (nodes >1 ) { + if (nodes >1) { printk(BIOS_ERR, "Going back to UP\n"); return 1; } @@ -1542,7 +1542,7 @@ static void clear_dead_routes(unsigned nodes) int last_row; int node, row; #if CONFIG_MAX_PHYSICAL_CPUS == 8 - if (nodes==8) return;/* don't touch (7,7)*/ + if (nodes == 8) return;/* don't touch (7,7)*/ #endif last_row = nodes; if (nodes == 1) { @@ -1555,9 +1555,9 @@ static void clear_dead_routes(unsigned nodes) } /* Update the local row */ - for ( node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { uint32_t val = 0; - for (row =0; row<nodes; row++) { + for (row =0; row < nodes; row++) { val |= get_row(node, row); } fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); @@ -1571,7 +1571,7 @@ static unsigned verify_dualcore(unsigned nodes) unsigned node, totalcpus, tmp; totalcpus = 0; - for (node=0; node<nodes; node++) { + for (node = 0; node < nodes; node++) { tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; totalcpus += (tmp + 1); } @@ -1626,7 +1626,7 @@ static void coherent_ht_finalize(unsigned nodes) /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ - val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); + val = pci_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); @@ -1666,14 +1666,14 @@ static int apply_cpu_errata_fixes(unsigned nodes) if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); - pci_write_config32(dev, 0x70, cmd ); + pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); - pci_write_config32(dev, 0x7c, cmd ); + pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } /* Clock Power/Timing Low */ @@ -1694,7 +1694,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) cmd_ref = 0x04e20707; /* Registered */ cmd = pci_read_config32(dev, 0xd4); if (cmd != cmd_ref) { - pci_write_config32(dev, 0xd4, cmd_ref ); + pci_write_config32(dev, 0xd4, cmd_ref); needs_reset = 1; /* Needed? */ } } @@ -1765,14 +1765,14 @@ static int optimize_link_coherent_ht(void) nodes = get_nodes(); #if CONFIG_MAX_PHYSICAL_CPUS > 1 - if (nodes>1) { + if (nodes > 1) { needs_reset |= optimize_connection( NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), - NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0))); } #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if (nodes>2) { + if (nodes > 2) { /* optimize physical connections - by LYH */ static const u8 opt_conn4[] = { 0,2, @@ -1784,7 +1784,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 - if (nodes>4) { + if (nodes > 4) { static const uint8_t opt_conn6[] ={ 2, 4, 3, 5, @@ -1797,7 +1797,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if (nodes>6) { + if (nodes > 6) { static const uint8_t opt_conn8[] ={ 4, 6, #if CROSS_BAR_47_56 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 18fc858..a8431f4 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -71,7 +71,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -185,7 +185,7 @@ static void dump_smbus_registers(void) printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( smbus_read_byte(device, 0) < 0 ) continue; + if (smbus_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; @@ -211,7 +211,7 @@ static inline void dump_io_resources(unsigned port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { uint8_t val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -229,8 +229,8 @@ static inline void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for (i=start;i<end;i++) { - if ((i & 0xf)==0) { + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index d07da2a..638511a 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -64,7 +64,7 @@ static void enumerate_ht_chain(void) pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. + if (next_unitid >= 0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -127,7 +127,7 @@ out: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { + if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index 858a0c0..6da042f 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -144,7 +144,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); } while (((dcm & DCM_MemClrStatus) == - 0) /* || ((dcm & DCM_DramEnabled) == 0) */ ); + 0) /* || ((dcm & DCM_DramEnabled) == 0) */); if (loops >= TIMEOUT_LOOPS) { printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index ce039af..a679150 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -537,9 +537,9 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) if (sysinfo->nodes == 1) return; // in case only one CPU installed - for (i=1; i<sysinfo->nodes; i++) { + for (i = 1; i < sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->mem_trained[i]==0x00) continue; + if (sysinfo->mem_trained[i]== 0x00) continue; mask |= (1<<i); @@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) i%=sysinfo->nodes; } - for (i=0; i<sysinfo->nodes; i++) { + for (i = 0; i < sysinfo->nodes; i++) { printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); switch(sysinfo->mem_trained[i]) { case 0: //don't need train diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 9cf4083..32f56b5 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -51,7 +51,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + printk(BIOS_DEBUG, "node.link = bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif @@ -170,7 +170,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * Total: 12 * * Just put all the possible HT Node/link to the list tp pci1234[] in - * src/mainboard/<vendor>/<mainboard>get_bus_conf.c + * src/mainboard/<vendor>/<mainboard > get_bus_conf.c * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and * socket 3 on a 4 way system? Treat that as an HC, too! @@ -211,7 +211,7 @@ void get_sblk_pci1234(void) dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for (j=0;j<4;j++) { + for (j = 0; j < 4; j++) { uint32_t dwordx; dwordx = pci_read_config32(dev, 0xe0 + j*4); dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ @@ -225,7 +225,7 @@ void get_sblk_pci1234(void) /* We need to find out the number of HC * for exact match */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -234,7 +234,7 @@ void get_sblk_pci1234(void) } /* For 0xff0 match or same node */ - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; @@ -244,7 +244,7 @@ void get_sblk_pci1234(void) } } - for (i=1;i<sysconf.hc_possible_num;i++) { + for (i = 1; i < sysconf.hc_possible_num; i++) { if ((sysconf.pci1234[i] & 1) != 1) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index bc50b66..971c4a5 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -118,7 +118,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) uint32_t id; freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, unfiltered freq_cap = 0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ id = pci_read_config32(dev, 0); @@ -148,7 +148,7 @@ static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) #endif } - printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + printk(BIOS_SPEW, "pos = 0x%x, filtered freq_cap = 0x%x\n", pos, freq_cap); #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 freq_cap &= 0x3f; @@ -221,7 +221,7 @@ static int ht_optimize_link( /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1 = 0x%x, freq_cap2 = 0x%x\n", freq_cap1, freq_cap2); /* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -230,11 +230,11 @@ static int ht_optimize_link( old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq = 0x%x, freq = 0x%x, needs_reset = 0x%0x\n", old_freq, freq, needs_reset); /* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -243,45 +243,45 @@ static int ht_optimize_link( /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1 = 0x%x, width_cap2 = 0x%x\n", width_cap1, width_cap2); /* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input width = 0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1 = 0x%x, ln_width2 = 0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev1 input|output width = 0x%x\n", width); /* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev1 input|output width = 0x%x\n", width); /* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "dev2 input|output width = 0x%x\n", width); /* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); + printk(BIOS_SPEW, "old dev2 input|output width = 0x%x\n", width); /* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -374,7 +374,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (offset_unitid) { - if (next_unitid>= (bus ? 0x20:0x18) ) { + if (next_unitid>= (bus ? 0x20:0x18)) { if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; @@ -428,9 +428,9 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, /* Remeber the location of the last device */ udev = dev; upos = pos; - uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS; + uoffs = (offs != PCI_HT_SLAVE0_OFFS) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS; - } while (last_unitid != next_unitid ); + } while (last_unitid != next_unitid); #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: @@ -438,7 +438,7 @@ out: end_of_chain: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { + if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; @@ -448,7 +448,7 @@ end_of_chain: ; #if CONFIG_RAMINIT_SYSINFO // Here need to change the dev in the array int i; - for (i=0;i<sysinfo->link_pair_num;i++) + for (i = 0; i < sysinfo->link_pair_num; i++) { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { @@ -514,9 +514,9 @@ static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt link_type = dword & 0xff; - if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + if ((link_type & 7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/ dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); - dword &= ~( 0xff<<(linkn *8) ); + dword &= ~(0xff<<(linkn *8)); dword |= val << (linkn *8); if (dword != dword_old) { @@ -551,10 +551,10 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) devn = offset_unit_id(i == 0) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; - reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted - if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) { + reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted + if ((reg & 0xffff) == PCI_VENDOR_ID_AMD) { val = 0x25; - } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) { + } else if ((reg & 0xffff) == PCI_VENDOR_ID_NVIDIA) { val = 0x25;//??? } else { continue; @@ -581,9 +581,9 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, dword = pci_read_config32(dev, regpos); link_type = dword & 0xff; - if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + if ((link_type & 0x7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/ regpos = 0x90 + (linkn * 0x20); - dword = pci_read_config32(dev, regpos ); + dword = pci_read_config32(dev, regpos); if (dword != val) { pci_write_config32(dev, regpos, val); @@ -615,8 +615,8 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, busn = (reg & 0xff0000)>>16; //busn for (devn = 0; devn < 0x20; devn++) { - reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? - if ( (reg & 0xffff) == vendorid ) { + reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? + if ((reg & 0xffff) == vendorid) { reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); break; } @@ -659,14 +659,14 @@ static int ht_setup_chains(uint8_t ht_c_num) reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); //We need setup 0x94, 0xb4, and 0xd4 according to the reg - devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 - regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; + devpos = ((reg & 0xf0)>>4)+0x18; // nodeid;it will decide 0x18 or 0x19 + regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; + dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ; dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; - pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); + pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword); /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(busn, offset_unit_id(i == 0)); @@ -712,29 +712,29 @@ static int ht_setup_chains_x(void) /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ - print_linkn_in("SBLink=", ((reg>>8) & 3) ); + /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */ + print_linkn_in("SBLink=", ((reg>>8) & 3)); #if CONFIG_RAMINIT_SYSINFO sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; #endif - tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); + tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); - next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ + next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ #if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ - tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit + tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg); - tempreg = 3 | ( 3<<4) | (0<<12); //base + tempreg = 3 | (3<<4) | (0<<12); //base pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg); next_io_base = 0x3+0x1; #endif /* clean others */ - for (ht_c_num=1;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); #if CONFIG_K8_ALLOCATE_IO_RANGE @@ -744,11 +744,11 @@ static int ht_setup_chains_x(void) #endif } - for (nodeid=0; nodeid<nodes; nodeid++) { + for (nodeid = 0; nodeid < nodes; nodeid++) { pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); - for (linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn < 3; linkn++) { unsigned regpos; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(dev, regpos); @@ -756,7 +756,7 @@ static int ht_setup_chains_x(void) print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); tempreg = 3 | (nodeid <<4) | (linkn<<8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ break; @@ -774,7 +774,7 @@ static int ht_setup_chains_x(void) /* io range allocation */ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); next_io_base += 0x3+0x1; #endif @@ -783,7 +783,7 @@ static int ht_setup_chains_x(void) } /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/ - for (nodeid = 1; nodeid<nodes; nodeid++) { + for (nodeid = 1; nodeid < nodes; nodeid++) { int i; pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); @@ -812,8 +812,8 @@ static int ht_setup_chains_x(void) } /* recount ht_c_num*/ - uint8_t i=0; - for (ht_c_num=0;ht_c_num<4; ht_c_num++) { + uint8_t i = 0; + for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if (((reg & 0xf) != 0x0)) { i++; @@ -840,15 +840,15 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) unsigned link_pair_num = sysinfo->link_pair_num; printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); - for (i=0; i< link_pair_num; i++) { + printk(BIOS_SPEW, "sysinfo->link_pair_num = 0x%x\n", link_pair_num); + for (i = 0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed = 0x%x\n", i, reset_needed); } reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed = 0x%x\n", reset_needed); return reset_needed; diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index a2b4651..3cbeb04 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -120,7 +120,7 @@ static void misc_control_init(struct device *dev) */ cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + pci_write_config32(dev, 0x44, cmd); #if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { @@ -129,11 +129,11 @@ static void misc_control_init(struct device *dev) */ cmd = pci_read_config32(dev, 0x80); cmd &= ~(1<<0); - pci_write_config32(dev, 0x80, cmd ); + pci_write_config32(dev, 0x80, cmd); cmd = pci_read_config32(dev, 0x84); cmd &= ~(1<<24); cmd &= ~(1<<8); - pci_write_config32(dev, 0x84, cmd ); + pci_write_config32(dev, 0x84, cmd); /* Errata 66 * Limit the number of downstream posted requests to 1 @@ -142,14 +142,14 @@ static void misc_control_init(struct device *dev) if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); - pci_write_config32(dev, 0x70, cmd ); + pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); - pci_write_config32(dev, 0x7c, cmd ); + pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } /* Clock Power/Timing Low */ @@ -175,7 +175,7 @@ static void misc_control_init(struct device *dev) } cmd = pci_read_config32(dev, 0xd4); if (cmd != cmd_ref) { - pci_write_config32(dev, 0xd4, cmd_ref ); + pci_write_config32(dev, 0xd4, cmd_ref); needs_reset = 1; /* Needed? */ } } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d80c565..2f71b8c 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -42,7 +42,7 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 static device_t __f0_dev[MAX_FX_DEVS]; static device_t __f1_dev[MAX_FX_DEVS]; -static unsigned fx_devs=0; +static unsigned fx_devs = 0; static void get_fx_devs(void) { @@ -178,7 +178,7 @@ static void amdk8_scan_chain(struct bus *link) config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | + ((nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | (0xff << 24); @@ -489,8 +489,8 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate) ) #endif break; @@ -505,7 +505,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) /* allocate a temp resource for the legacy VGA buffer */ resource = new_resource(dev, IOINDEX(4, link->link_num)); - if (!resource){ + if (!resource) { printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev)); return; } @@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id==-1) { u32 limitk_pri = 0; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); @@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) hole_sizek = (4*1024*1024) - hole_startk; - for (i=7;i>node_id;i--) { + for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) carry_over = (4*1024*1024) - hole_startk; - for (i=7;i>node_id;i--) { + for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -962,7 +962,7 @@ static void amdk8_domain_set_resources(device_t dev) #if CONFIG_GFXUMA - printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d : uma_memory_base/1024 = 0x%08llx, mmio_basek = 0x%08lx, basek = 0x%08x, limitk = 0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); #else @@ -970,11 +970,11 @@ static void amdk8_domain_set_resources(device_t dev) #endif /* See if I need to split the region to accommodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -984,7 +984,7 @@ static void amdk8_domain_set_resources(device_t dev) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (reset_memhole) #if !CONFIG_K8_REV_F_SUPPORT - if (!is_cpu_pre_e0() ) + if (!is_cpu_pre_e0()) #endif sizek += hoist_memory(mmio_basek,i); #endif @@ -1210,7 +1210,7 @@ static void cpu_bus_scan(device_t dev) // ----> you can mixed single core e0 and dual core e0 at any sequence // That is the typical case - if (j == 0 ){ + if (j == 0) { #if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else @@ -1222,10 +1222,10 @@ static void cpu_bus_scan(device_t dev) if (e0_later_single_core) { printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); - j=1; + j = 1; } - if (siblings > j ) { + if (siblings > j) { } else { siblings = j; @@ -1243,7 +1243,7 @@ static void cpu_bus_scan(device_t dev) jj = siblings; } - for (j = 0; j <=jj; j++ ) { + for (j = 0; j <=jj; j++) { u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index aab9fa7..ec90756 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -645,7 +645,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) value = spd_read_byte(device, 5); /* number of physical banks */ if (value < 0) goto hw_err; if (value == 1) goto out; - if ((value != 2) && (value != 4 )) { + if ((value != 2) && (value != 4)) { goto val_err; } #if CONFIG_QRANK_DIMM_SUPPORT @@ -748,7 +748,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) { static const unsigned cs_map_aa[] = { - /* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */ + /* (row = 12, col = 8)(14, 12) ---> (0, 0) (2, 4) */ 0, 1, 3, 6, 0, 0, 2, 4, 7, 9, 0, 0, 5, 8,10, @@ -760,7 +760,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map &= ~(0xf << (index * 4)); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map &= ~(0xf << ( (index + 2) * 4)); + map &= ~(0xf << ((index + 2) * 4)); } #endif @@ -771,7 +771,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map |= (sz.side1 - (25 + 3)) << (index *4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); + map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4); } #endif } @@ -779,7 +779,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz.rank == 4) { - map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); + map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4); } #endif } @@ -824,7 +824,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, limit = (limit_k << 2); limit &= 0xffff0000; limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); + limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; base |= (0 << 8) | (1<<1) | (1<<0); @@ -940,8 +940,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) } value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - cs_mode =( value >> ((index>>1)*4)) & 0xf; - if (cs_mode == 0 ) continue; + cs_mode =(value >> ((index>>1)*4)) & 0xf; + if (cs_mode == 0) continue; if (common_cs_mode == 0) { common_cs_mode = cs_mode; } @@ -960,7 +960,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) } /* Find the bits of csbase that we need to interleave on */ - if (is_cpu_pre_d0()){ + if (is_cpu_pre_d0()) { csbase_inc = 1 << csbase_low_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ @@ -974,8 +974,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) else { csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; if (is_dual_channel(ctrl)) { - if ( (bits==3) && (common_cs_mode > 8)) { -// printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n"); + if ((bits == 3) && (common_cs_mode > 8)) { +// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1223,7 +1223,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 5, /* *Physical Banks */ 6, /* *Module Data Width low */ 7, /* *Module Data Width high */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 11, /* *SDRAM Type */ 13, /* *SDRAM Width */ 17, /* *Logical Banks */ @@ -1390,7 +1390,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_ /* Following table comes directly from BKDG (unbuffered DIMM support) - [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty + [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1 = present 0 = empty X uses same layout but 1 means double rank 0 is single rank/empty Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to @@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ if (!is_cpu_pre_e0()) { - if (min_cycle_time==0x50) { + if (min_cycle_time == 0x50) { value |= 1<<31; } } @@ -1927,7 +1927,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa dimm = 1<<(DCL_x4DIMM_SHIFT+i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif @@ -2239,7 +2239,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, carry_over = (4*1024*1024) - hole_startk; - for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -2294,7 +2294,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) * we need to decrease it. */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2315,7 +2315,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2480,7 +2480,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node - 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node) + 5. for node interleaving we need to set mem hole to every node (need recalcute hole offset in f0 for every node) */ } @@ -2495,7 +2495,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -2505,7 +2505,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, if (spd_addr == (void *)0) continue; - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 67f3433..9d2f95d 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -222,7 +222,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in /* DRAM Control Register * F2:0x78 - * [ 3: 0] RdPtrInit ( Read Pointer Initial Value) + * [ 3: 0] RdPtrInit (Read Pointer Initial Value) * 0x03-0x00: reserved * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO) * 000 = reserved @@ -361,7 +361,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 01 = 3 bus clocks * 10 = 4 bus clocks * 11 = 5 bus clocks - * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, + * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel A, * BIOS should set it to reduce the power consumption) * Bit F(1207) M2 Package S1g1 Package * 0 N/A MA1_CLK1 N/A @@ -400,22 +400,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 10 = 2 bus clocks * 11 = 3 bus clocks * [13:12] Twrwr (Write to Write Timing) - * 00 = 1 bus clocks ( 0 idle cycle on the bus) - * 01 = 2 bus clocks ( 1 idle cycle on the bus) - * 10 = 3 bus clocks ( 2 idle cycles on the bus) + * 00 = 1 bus clocks (0 idle cycle on the bus) + * 01 = 2 bus clocks (1 idle cycle on the bus) + * 10 = 3 bus clocks (2 idle cycles on the bus) * 11 = Reserved - * [15:14] Trdrd ( Read to Read Timing) - * 00 = 2 bus clocks ( 1 idle cycle on the bus) - * 01 = 3 bus clocks ( 2 idle cycles on the bus) - * 10 = 4 bus clocks ( 3 idle cycles on the bus) - * 11 = 5 bus clocks ( 4 idle cycles on the bus) + * [15:14] Trdrd (Read to Read Timing) + * 00 = 2 bus clocks (1 idle cycle on the bus) + * 01 = 3 bus clocks (2 idle cycles on the bus) + * 10 = 4 bus clocks (3 idle cycles on the bus) + * 11 = 5 bus clocks (4 idle cycles on the bus) * [17:16] Tref (Refresh Rate) * 00 = Undefined behavior * 01 = Reserved * 10 = Refresh interval of 7.8 microseconds * 11 = Refresh interval of 3.9 microseconds * [19:18] Reserved - * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, + * [22:20] Trfc0 (Auto-Refresh Row Cycle Time for the Logical DIMM0, * based on DRAM density and speed) * 000 = 75 ns (all speeds, 256Mbit) * 001 = 105 ns (all speeds, 512Mbit) @@ -425,11 +425,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 101 = reserved * 110 = reserved * 111 = reserved - * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, + * [25:23] Trfc1 (Auto-Refresh Row Cycle Time for the Logical DIMM1, * based on DRAM density and speed) - * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, + * [28:26] Trfc2 (Auto-Refresh Row Cycle Time for the Logical DIMM2, * based on DRAM density and speed) - * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, + * [31:29] Trfc3 (Auto-Refresh Row Cycle Time for the Logical DIMM3, * based on DRAM density and speed) */ PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8), @@ -438,7 +438,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 0: 0] InitDram (Initialize DRAM) * 1 = write 1 cause DRAM controller to execute the DRAM * initialization, when done it read to 0 - * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command ) + * [ 1: 1] ExitSelfRef (Exit Self Refresh Command) * 1 = write 1 causes the DRAM controller to bring the DRAMs out * for self refresh mode * [ 3: 2] Reserved @@ -448,19 +448,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 10 = 150 ohms * 11 = 50 ohms * [ 6: 6] Reserved - * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode) + * [ 7: 7] DramDrvWeak (DRAM Drivers Weak Mode) * 0 = Normal drive strength mode. * 1 = Weak drive strength mode * [ 8: 8] ParEn (Parity Enable) * 1 = Enable address parity computation output, PAR, * and enables the parity error input, ERR * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) - * 1 = Enable high temperature ( two times normal ) + * 1 = Enable high temperature (two times normal) * self refresh rate - * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes) + * [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes) * 0 = 64-byte mode * 1 = 32-byte mode - * [11:11] Width128 ( Width of DRAM interface) + * [11:11] Width128 (Width of DRAM interface) * 0 = the controller DRAM interface is 64-bits wide * 1 = the controller DRAM interface is 128-bits wide * [12:12] X4Dimm (DIMM 0 is x4) @@ -469,19 +469,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [15:15] X4Dimm (DIMM 3 is x4) * 0 = DIMM is not x4 * 1 = x4 DIMM present - * [16:16] UnBuffDimm ( Unbuffered DIMMs) + * [16:16] UnBuffDimm (Unbuffered DIMMs) * 0 = Buffered DIMMs * 1 = Unbuffered DIMMs * [18:17] Reserved - * [19:19] DimmEccEn ( DIMM ECC Enable ) + * [19:19] DimmEccEn (DIMM ECC Enable) * 1 = ECC checking is being enabled for all DIMMs on the DRAM - * controller ( Through F3 0x44[EccEn]) + * controller (Through F3 0x44[EccEn]) * [31:20] Reserved */ PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010, /* DRAM Config High Register * F2:0x94 - * [ 0: 2] MemClkFreq ( Memory Clock Frequency) + * [ 0: 2] MemClkFreq (Memory Clock Frequency) * 000 = 200MHz * 001 = 266MHz * 010 = 333MHz @@ -490,25 +490,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 3: 3] MemClkFreqVal (Memory Clock Frequency Valid) * 1 = BIOS need to set the bit when setting up MemClkFreq to * the proper value - * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) + * [ 7: 4] MaxAsyncLat (Maximum Asynchronous Latency) * 0000 = 0 ns * ... * 1111 = 15 ns * [11: 8] Reserved - * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 + * [12:12] RDqsEn (Read DQS Enable) This bit is only be set if x8 * registered DIMMs are present in the system * 0 = DM pins function as data mask pins * 1 = DM pins function as read DQS pins * [13:13] Reserved - * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit + * [14:14] DisDramInterface (Disable the DRAM interface) When this bit * is set, the DRAM controller is disabled, and interface in low power * state * 0 = Enabled (default) * 1 = Disabled - * [15:15] PowerDownEn ( Power Down Mode Enable ) + * [15:15] PowerDownEn (Power Down Mode Enable) * 0 = Disabled (default) * 1 = Enabled - * [16:16] PowerDown ( Power Down Mode ) + * [16:16] PowerDown (Power Down Mode) * 0 = Channel CKE Control * 1 = Chip Select CKE Control * [17:17] FourRankSODimm (Four Rank SO-DIMM) @@ -526,17 +526,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * i.e., these signals are driven for two MEMCLK cycles * rather than one * [21:21] Reserved - * [22:22] BankSwizzleMode ( Bank Swizzle Mode), + * [22:22] BankSwizzleMode (Bank Swizzle Mode), * 0 = Disabled (default) * 1 = Enabled * [23:23] Reserved - * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum) + * [27:24] DcqBypassMax (DRAM Controller Queue Bypass Maximum) * 0000 = No bypass; the oldest request is never bypassed * 0001 = The oldest request may be bypassed no more than 1 time * ... * 1111 = The oldest request may be bypassed no more than 15\ * times - * [31:28] FourActWindow ( Four Bank Activate Window) , not more than + * [31:28] FourActWindow (Four Bank Activate Window) , not more than * 4 banks in a 8 bank device are activated * 0000 = No tFAW window restriction * 0001 = 8 MEMCLK cycles @@ -552,11 +552,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * when set, this bit indicates that the memory clear function * is complete. Only clear by reset. BIOS should not write or * read the DRAM until this bit is set by hardware - * [ 1: 1] DisableJitter ( Disable Jitter) + * [ 1: 1] DisableJitter (Disable Jitter) * When set the DDR compensation circuit will not change the * values unless the change is more than one step from the * current value - * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count) + * [ 3: 2] RdWrQByp (Read/Write Queue Bypass Count) * 00 = 2 * 01 = 4 * 10 = 8 @@ -565,11 +565,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1 When bit enables support for mismatched DIMMs when using * 128-bit DRAM interface, the Width128 no effect, only for * AM2 and s1g1 - * [ 5: 5] DCC_EN ( Dynamic Idle Cycle Counter Enable) + * [ 5: 5] DCC_EN (Dynamic Idle Cycle Counter Enable) * When set to 1, indicates that each entry in the page tables * dynamically adjusts the idle cycle limit based on page * Conflict/Page Miss (PC/PM) traffic - * [ 8: 6] ILD_lmt ( Idle Cycle Limit) + * [ 8: 6] ILD_lmt (Idle Cycle Limit) * 000 = 0 cycles * 001 = 4 cycles * 010 = 8 cycles @@ -578,16 +578,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 101 = 64 cycles * 110 = 128 cycles * 111 = 256 cycles - * [ 9: 9] DramEnabled ( DRAM Enabled) + * [ 9: 9] DramEnabled (DRAM Enabled) * When Set, this bit indicates that the DRAM is enabled, this * bit is set by hardware after DRAM initialization or on an exit * from self refresh. The DRAM controller is initialized after the - * hardware-controlled initialization process ( initiated by the + * hardware-controlled initialization process (initiated by the * F2 0x90[DramInit]) completes or when the BIOS-controlled * initialization process completes (F2 0x7c(EnDramInit] is * written from 1 to 0) * [23:10] Reserved - * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, + * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel B, * BIOS should set it to reduce the power consumption) * Bit F(1207) M2 Package S1g1 Package * 0 N/A MA1_CLK1 N/A @@ -785,7 +785,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) rank == 4 two side , and four ranks total Some one side two ranks, because of stacked */ - if ((value != 1) && (value != 2) && (value != 4 )) { + if ((value != 1) && (value != 2) && (value != 4)) { goto val_err; } sz->rank = value; @@ -797,9 +797,9 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) if (value < 0) goto hw_err; value &= 0xff; value = log2(value); - if (value <=4 ) value += 8; // add back to 1G to high + if (value <=4) value += 8; // add back to 1G to high value += (27-5); // make 128MB to the real lines - if ( value != (sz->per_rank)) { + if (value != (sz->per_rank)) { printk(BIOS_ERR, "Bad RANK Size --\n"); goto val_err; } @@ -836,12 +836,12 @@ static void set_dimm_size(const struct mem_controller *ctrl, /* Make certain side1 of the dimm is at least 128MB */ if (sz->per_rank >= 27) { - base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + base0 = (1 << ((sz->per_rank - 27) + 19)) | 1; } /* Make certain side2 of the dimm is at least 128MB */ if (sz->rank > 1) { // 2 ranks or 4 ranks - base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + base1 = (1 << ((sz->per_rank - 27) + 19)) | 1; } /* Double the size if we are using dual channel memory */ @@ -932,7 +932,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, struct mem_info *meminfo) { static const uint8_t cs_map_aaa[24] = { - /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ + /* (bank = 2, row = 13, col = 9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ //Bank2 0, 1, 3, 0, 2, 6, @@ -954,7 +954,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, map &= ~(0xf << (index * 4)); #if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { - map &= ~(0xf << ( (index + 2) * 4)); + map &= ~(0xf << ((index + 2) * 4)); } #endif @@ -965,7 +965,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, map |= temp_map << (index*4); #if CONFIG_QRANK_DIMM_SUPPORT if (sz->rank == 4) { - map |= temp_map << ( (index + 2) * 4); + map |= temp_map << ((index + 2) * 4); } #endif } @@ -1018,7 +1018,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, limit = (limit_k << 2); limit &= 0xffff0000; limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); + limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; base |= (0 << 8) | (1<<1) | (1<<0); @@ -1136,7 +1136,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, } value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - cs_mode =( value >> ((index>>1)*4)) & 0xf; + cs_mode =(value >> ((index>>1)*4)) & 0xf; if (common_cs_mode == 0xff) { common_cs_mode = cs_mode; } @@ -1351,8 +1351,8 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, if (is_opteron(ctrl)) { #if 0 - if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) { - meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffered dimm + if (registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1))) { + meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm // die("Mixed buffered and registered dimms not supported"); } //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM @@ -1441,7 +1441,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i * Keep them at the end to see other mismatches (if any). */ 18, /* *Supported CAS Latencies */ - 9, /* *Cycle time at highest CAS Latency CL=X */ + 9, /* *Cycle time at highest CAS Latency CL = X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; @@ -1647,7 +1647,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if ( cpuid1.edx & 0x02 ) { + if (cpuid1.edx & 0x02) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -1663,9 +1663,9 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) index = fid_start>>25; } - if (index>12) return divisor; + if (index > 12) return divisor; - if (i>3) return divisor; + if (i > 3) return divisor; return dv_a[index * 4+i]; @@ -1748,7 +1748,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig printk_raminit("\t\tvalue2: %08x\n", value); /* Only increase the latency if we decrease the clock */ - if (value >= *min_cycle_time ) { + if (value >= *min_cycle_time) { if (value < new_cycle_time) { new_cycle_time = value; new_latency = latency; @@ -1763,7 +1763,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig } - if (new_latency > 6){ + if (new_latency > 6) { return 1; } @@ -2052,7 +2052,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask, unsigned TT_REG, - unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX ) + unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX) { unsigned clocks, old_clocks; uint32_t dtl; @@ -2181,7 +2181,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl, value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us.... if (value < 0) return -1; - if (value == 1 ) { + if (value == 1) { value = 3; } else { value = 2; @@ -2267,7 +2267,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, mask_single_rank |= 1<<i; } - if (meminfo->sz[i].col==10) { + if (meminfo->sz[i].col == 10) { mask_page_1k |= 1<<i; } @@ -2278,17 +2278,17 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, rank = meminfo->sz[i].rank; #endif - if (value==4) { + if (value == 4) { mask_x4 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x4 |= 1<<(i+2); } #endif - } else if (value==16) { + } else if (value == 16) { mask_x16 |= (1<<i); #if CONFIG_QRANK_DIMM_SUPPORT - if (rank==4) { + if (rank == 4) { mask_x16 |= 1<<(i+2); } #endif @@ -2340,7 +2340,7 @@ static void set_DramTerm(const struct mem_controller *ctrl, if (param->divisor == 100) { //DDR2 800 if (meminfo->is_Width128) { - if (count_ones(meminfo->dimm_mask & 0x0f)==2) { + if (count_ones(meminfo->dimm_mask & 0x0f) == 2) { odt = 3; //50 ohms } } @@ -2503,7 +2503,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2524,23 +2524,23 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * { uint32_t dword; uint32_t dwordx; -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ unsigned SlowAccessMode = 0; #endif -#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT == 0x0104 /* DDR2 and REG */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; switch (meminfo->memclk_set) { case DCH_MemClkFreq_266MHz: - if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { dwordx = 0x002f2700; } break; case DCH_MemClkFreq_333MHz: - if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there? dwordx = 0x002f2f00; } @@ -2553,7 +2553,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT == 0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2593,7 +2593,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT == 0x0004 /* DDR2 and unbuffered */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; @@ -2609,7 +2609,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * if (dimm_mask == 0x03) { SlowAccessMode = 1; dword = 0x00111322; - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) { switch (meminfo->single_rank_mask) { case 0x03: dwordx = 0x00002f00; //x8 single Rank @@ -2620,14 +2620,14 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * default: dwordx = 0x00372f00; //x8 single Rank and double Rank mixed } - } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { + } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed - } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { + } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed } } else { - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank dwordx = 0x002f2f00; } else { dwordx = 0x002b2f00; @@ -2639,7 +2639,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * if (dimm_mask == 0x03) { SlowAccessMode = 1; dword = 0x00111322; - if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) { switch (meminfo->single_rank_mask) { case 0x03: dwordx = 0x00302220; //x8 single Rank @@ -2676,7 +2676,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2707,7 +2707,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CONFIG_CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE == 0x10 //only need to set for reg and x8 uint32_t dch; @@ -2749,7 +2749,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, for (i = 0; i < DIMM_SOCKETS; i++) { int rc; if (!(meminfo->dimm_mask & (1 << i)) && - !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) { + !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { continue; } printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i); @@ -2844,7 +2844,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, activate_spd_rom(ctrl); meminfo->dimm_mask = spd_detect_dimms(ctrl); - printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("sdram_set_spd_registers: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1))) { @@ -2852,24 +2852,24 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, return; } meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo); - printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_enable_2channels: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo); - printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_ram_size: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo); - printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_handle_unbuffered_dimms: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; result = spd_set_memclk(ctrl, meminfo); param = result.param; meminfo->dimm_mask = result.dimm_mask; - printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_memclk: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2881,7 +2881,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo); - printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask); + printk_raminit("spd_set_dram_timing: dimm_mask = 0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) goto hw_spd_err; @@ -2911,17 +2911,17 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, carry_over = (4*1024*1024) - hole_startk; - for (ii=controllers - 1;ii>i;ii--) { + for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); - limit += (carry_over << 2 ); - base += (carry_over << 2 ); + limit += (carry_over << 2); + base += (carry_over << 2); for (j = 0; j < controllers; j++) { pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit); - pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base ); + pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base); } } limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); @@ -2966,7 +2966,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; - for (i=0; i<controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -2985,7 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ - for (i=0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); @@ -3038,7 +3038,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); /* if no memory installed, disabled the interface */ - if (sysinfo->meminfo[i].dimm_mask==0x00){ + if (sysinfo->meminfo[i].dimm_mask == 0x00) { dch |= DCH_DisDramInterface; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); @@ -3046,7 +3046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dch |= DCH_MemClkFreqVal; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); /* address timing and Output driver comp Control */ - set_misc_timing(ctrl+i, sysinfo->meminfo+i ); + set_misc_timing(ctrl+i, sysinfo->meminfo+i); } } @@ -3108,7 +3108,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "Initializing memory: "); int loops = 0; @@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* Wait until it is safe to touch memory */ do { dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); - } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); + } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 if (cpu_f0_f1[i]) { @@ -3136,7 +3136,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); - if (tsc.lo<tsc0[i].lo) { + if (tsc.lo < tsc0[i].lo) { tsc.hi--; } tsc.lo -= tsc0[i].lo; @@ -3176,7 +3176,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; sysinfo->mem_trained[i] = 0x80; // mem need to be trained @@ -3226,7 +3226,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, int i; int j; struct mem_controller *ctrl; - for (i=0;i<controllers; i++) { + for (i = 0; i < controllers; i++) { ctrl = &ctrl_a[i]; ctrl->node_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -3236,7 +3236,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, if (spd_addr == (void *)0) continue; - for (j=0;j<DIMM_SOCKETS;j++) { + for (j = 0; j < DIMM_SOCKETS; j++) { ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 9f0b8db..42a77da 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -60,7 +60,7 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct int i; sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); } @@ -91,7 +91,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_id if (hole_reg & 1) { unsigned hole_startk; hole_startk = (hole_reg & (0xff<<24)) >> 10; - if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + if ((dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { dword += ((4*1024*1024 - hole_startk)<<2); } } @@ -197,7 +197,7 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; - if (p==1) { buf = buf_b; } + if (p == 1) { buf = buf_b; } else { buf = buf_a; } set_FSBASE (addr>>24); @@ -243,7 +243,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned unsigned result = DQS_FAIL; if (Pass == DQS_FIRST_PASS) { - if (pattern==1) { + if (pattern == 1) { test_buf = (uint32_t *)TestPattern1; } else { @@ -285,13 +285,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); - if (value == value_test){ + if (value == value_test) { result = DQS_PASS; } } if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted - if (result==DQS_PASS) { + if (result == DQS_PASS) { result = DQS_FAIL; } else { @@ -409,7 +409,7 @@ static uint16_t get_exact_T1000(unsigned i) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if ( cpuid1.edx & 0x02 ) { + if (cpuid1.edx & 0x02) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -425,7 +425,7 @@ static uint16_t get_exact_T1000(unsigned i) index = fid_start>>25; } - if (index>12) return T1000_a[i]; + if (index > 12) return T1000_a[i]; return TT_a[index * 4+i]; @@ -437,14 +437,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) uint32_t dword; dword = 0x00000000; - for (i=1; i<=3; i++) { + for (i = 1; i <= 3; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); } dword = 0x2f2f2f2f; - for (i=5; i<=7; i++) { + for (i = 5; i <= 7; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); @@ -554,14 +554,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? - if (Pass==DQS_FIRST_PASS) { - for (i=0;i<16;i++) { + if (Pass == DQS_FIRST_PASS) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; } } else { - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; } @@ -581,13 +581,13 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st channel = 1; } - for ( ; (channel < 2) && (!Errors); channel++) + for (; (channel < 2) && (!Errors); channel++) { print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); /* for each rank */ /* there are four receiver pairs, loosely associated with CS */ - for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + for (receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; @@ -642,7 +642,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; } - while ( RcvrEnDly < 0xaf) { // Sweep Delay value here + while (RcvrEnDly < 0xaf) { // Sweep Delay value here print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); if (RcvrEnDly & 1) { @@ -841,7 +841,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif - return (CTLRMaxDelay==0xae)?1:0; + return (CTLRMaxDelay == 0xae)?1:0; } @@ -859,7 +859,7 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); shift = bytelane; - while (shift>3) { + while (shift > 3) { shift-=4; } shift <<= 3; // 8 bit @@ -879,13 +879,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe dword = 0; dqs_delay &= 0xff; - for (i=0;i<4;i++) { + for (i = 0; i < 4; i++) { dword |= dqs_delay<<(i*8); } index = 1 + channel * 0x20 + direction * 4; - for (i=0; i<2; i++) { + for (i = 0; i < 2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); } @@ -898,7 +898,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d) if (size_d & 1) { //need round up min_d++; } - return ( min_d + (size_d>>1)); + return (min_d + (size_d>>1)); } static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay) @@ -1026,10 +1026,10 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) ); } -static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) +static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern) { - if (pattern == 0){ + if (pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { @@ -1056,7 +1056,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign } bytelane = 0; - for (i=0;i<9*64/4;i++) { + for (i = 0; i < 9*64/4; i++) { __asm__ volatile ( "movl %%fs:(%1), %0\n\t" :"=b"(value): "a" (addr_lo) @@ -1066,7 +1066,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); - for (j=0;j<4*8;j+=8) { + for (j = 0; j < 4*8; j+=8) { if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } @@ -1116,8 +1116,8 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); - for (DQSDelay=0; DQSDelay<48; DQSDelay++) { - MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { + MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff = All positions passing (1= PASS) } for (ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 @@ -1138,7 +1138,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } - for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); @@ -1150,7 +1150,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5); ReadDQSTestPattern(TestAddr<<8, Pattern); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass + MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1 = pass print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO(TestAddr); FlushDQSTestPattern(TestAddr<<8, Pattern); @@ -1166,7 +1166,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, RnkDlySeqPassMax = 0; RnkDlyFilterMax = 0; RnkDlyFilterMin = 0; - for (DQSDelay=0; DQSDelay<48; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) { if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); @@ -1176,7 +1176,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) { RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -1194,7 +1194,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, else { print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); - if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ + if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW) { Errors |= SB_SMALLDQS; } else { @@ -1371,15 +1371,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in //SetupDqsPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); - if (is_Width128){ + if (is_Width128) { pattern = 1; - for (i=0;i<16*18;i++) { + for (i = 0; i < 16*18; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; - for (i=0; i<16*9;i++) { + for (i = 0; i < 16*9; i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; } @@ -1397,7 +1397,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in channel = 1; } - while ( (channel<2) && (!Errors)) { + while ((channel < 2) && (!Errors)) { print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; @@ -1417,7 +1417,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in } channel++; - if (!is_Width128){ + if (!is_Width128) { //FIXME: 64MuxMode?? channel++; // skip channel if 64-bit mode } @@ -1458,7 +1458,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; InterFactor = 0xff - InterFactor; } @@ -1470,7 +1470,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay >>= 8; // /255 - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay += DQSDelay1; } else { @@ -1496,11 +1496,11 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info ByteLane = 8; for (channel = 0; channel < 2; channel++) { - for (i=0;i<2;i++) { + for (i = 0; i < 2; i++) { Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay); save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay); } @@ -1546,7 +1546,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; uint32_t dword; @@ -1568,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); dword = tsc1[i].lo + tsc0[i].lo; - if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + if ((dword < tsc1[i].lo) || (dword < tsc0[i].lo)) { tsc1[i].hi++; } tsc1[i].lo = dword; @@ -1583,7 +1583,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; if (!cpu_f0_f1[i]) continue; @@ -1591,7 +1591,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl do { tsc = rdtsc(); - } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); + } while ((tsc1[i].hi > tsc.hi) || ((tsc1[i].hi == tsc.hi) && (tsc1[i].lo > tsc.lo))); print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); } @@ -1661,8 +1661,8 @@ static unsigned int range_to_mtrr(unsigned int reg, #if CONFIG_MEM_TRAIN_SEQ != 1 printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + (type == MTRR_TYPE_UNCACHEABLE)?"UC": + ((type == MTRR_TYPE_WRBACK)?"WB":"Other") ); #endif set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); @@ -1737,7 +1737,7 @@ static void clear_mtrr_dqs(unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - for (i=0x204;i<0x210;i++) { + for (i = 0x204; i < 0x210; i++) { wrmsr(i, msr); } @@ -1890,7 +1890,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } @@ -1901,7 +1901,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; @@ -1919,7 +1919,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if (train_DqsPos(ctrl+i, sysinfo)) goto out; @@ -1932,7 +1932,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc continue; /* Skip everything if I don't have any memory on this controller */ - if (sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask == 0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; @@ -1948,7 +1948,7 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); } @@ -2004,7 +2004,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - if (train_DqsRcvrEn(ctrl, 2, sysinfo)){ + if (train_DqsRcvrEn(ctrl, 2, sysinfo)) { sysinfo->mem_trained[i]=0x83; // goto out; } @@ -2021,7 +2021,7 @@ out: #endif if (v) { - for (ii=0;ii<4;ii++) { + for (ii = 0; ii < 4; ii++) { print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 597b689..9e2d8a9 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -15,13 +15,13 @@ static int is_cpu_pre_c0(void) return 0; } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ +#define PCI_ADDR(BUS, DEV, FN, WHERE) (\ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x07) << 8) | \ ((WHERE) & 0xFF)) -#define PCI_DEV(BUS, DEV, FN) ( \ +#define PCI_DEV(BUS, DEV, FN) (\ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x7) << 8)) diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index fa03e4a..e6e79c8 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -50,9 +50,9 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int #if RES_DEBUG printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], - register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), + register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], - register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) + register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); #endif switch (register_values[i]) { @@ -103,7 +103,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int reg = read32(where); reg &= register_values[i+2]; reg |= register_values[i+3]; - write32( where, reg); + write32(where, reg); } break; #endif @@ -174,7 +174,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) reg = read32(where); reg &= register_values[i+1]; reg |= register_values[i+2]; - write32( where, reg); + write32(where, reg); #if 0 reg = read32(where); prink(BIOS_DEBUG, " RB %08x\n", reg); diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl index 6a9b69f..83d741e 100644 --- a/src/northbridge/amd/amdk8/util.asl +++ b/src/northbridge/amd/amdk8/util.asl @@ -44,9 +44,9 @@ Scope (\_SB) Method (DADD, 2, NotSerialized) { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) + Store(Arg1, Local0) + Store(Arg0, Local1) + Add(ShiftLeft(Local1,16), Local0, Local0) Return (Local0) } @@ -54,7 +54,7 @@ Scope (\_SB) Method (GHCE, 1, NotSerialized) // check if the HC enabled { Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } Else { Return (0x00) } } @@ -62,7 +62,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0) Return (Local0) } @@ -70,7 +70,7 @@ Scope (\_SB) { Store (0x00, Local0) Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0) Return (Local0) } @@ -80,7 +80,7 @@ Scope (\_SB) Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Store (And (ShiftRight(Local1, Local2), 0xff), Local0) Return (Local0) } diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index bbdd2ed..9d3e86a 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -74,8 +74,8 @@ #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2) #define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) #define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index 61b2b2b..3847688 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -23,16 +23,16 @@ #define PT_M2 1 #define PT_S1 2 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 4 /* j loop constraint. 4=CL 6.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 4 /* k loop constraint. 9=400 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 4 /* j loop constraint. 4 = CL 6.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 4 /* k loop constraint. 9 = 400 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -208,7 +208,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /* For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /* For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -218,14 +218,14 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM1Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM1Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /* Number of DIMMs loading CH A*/ @@ -233,16 +233,16 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /* Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -252,16 +252,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -271,27 +271,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -319,9 +319,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM 0 - 3 Receiver Enable Delay*/ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -399,72 +399,72 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /* Platform Configuration */ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /* Dram Timing */ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /* Dram Configuration */ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /* Dram Power */ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /* Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -472,8 +472,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /* ECC */ #define NV_ECC 50 /* Dram ECC enable*/ @@ -484,14 +484,14 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /*Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_Parity 60 /* Parity Enable*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /* global function */ @@ -505,11 +505,11 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Get_ChannelPS_Cfg0( unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, +void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL); -void Get_ChannelPS_Cfg1( unsigned MAAdimms, unsigned Speed, unsigned MAAload, +void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); -void Get_ChannelPS_Cfg2( unsigned MAAdimms, unsigned Speed, unsigned MAAload, +void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); u8 MCTDefRet(void); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 16e67df..c521ee7 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -195,7 +195,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. Complete Hypertransport Bus Configuration * 2. SMBus Controller Initialized * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to * entry * 6. All var MTRRs reset to zero @@ -308,7 +308,7 @@ restartinit: MCTMemClr_D(pMCTstat,pDCTstatA); } - mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 + mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0)); // Node 0 print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; @@ -434,7 +434,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); } @@ -452,7 +452,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 2; DIMM++) { - if (DIMM==0) { + if (DIMM == 0) { index = 0; /* CHA Write Data Timing Low */ } else { if (pDCTstat->Speed >= 4) { @@ -461,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, break; } } - for (Dir=0;Dir<2;Dir++) {//RD/WR + for (Dir = 0;Dir < 2;Dir++) {//RD/WR p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir]; val = stream_to_int(p); /* CHA Read Data Timing High */ Set_NB32_index_wait(dev, index_reg, index+1, val); @@ -474,7 +474,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78 + Channel * 0x100; val = Get_NB32(dev, reg); val &= ~(0x3ff<<22); @@ -497,7 +497,7 @@ static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, * or normal ECC memory conditioning. */ - //FIXME: this function depends on pDCTstat Array ( with Node id ) - Is this really a problem? + //FIXME: this function depends on pDCTstat Array (with Node id) - Is this really a problem? u32 dev; u8 Node; @@ -650,7 +650,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(dev, reg); Set_NB32(devx, reg, val); reg += 4; - } while ( reg < 0x80); + } while (reg < 0x80); } else { break; /* stop at first absent Node */ } @@ -672,7 +672,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, u8 Node; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { // FIXME: callback to wrapper: mctDoWarmResetMemClr_D } else { // NV_DQSTrainCTL == 1 for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -723,7 +723,7 @@ static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, u8 Node; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { // callback to wrapper: mctDoWarmResetMemClr_D } else { // NV_DQSTrainCTL == 1 for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -745,7 +745,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, u32 reg; /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit){ + if (pDCTstat->DCTSysLimit) { reg = 0x110; do { @@ -834,7 +834,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst u32 reg_off = dct * 0x100; val = 1<<DisDramInterface; Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val); - /*To maximize power savings when DisDramInterface=1b, + /*To maximize power savings when DisDramInterface = 1b, all of the MemClkDis bits should also be set.*/ val = 0xFF000000; Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val); @@ -997,7 +997,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, pDCTstat->CASL = pDCTstat->DIMMCASL; /* if "manual" memclock mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1; } @@ -1013,10 +1013,10 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0; - for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i); @@ -1062,13 +1062,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, if (Trc < val) Trc = val; - /* dev density=rank size/#devs per rank */ + /* dev density = rank size/#devs per rank */ byte = mctRead_SPD(smbaddr, SPD_BANKSZ); val = ((byte >> 5) | (byte << 3)) & 0xFF; val <<= 2; - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ + byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density = 2^(rows+columns+banks) */ if (byte == 4) { val >>= 4; } else if (byte == 8) { @@ -1260,7 +1260,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i]; mctAdjustAutoCycTmg_D(); @@ -1329,7 +1329,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16; val = 0; - for (i=4;i>0;i--) { + for (i = 4; i > 0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -1385,7 +1385,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, proposedFreq = 533; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); if (word < proposedFreq) proposedFreq = word; @@ -1426,9 +1426,9 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, CL1min = 0xFF; T1min = 0xFF; - for (k=K_MAX; k >= K_MIN; k--) { + for (k = K_MAX; k >= K_MIN; k--) { for (j = J_MIN; j <= J_MAX; j++) { - if (Sys_Capability_D(pMCTstat, pDCTstat, j, k) ) { + if (Sys_Capability_D(pMCTstat, pDCTstat, j, k)) { /* 1. check to see if DIMMi is populated. 2. check if DIMMi supports CLj and Tjk */ for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { @@ -1480,7 +1480,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1); } - if ( pDCTstat->_2Tmode == 2) { + if (pDCTstat->_2Tmode == 2) { dev = pDCTstat->dev_dct; reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */ val = Get_NB32(dev, reg); @@ -1547,20 +1547,20 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->Speed == 3) { if (pDCTstat->MAdimms[dct] == 4) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ - } else if (pDCTstat->Speed == 4){ + } else if (pDCTstat->Speed == 4) { if (pDCTstat->MAdimms[dct] != 1) DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else { // FIXME: Skip for Ax versions if (pDCTstat->MAdimms[dct] == 4) { - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } else if (pDCTstat->MAdimms[dct] == 4) { if (pDCTstat->Speed == 4) { - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { DramConfigLo |= 1 << 5; /* 50 Ohms ODT */ } } @@ -1604,7 +1604,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) - if ( mctGet_NVbits(NV_ECC)) + if (mctGet_NVbits(NV_ECC)) DramConfigLo |= 1 << DimmEcEn; DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); @@ -1633,7 +1633,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */ /* Check for Quadrank DIMM presence */ - if ( pDCTstat->DimmQRPresent != 0) { + if (pDCTstat->DimmQRPresent != 0) { byte = mctGet_NVbits(NV_4RANKType); if (byte == 2) DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */ @@ -1641,7 +1641,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ } - if (0) /* call back not needed mctOverrideDcqBypMax_D ) */ + if (0) /* call back not needed mctOverrideDcqBypMax_D) */ val = mctGet_NVbits(NV_BYPMAX); else val = 0x0f; // recommended setting (default) @@ -1676,7 +1676,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, 1. We will assume that MemClkDis field has been preset prior to this point. 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks ==0 */ + NV_AllMemClks <>0 AND SB_DiagClks == 0 */ /* Dram Timing Low (owns Clock Enable bits) */ @@ -1795,7 +1795,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, /* 13 Rows is smallest dev size */ byte |= Rows - 13; /* CCCBRR internal encode */ - for (dword=0; dword < 12; dword++) { + for (dword = 0; dword < 12; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -1810,7 +1810,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0; - byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ if (Banks == 8) byte -= 2; /* 3 banks - 5 */ else @@ -1881,7 +1881,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { smbaddr = Get_DIMMAddress_D(pDCTstat, i); smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1); @@ -1952,7 +1952,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, _DSpareEn = 0; - /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -1967,7 +1967,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -1981,13 +1981,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/ val = Get_NB32(dev, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/ val = Get_NB32(dev, reg); val >>= 19; @@ -2003,7 +2003,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2) + reg_off; if (_DSpareEn) { @@ -2022,7 +2022,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /* bank present but disabled?*/ - if ( pDCTstat->CSTestFail & (1 << p)) { + if (pDCTstat->CSTestFail & (1 << p)) { /* DRAM CS Base b Address Register offset */ reg = (p << 2) + 0x40 + reg_off; val = 1 << TestFail; @@ -2102,7 +2102,7 @@ static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat, byte = mctRead_SPD(DIMMi, word); /* DIMMi speed */ if (Tk < byte) { ret = 1; - } else if (byte == 0){ + } else if (byte == 0) { pDCTstat->ErrStatus |= 1<<SB_NoCycTime; ret = 1; } else { @@ -2121,12 +2121,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */ u16 i, j, k; @@ -2159,7 +2159,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, print_tx("\t DIMMPresence: smbaddr=", smbaddr); if (smbaddr) { Checksum = 0; - for (Index=0; Index < 64; Index++){ + for (Index = 0; Index < 64; Index++) { int status; status = mctRead_SPD(smbaddr, Index); if (status < 0) @@ -2250,7 +2250,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /*Check if SPD diag bit 'analysis probe installed' is set */ byte = mctRead_SPD(smbaddr, SPD_ATTRIB); - if ( byte & JED_PROBEMSK ) + if (byte & JED_PROBEMSK) pDCTstat->Status |= 1<<SB_DiagClks; byte = mctRead_SPD(smbaddr, SPD_DMBANKS); @@ -2260,7 +2260,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, byte++; /* ranks */ if (byte > 2) { /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if ( pDCTstat->DimmQRPresent == 0) { + if (pDCTstat->DimmQRPresent == 0) { MaxDimms <<= 1; } if (i < DimmSlots) { @@ -2274,7 +2274,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, if (devwidth == 16) bytex = 4; else if (devwidth == 4) - bytex=16; + bytex = 16; if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ @@ -2330,7 +2330,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } } if (pDCTstat->DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) { + if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { /* all DIMMs are ECC capable */ pDCTstat->Status |= 1<<SB_ECCDIMMs; } @@ -2418,7 +2418,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, } else { /* Configure DCT1 if unganged and enabled*/ if (!pDCTstat->GangedMode) { - if ( pDCTstat->DIMMValidDCT[1] > 0) { + if (pDCTstat->DIMMValidDCT[1] > 0) { print_t("\tmct_initDCT: DCTInit_D 1\n"); err_code = pDCTstat->ErrCode; /* save DCT0 errors */ pDCTstat->ErrCode = 0; @@ -2497,7 +2497,7 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat, if (byte != bytex) { pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); } else { - if ( mctGet_NVbits(NV_Unganged) ) + if (mctGet_NVbits(NV_Unganged)) pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) { @@ -2595,7 +2595,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98 + (i * 0x100); Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */ Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */ @@ -2615,7 +2615,7 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) print_tx("mct_SyncDCTsReady: Node ", pDCTstat->Node_ID); dev = pDCTstat->dev_dct; - if ((pDCTstat->DIMMValidDCT[0] ) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */ + if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */ do { val = Get_NB32(dev, 0x110); } while (!(val & (1 << DramEnabled))); @@ -2629,7 +2629,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!pDCTstat->GangedMode) { - if (dct == 0 ) { + if (dct == 0) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; if (pDCTstat->DIMMValidDCT[dct] == 0) pDCTstat->ErrCode = SC_StopError; @@ -2648,7 +2648,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, { u8 ret; - if ( dct == 0) { + if (dct == 0) { SPDCalcWidth_D(pMCTstat, pDCTstat); ret = mct_setMode(pMCTstat, pDCTstat); } else { @@ -2752,7 +2752,7 @@ static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat, { u8 ret; - if ( dct == 0) + if (dct == 0) ret = DIMMPresence_D(pMCTstat, pDCTstat); else ret = pDCTstat->ErrCode; @@ -2777,7 +2777,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; Set_OtherTiming(pMCTstat, pDCTstat, 0); } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) { + if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; Set_OtherTiming(pMCTstat, pDCTstat, 1); } @@ -3022,8 +3022,8 @@ static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); byte = val & 0xFF; if (byte < Smallest_0) @@ -3153,8 +3153,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x00E000E0; byte = (val >> 5) & 0xFF; @@ -3192,11 +3192,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait(dev, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -3308,14 +3308,14 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, /* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map; /* get base/limit from Node0 */ reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); - Drambase = val >> ( 16 + 3); + Drambase = val >> (16 + 3); reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); @@ -3335,7 +3335,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, val |= Dramlimit; Set_NB32(devx, reg, val); - if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) { + if (pMCTstat->GStatus & (1 << GSB_HWHole)) { reg = 0xF0; val = Get_NB32(devx, reg); val |= (1 << DramMemHoistValid); @@ -3476,7 +3476,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, val = Get_NB32_index_wait(dev, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -3652,8 +3652,8 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, u32 dev = pDCTstat->dev_dct; // FIXME: skip for Ax - if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz - for (i=0; i < 2; i++) { + if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz + for (i = 0; i < 2; i++) { reg_off = 0x100 * i; Set_NB32(dev, 0x98 + reg_off, 0x0D000030); Set_NB32(dev, 0x9C + reg_off, 0x00000806); @@ -3667,7 +3667,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax - if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz + if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz *dqs_pos = 32; } } @@ -3783,10 +3783,10 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) + * - a) Disable Compensation (F2[1, 0]9C_x08[30]) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30] ) + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 @@ -3970,7 +3970,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { mct_Wait(10000); /* Wait 50 us*/ val = Get_NB32(dev, 0x110); - if ( val & (1 << DramEnabled)) { + if (val & (1 << DramEnabled)) { /* If 50 us expires while DramEnable =0 then do the following */ val = Get_NB32(dev, 0x90 + reg_off); val &= ~(1 << Width128); /* Program Width128 = 0 */ @@ -3990,9 +3990,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { /* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index b580457..4e1a909 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -30,16 +30,16 @@ #define PT_S1 2 #define PT_GR 3 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -289,7 +289,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller*/ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -306,7 +306,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -316,15 +316,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -332,17 +332,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -352,16 +352,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -371,27 +371,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -415,9 +415,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -483,15 +483,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; // NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller) - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ // NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/ #define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/ @@ -587,73 +587,73 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -661,8 +661,8 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -674,13 +674,13 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index fd39b38..fbfe988 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -39,7 +39,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi) __asm__ volatile ( "rdtsc" : "=a" (*lo), "=d"(*hi) - ); + ); } @@ -61,7 +61,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for (i=31; i>0; i--) { + for (i = 31; i > 0; i--) { if (x & (1<<i)) { ret = i; break; @@ -78,7 +78,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -88,9 +88,9 @@ static u32 bsf(u32 x) return ret; } -#define _MFENCE asm volatile ( "mfence") +#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ( "sfence" ) +#define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") @@ -343,7 +343,7 @@ static u32 stream_to_int(u8 const *p) val = 0; - for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index 327acbc..e290333 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -187,7 +187,7 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, } while (*p != 0xFF) { - if ((MAAdimms == *(p+10)) || (*(p+10 ) == 0xFE)) { + if ((MAAdimms == *(p+10)) || (*(p+10) == 0xFE)) { if ((*p == Speed) || (*p == 0xFE)) { if (MAAload <= *(p+1)) { *AddrTmgCTL = stream_to_int((u8*)(p+2)); diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index cac2342..7e1d91a 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -96,7 +96,7 @@ static const u8 Table_ATC_ODC_D_Ax[] = { }; -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c index d5956b1..705bd91 100644 --- a/src/northbridge/amd/amdmct/mct/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c @@ -37,7 +37,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, /* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ // FIXME: Check for Cx - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ beforeInterleaveChannels_D(pDCTstatA, &enabled); if (DctSelIntLvAddr & 1) { @@ -71,7 +71,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, if (dct1_size == dct0_size) { dct1_size = 0; DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size ) { + } else if (dct1_size > dct0_size) { dct1_size = dct0_size; DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ } diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index e8d26da..4da021b 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -47,7 +47,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */ val = Get_NB32(dev, reg); - if ( val & (1<<CSEnable)) { + if (val & (1<<CSEnable)) { EnChipSels++; reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */ val = Get_NB32(dev, reg); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 67ff823..e0c7761 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -221,12 +221,12 @@ static void SetEccDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, u8 channel; u8 direction; - for (channel = 0; channel < 2; channel++){ + for (channel = 0; channel < 2; channel++) { for (direction = 0; direction < 2; direction++) { pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -251,7 +251,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); DQSDelay1 = pDCTstat->DQSDelay; - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; } else { DQSDelay = DQSDelay1 - DQSDelay0; @@ -263,7 +263,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, DQSDelay >>= 8; // /256 - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay1 - DQSDelay; } else { DQSDelay += DQSDelay1; @@ -320,7 +320,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ continue; - for ( DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { + for (DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { pDCTstat->DQSDelay = DQSWrDelay; pDCTstat->Direction = DQS_WRITEDIR; mct_SetDQSDelayAllCSR_D(pMCTstat, pDCTstat, cs_start); @@ -362,7 +362,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -383,7 +383,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -411,11 +411,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1 << SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -458,10 +458,10 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, dqsDelay_end = 32; } - /* Bitmapped status per delay setting, 0xff=All positions + /* Bitmapped status per delay setting, 0xff = All positions * passing (1= PASS). Set the entire array. */ - for (DQSDelay=0; DQSDelay<64; DQSDelay++) { + for (DQSDelay = 0; DQSDelay < 64; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xFF; } @@ -481,7 +481,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, } print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ if (pDCTstat->Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); @@ -504,7 +504,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ - tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */ + tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0 = fail, 1 = pass */ if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) { goto skipLocMiddle; @@ -538,7 +538,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) { RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -552,7 +552,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, Errors |= 1 << SB_NODQSPOS; /* no passing window */ } else { print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4); - if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)){ + if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)) { Errors |= 1 << SB_SMALLDQS; } else { u8 middle_dqs; @@ -631,7 +631,7 @@ static u8 MiddleDQS_D(u8 min, u8 max) size = max-min; if (size % 2) size++; // round up if the size isn't even. - return ( min + (size >> 1)); + return (min + (size >> 1)); } @@ -679,10 +679,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, reg_off = 0; } - if (ChipSel < MAX_CS_SUPPORTED){ + if (ChipSel < MAX_CS_SUPPORTED) { reg = 0x40 + (ChipSel << 2) + reg_off; val = Get_NB32(dev, reg); - if (val & ( 1 << 0)) + if (val & (1 << 0)) ret = 1; } @@ -775,8 +775,8 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS } bytelane = 0; /* bytelane counter */ - bitmap = 0xFF; /* bytelane test bitmap, 1=pass */ - for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ + bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ + for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); value_test = *test_buf; @@ -797,7 +797,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS if (!bitmap) break; - if (bytelane == 0){ + if (bytelane == 0) { if (pattern == 1) { //dual channel addr_lo += 8; //skip over other channel's data test_buf += 2; @@ -815,7 +815,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo) { /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0){ + if (pDCTstat->Pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { FlushDQSTestPattern_L18(addr_lo); @@ -1036,7 +1036,7 @@ static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, for (ChipSel = cs_start; ChipSel < (cs_start + 2); ChipSel++) { - if ( mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) { for (ByteLane = 0; ByteLane < 8; ByteLane++) { pDCTstat->ByteLane = ByteLane; mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -1088,9 +1088,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val &= ~0x0F; - /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { + if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; dword = Get_NB32(dev, reg); dword &= 0xfffff800; @@ -1104,7 +1104,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase; /* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 5c1dc3a..59ebd77 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -40,7 +40,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -121,10 +121,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if (pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); @@ -176,7 +176,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -239,8 +239,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if ((val & 3)==3) { /* Node has dram populated*/ - if ( isDramECCEn_D(pDCTstat)) { + if ((val & 3) == 3) { /* Node has dram populated*/ + if (isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -300,8 +300,8 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0){ + for (i = 0; i < ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0) { reg = 0x90 + i * 0x100; /* Dram Config Low */ val = Get_NB32(dev, reg); if (val & (1<<DimmEcEn)) { diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index a13d4e2..41a479b 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -31,12 +31,12 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, DramTimingLo = val; /* Dram Timing Low (owns Clock Enable bits) */ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if (mctGet_NVbits(NV_AllMemClks)==0) { + if (mctGet_NVbits(NV_AllMemClks) == 0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ if (!(pDCTstat->Status & (1<<SB_DiagClks))) { - for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if (val<8) { + if (val < 8) { if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 5e91947..deb0f8a 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -35,11 +35,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */ @@ -83,8 +83,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -115,10 +115,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -177,17 +177,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8; /* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; - val |= ( 1 << 11); /* set MTRR valid*/ + val |= (1 << 11); /* set MTRR valid*/ addr++; _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ val = curLimit; @@ -217,9 +217,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; @@ -238,7 +238,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while ( addr < 0x20C) { + while (addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 32c3199..389d56b 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -72,7 +72,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, NodesWmem++; Base &= 0xFFFF0000; /* Base[39:8] */ - if (pDCTstat->Status & (1 << SB_HWHole )) { + if (pDCTstat->Status & (1 << SB_HWHole)) { /* to get true amount of dram, * subtract out memory hole if HW dram remapping */ @@ -87,7 +87,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); if (DctSelBase) { DctSelBase <<= 8; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { DctSelBase -= HWHoleSz; } @@ -104,7 +104,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, MemSize &= 0xFFFF0000; MemSize += 0x00010000; MemSize -= Base; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { MemSize -= HWHoleSz; } if (Node == 0) { @@ -144,7 +144,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat,pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; @@ -185,7 +185,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if ( Node == 0) { + if (Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 95afebf..081e8ac 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -36,13 +36,13 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) { /* Bug#10695:One MEMCLK Bubble Writes Don't Do X4 X8 Switching Correctly * Solution: BIOS should set DRAM Timing High[Twrwr] > 00b - * ( F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B + * (F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B * FIXME: check if this is still required. */ uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (!(val & (3<<12) )) + if (!(val & (3<<12))) val |= 1<<12; } return val; @@ -69,7 +69,7 @@ void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) val |= 1<<BurstLength32; Set_NB32(dev, reg, val); - reg = 0x88 + reg_off; /* cx=Dram Timing Lo */ + reg = 0x88 + reg_off; /* cx = Dram Timing Lo */ val = Get_NB32(dev, reg); val |= 0x000F0000; /* Trc = 0Fh */ Set_NB32(dev, reg, val); @@ -89,7 +89,7 @@ void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat, * NOTE -- this has been documented with a note at the end of this * section in the BKDG (although, admittedly, the note does not really * stand out). - * Silicon Status: Fixed in Rev B ( confirm) + * Silicon Status: Fixed in Rev B (confirm) * FIXME: check this. */ @@ -149,14 +149,14 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; index = 0; - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { index_reg = 0x98 + 0x100 * Channel; val = Get_NB32_index_wait(dev, index_reg, 0x0d004007); val |= 0x3ff; Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val); } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { if (pDCTstat->GangedMode && Channel) break; reg_off = 0x100 * Channel; @@ -167,11 +167,11 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg_off = 0x100 * Channel; val = 0; index_reg = 0x98 + reg_off; - for ( index = 0x30; index < (0x45 + 1); index++) { + for (index = 0x30; index < (0x45 + 1); index++) { Set_NB32_index_wait(dev, index_reg, index, val); } } @@ -265,7 +265,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) print_tx("NB COF:", valy >> NbDid); val = valy/valx; - if ((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ + if ((val == 3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ ret = 1; return ret; @@ -296,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) } dev = pDCTstat->dev_dct; index = 0x0D00E001; - for (ch=ch_start; ch<ch_end; ch++) { + for (ch = ch_start; ch < ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); val &= ~(0xf0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 510cf0d..a87cea8 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -86,7 +86,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -161,7 +161,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_t("TrainRcvrEn: 1\n"); cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -261,7 +261,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { pDCTstat->DqsRcvEn_Pass = 0; } else { - pDCTstat->DqsRcvEn_Pass=0xFF; + pDCTstat->DqsRcvEn_Pass = 0xFF; } pDCTstat->DqsRcvEn_Saved = 0; @@ -446,7 +446,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -456,7 +456,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -472,10 +472,10 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for (Receiver = 0; Receiver<8; Receiver+=2) { + for (Receiver = 0; Receiver < 8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, "%02x ", val); } @@ -494,7 +494,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { - if (pDCTstat->DIMMValidDCT[dct] == 0 ) { + if (pDCTstat->DIMMValidDCT[dct] == 0) { return 8; } else { return 0; @@ -526,7 +526,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; } - for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78 + 0x100 * ch; val = Get_NB32(dev, reg); val &= ~(1 << DqsRcvEnTrain); @@ -562,14 +562,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } - /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -661,7 +661,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ valx = (val + 3) << 2; val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - SubTotal *= ((val & 0x1f) + 4 ) * 3; + SubTotal *= ((val & 0x1f) + 4) * 3; SubTotal /= valx; if (SubTotal % valx) { /* round up */ @@ -723,7 +723,7 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, mask_Saved &= mask_Pass; p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; } - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* cmp per byte lane */ if (mask_Pass & (1 << i)) { if (!(mask_Saved & (1 << i))) { @@ -757,7 +757,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { - if (pattern==1) { + if (pattern == 1) { test_buf = (u8 *)TestPattern1_D; } else { test_buf = (u8 *)TestPattern0_D; @@ -769,13 +769,13 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); addr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { addr += 8; /* second channel */ test_buf += 8; } print_debug_dqs_pair("\t\t\t\t\t\t test_buf = ", (u32)test_buf, " | addr_lo = ", addr, 4); - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { value = read32_fs(addr); print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4); @@ -790,7 +790,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, if (Pass == FirstPass) { /* if first pass, at least one byte lane pass - * ,then DQS_PASS=1 and will set to related reg. + * ,then DQS_PASS = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0) { result = DQS_PASS; @@ -800,7 +800,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, } else { /* if second pass, at least one byte lane fail - * ,then DQS_FAIL=1 and will set to related reg. + * ,then DQS_FAIL = 1 and will set to related reg. */ if (pDCTstat->DqsRcvEn_Pass != 0xFF) { result = DQS_FAIL; @@ -843,7 +843,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++) { InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -867,8 +867,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, // FIXME: add Cx support dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); @@ -876,14 +876,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword); } @@ -969,7 +969,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1081,5 +1081,5 @@ void mct_Wait(u32 cycles) saved = lo; do { _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles ); + } while (lo - saved < cycles); } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index e059e1e..c1b1133 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -50,7 +50,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index bd3c503..c7c92ac 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -62,7 +62,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; // print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); // print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); - for ( i=0;i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); @@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ //val += Pass1MemClkDly; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 0eb3c61..a47990a 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -149,7 +149,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); @@ -164,7 +164,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -185,7 +185,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -195,7 +195,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -213,7 +213,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; // for safe - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; @@ -247,7 +247,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8; _EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i]; @@ -292,11 +292,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp>Max) { + if (tmp > Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -382,7 +382,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4 ) * 3; + val = ((val & 0x1f) + 4) * 3; /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ valxx = val << 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 08d8d43..da2a4fe 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2625,7 +2625,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 1. BSP in Big Real Mode * 2. Stack at SS:SP, located somewhere between A000:0000 and F000:FFFF * 3. Checksummed or Valid NVRAM bits - * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs + * 4. MCG_CTL = -1, MC4_CTL_EN = 0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry * 6. All var MTRRs reset to zero * 7. State of NB_CFG.DisDatMsk set properly on all CPUs @@ -3819,7 +3819,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { SetEccDQSRcvrEn_D(pDCTstat, Channel); } @@ -3859,7 +3859,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, } } - for (Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); val &= ~(0x3ff<<22); @@ -3993,7 +3993,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(dev, reg); Set_NB32(devx, reg, val); reg += 4; - } while ( reg < 0x80); + } while (reg < 0x80); } else { break; /* stop at first absent Node */ } @@ -4015,7 +4015,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, uint32_t dword; struct DCTStatStruc *pDCTstat; - if (!mctGet_NVbits(NV_DQSTrainCTL)){ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /* FIXME: callback to wrapper: mctDoWarmResetMemClr_D */ } else { /* NV_DQSTrainCTL == 1 */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -4080,7 +4080,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Start\n", __func__); /* Ensure that a memory clear operation has completed on one node */ - if (pDCTstat->DCTSysLimit){ + if (pDCTstat->DCTSysLimit) { printk(BIOS_DEBUG, "%s: Waiting for memory clear to complete", __func__); do { dword = Get_NB32(dev, 0x110); @@ -4223,7 +4223,7 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p dword &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword); - /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x88, 0xff000000); @@ -4369,16 +4369,16 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Trc = 0; Twr = 0; Twtr = 0; - for (i=0; i < 2; i++) + for (i = 0; i < 2; i++) Etr[i] = 0; - for (i=0; i < 4; i++) + for (i = 0; i < 4; i++) Trfc[i] = 0; Tfaw = 0; - for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */ + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB = Dividend/Divisor */ MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4); MTB16x /= val; /* transfer to MTB*16 */ @@ -4574,7 +4574,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, pDCTstat->Twtr = val; /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) pDCTstat->Trfc[i] = Trfc[i]; /* Tfaw */ @@ -4647,7 +4647,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */ /* Trfc0-Trfc3 */ - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) if (pDCTstat->Trfc[i] == 0x0) pDCTstat->Trfc[i] = 0x1; dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ @@ -4714,7 +4714,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, DramTimingHi |= val<<16; val = 0; - for (i=4;i>0;i--) { + for (i = 4; i > 0; i--) { val <<= 3; val |= Trfc[i-1]; } @@ -4850,7 +4850,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, proposedFreq = 800; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ - if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { + if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1); if (word < proposedFreq) proposedFreq = word; @@ -4984,7 +4984,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, determine the desired CAS Latency. If tCKproposed is not a standard JEDEC value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the next lower standard tCK value for calculating CLdesired. - CLdesired = ceiling ( tAAmin(all) / tCKproposed ) + CLdesired = ceiling (tAAmin(all) / tCKproposed) where tAAmin is defined in Byte 16. The ceiling function requires that the quotient be rounded up always. */ CLdesired = tAAmin16x / tCKproposed16x; @@ -5163,7 +5163,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) - if ( mctGet_NVbits(NV_ECC)) + if (mctGet_NVbits(NV_ECC)) DramConfigLo |= 1 << DimmEcEn; DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct); @@ -5210,7 +5210,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */ } - if (0) /* call back not needed mctOverrideDcqBypMax_D ) */ + if (0) /* call back not needed mctOverrideDcqBypMax_D) */ val = mctGet_NVbits(NV_BYPMAX); else val = 0x0f; /* recommended setting (default) */ @@ -5224,7 +5224,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, 1. We will assume that MemClkDis field has been preset prior to this point. 2. We will only set MemClkDis bits if a DIMM is NOT present AND if: - NV_AllMemClks <>0 AND SB_DiagClks ==0 */ + NV_AllMemClks <>0 AND SB_DiagClks == 0 */ /* Dram Timing Low (owns Clock Enable bits) */ DramTimingLo = Get_NB32_DCT(dev, dct, 0x88); @@ -5253,7 +5253,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dword = 0; byte = 0xFF; while (dword < MAX_CS_SUPPORTED) { - if (pDCTstat->CSPresent & (1<<dword)){ + if (pDCTstat->CSPresent & (1<<dword)) { /* re-enable clocks for the enabled CS */ val = p[dword]; byte &= ~val; @@ -5330,11 +5330,11 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValid & (1<<byte)) { byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; - Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */ - Cols = byte & 0x7; /* Cols:0b=9-bit,... */ + Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */ + Cols = byte & 0x7; /* Cols:0b = 9-bit,... */ byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density]; - Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */ + Banks = (byte >> 4) & 7; /* Banks:0b = 3-bit,... */ byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization]; Ranks = ((byte >> 3) & 7) + 1; @@ -5351,7 +5351,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, byte |= Rows << 3; /* RRRBCC internal encode */ - for (dword=0; dword < 13; dword++) { + for (dword = 0; dword < 13; dword++) { if (byte == Tab_BankAddr[dword]) break; } @@ -5367,7 +5367,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, or 2pow(rows+cols+banks-5)-1*/ csMask = 0; - byte = Rows + Cols; /* cl=rows+cols*/ + byte = Rows + Cols; /* cl = rows+cols*/ byte += 21; /* row:12+col:9 */ byte -= 2; /* 3 banks - 5 */ @@ -5435,7 +5435,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat, /* Check Symmetry of Channel A and Channel B DIMMs (must be matched for 128-bit mode).*/ - for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) { if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) { byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; @@ -5498,7 +5498,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, _DSpareEn = 0; - /* CS Sparing 1=enabled, 0=disabled */ + /* CS Sparing 1 = enabled, 0 = disabled */ if (mctGet_NVbits(NV_CS_SpareCTL) & 1) { if (MCT_DIMM_SPARE_NO_WARM) { /* Do no warm-reset DIMM spare */ @@ -5513,7 +5513,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, pDCTstat->ErrStatus |= 1 << SB_SpareDis; } } else { - if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */ + if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */ word = pDCTstat->CSPresent; val = bsf(word); word &= ~(1 << val); @@ -5527,13 +5527,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } nxtcsBase = 0; /* Next available cs base ADDR[39:8] */ - for (p=0; p < MAX_DIMMS_SUPPORTED; p++) { + for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) { BiggestBank = 0; for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */ if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */ reg = 0x40 + (q << 2); /* Base[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); - if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ + if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */ reg = 0x60 + (q << 1); /*Mask[q] reg.*/ val = Get_NB32_DCT(dev, dct, reg); val >>= 19; @@ -5549,7 +5549,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /*if bank present */ } /* while q */ if (BiggestBank !=0) { - curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/ + curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/ /* DRAM CS Base b Address Register offset */ reg = 0x40 + (b << 2); if (_DSpareEn) { @@ -5579,7 +5579,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, } /* bank present but disabled?*/ - if ( pDCTstat->CSTestFail & (1 << p)) { + if (pDCTstat->CSTestFail & (1 << p)) { /* DRAM CS Base b Address Register offset */ reg = (p << 2) + 0x40; val = 1 << TestFail; @@ -5611,12 +5611,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* Check DIMMs present, verify checksum, flag SDRAM type, * build population indicator bitmaps, and preload bus loading * of DIMMs into DCTStatStruc. - * MAAload=number of devices on the "A" bus. - * MABload=number of devices on the "B" bus. - * MAAdimms=number of DIMMs on the "A" bus slots. - * MABdimms=number of DIMMs on the "B" bus slots. - * DATAAload=number of ranks on the "A" bus slots. - * DATABload=number of ranks on the "B" bus slots. + * MAAload = number of devices on the "A" bus. + * MABload = number of devices on the "B" bus. + * MAAdimms = number of DIMMs on the "A" bus slots. + * MABdimms = number of DIMMs on the "B" bus slots. + * DATAAload = number of ranks on the "A" bus slots. + * DATABload = number of ranks on the "B" bus slots. */ u16 i, j, k; u8 smbaddr; @@ -5747,7 +5747,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, byte &= 7; if (byte == 3) { /* 4ranks */ /* if any DIMMs are QR, we have to make two passes through DIMMs*/ - if ( pDCTstat->DimmQRPresent == 0) { + if (pDCTstat->DimmQRPresent == 0) { MaxDimms <<= 1; } if (i < DimmSlots) { @@ -5767,7 +5767,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, else if (devwidth == 2) bytex = 4; - byte++; /* al+1=rank# */ + byte++; /* al+1 = rank# */ if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ @@ -5847,7 +5847,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, } } if (pDCTstat->DimmECCPresent != 0) { - if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) { + if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { /* all DIMMs are ECC capable */ pDCTstat->Status |= 1<<SB_ECCDIMMs; } @@ -5961,7 +5961,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, val &= ~(1 << ParEn); Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val); - /* To maximize power savings when DisDramInterface=1b, + /* To maximize power savings when DisDramInterface = 1b, * all of the MemClkDis bits should also be set. */ Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x88, 0xff000000); @@ -6119,7 +6119,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, i_start = dct; i_end = dct + 1; } - for (i=i_start; i<i_end; i++) { + for (i = i_start; i < i_end; i++) { index_reg = 0x98; Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */ Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */ @@ -6152,7 +6152,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { if (!pDCTstat->GangedMode) { - if (dct == 0 ) { + if (dct == 0) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct]; if (pDCTstat->DIMMValidDCT[dct] == 0) pDCTstat->ErrCode = SC_StopError; @@ -6172,7 +6172,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, u8 ret; u32 val; - if ( dct == 0) { + if (dct == 0) { SPDCalcWidth_D(pMCTstat, pDCTstat); ret = mct_setMode(pMCTstat, pDCTstat); } else { @@ -6313,7 +6313,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0]; Set_OtherTiming(pMCTstat, pDCTstat, 0); } - if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) { + if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) { pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1]; Set_OtherTiming(pMCTstat, pDCTstat, 1); } @@ -6568,8 +6568,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat, if (index == 0x12) ecc_reg = 1; - for (i=0; i < 8; i+=2) { - if ( pDCTstat->DIMMValid & (1 << i)) { + for (i = 0; i < 8; i+=2) { + if (pDCTstat->DIMMValid & (1 << i)) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x00E000E0; byte = (val >> 5) & 0xFF; @@ -6607,11 +6607,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, Smallest = 3; Largest = 0; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); val &= 0x60606060; val >>= 5; - for (j=0; j < 4; j++) { + for (j = 0; j < 4; j++) { byte = val & 0xFF; if (byte < Smallest) Smallest = byte; @@ -6774,7 +6774,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); - /* set F3x8C[DisFastTprWr] on all DR, if L3Size=0 */ + /* set F3x8C[DisFastTprWr] on all DR, if L3Size = 0 */ if (pDCTstat->LogicalCPUID & AMD_DR_ALL) { if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) { val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C); @@ -6948,7 +6948,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, /* Copy dram map from F1x40/44,F1x48/4c, to F1x120/124(Node0),F1x120/124(Node1),...*/ - for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map; @@ -6975,7 +6975,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, val |= Dramlimit; Set_NB32(devx, reg, val); - if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) { + if (pMCTstat->GStatus & (1 << GSB_HWHole)) { reg = 0xF0; val = Get_NB32(devx, reg); val |= (1 << DramMemHoistValid); @@ -7328,7 +7328,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, } else { dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00); dword = 0; - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { switch (i) { case 0: case 4: @@ -7668,7 +7668,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, dword = 0x00000800; else dword = 0x00000000; - for (i=0; i < 2; i++) { + for (i = 0; i < 2; i++) { Set_NB32_DCT(dev, i, 0x98, 0x0D000030); Set_NB32_DCT(dev, i, 0x9C, dword); Set_NB32_DCT(dev, i, 0x98, 0x4D040F30); @@ -7958,11 +7958,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= mct_DramTermDyn_RDimm(pMCTstat, pDCTstat, byte); } - /* Qoff=0, output buffers enabled */ + /* Qoff = 0, output buffers enabled */ /* Tcwl */ DramMRS |= (pDCTstat->Speed - 4) << 20; - /* ASR=1, auto self refresh */ - /* SRT=0 */ + /* ASR = 1, auto self refresh */ + /* SRT = 0 */ DramMRS |= 1 << 18; } @@ -7989,10 +7989,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) + * - a) Disable Compensation (F2[1, 0]9C_x08[30]) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30] ) + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 @@ -8275,9 +8275,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { /* ========================================================== * 6-bit Bank Addressing Table - * RR=rows-13 binary - * B=Banks-2 binary - * CCC=Columns-9 binary + * RR = rows-13 binary + * B = Banks-2 binary + * CCC = Columns-9 binary * ========================================================== * DCT CCCBRR Rows Banks Columns 64-bit CS Size * Encoding @@ -8311,7 +8311,7 @@ uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm) for (Index = 0; Index < byte_use; Index ++) { byte = pDCTstat->spd_data.spd_bytes[dimm][Index]; CRC ^= byte << 8; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { if (CRC & 0x8000) { CRC <<= 1; CRC ^= 0x1021; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e1d9da5..c42e452 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -33,16 +33,16 @@ #define PT_C3 5 #define PT_FM2 6 -#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/ -#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/ -#define K_MIN 1 /* k loop constraint. 1=200 MHz*/ -#define K_MAX 5 /* k loop constraint. 5=533 MHz*/ -#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/ -#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/ - -#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/ +#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/ +#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/ +#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/ +#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/ +#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/ +#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/ + +#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/ /* memory initialization (ecc and check-bits).*/ - /* 1=40 ns/64 bytes.*/ + /* 1 = 40 ns/64 bytes.*/ #define FirstPass 1 /* First pass through RcvEn training*/ #define SecondPass 2 /* Second pass through Rcven training*/ @@ -336,7 +336,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ - uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */ uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error @@ -353,7 +353,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* SPD address of..MB2_CS_L[0,1]*/ /* SPD address of..MA3_CS_L[0,1]*/ /* SPD address of..MB3_CS_L[0,1]*/ - u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present. + u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present. DIMM# Select Signal 0 MA0_CS_L[0,1] 1 MB0_CS_L[0,1] @@ -363,15 +363,15 @@ struct DCTStatStruc { /* A per Node structure*/ 5 MB2_CS_L[0,1] 6 MA3_CS_L[0,1] 7 MB3_CS_L[0,1]*/ - u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/ - u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */ - u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/ - u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/ - u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/ - u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/ - u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/ - u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/ - u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/ + u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/ + u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */ + u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/ + u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/ + u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/ + u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/ + u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/ + u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/ + u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/ u8 MAload[2]; /* Number of devices loading MAA bus*/ /* Number of devices loading MAB bus*/ u8 MAdimms[2]; /*Number of DIMMs loading CH A*/ @@ -379,17 +379,17 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /*Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz - 5=533MHz*/ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz + 5 = 533MHz*/ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -399,16 +399,16 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/ u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/ u8 Speed; /* Bus Speed (to set Controller) - 1=200MHz - 2=266MHz - 3=333MHz - 4=400MHz */ + 1 = 200MHz + 2 = 266MHz + 3 = 333MHz + 4 = 400MHz */ u8 CASL; /* CAS latency DCT setting - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0 = 2.0 + 1 = 3.0 + 2 = 4.0 + 3 = 5.0 + 4 = 6.0 */ u8 Trcd; /* DCT Trcd (busclocks) */ u8 Trp; /* DCT Trp (busclocks) */ u8 Trtp; /* DCT Trtp (busclocks) */ @@ -418,27 +418,27 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Trrd; /* DCT Trrd (busclocks) */ u8 Twtr; /* DCT Twtr (busclocks) */ u8 Trfc[4]; /* DCT Logical DIMM0 Trfc - 0=75ns (for 256Mb devs) - 1=105ns (for 512Mb devs) - 2=127.5ns (for 1Gb devs) - 3=195ns (for 2Gb devs) - 4=327.5ns (for 4Gb devs) */ + 0 = 75ns (for 256Mb devs) + 1 = 105ns (for 512Mb devs) + 2 = 127.5ns (for 1Gb devs) + 3 = 195ns (for 2Gb devs) + 4 = 327.5ns (for 4Gb devs) */ /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */ /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */ - u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */ - u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */ + u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */ + u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */ u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */ u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */ u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */ u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800) */ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800) */ u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode) - 1=1T - 2=2T */ + 1 = 1T + 2 = 2T */ u8 TrwtTO; /* DCT TrwtTO (busclocks)*/ u8 Twrrd; /* DCT Twrrd (busclocks)*/ u8 Twrwr; /* DCT Twrwr (busclocks)*/ @@ -462,9 +462,9 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB Byte 0-7 Read DQS Delay */ u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/ u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/ - u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/ + u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/ u8 ByteLane; /* Current Byte Lane (0..7)*/ - u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/ + u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/ u8 Pattern; /* Current pattern*/ u8 DQSDelay; /* Current DQS delay value*/ u32 TrainErrors; /* Current Training Errors*/ @@ -545,15 +545,15 @@ struct DCTStatStruc { /* A per Node structure*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */ - /* 1=200MHz */ - /* 2=266MHz */ - /* 3=333MHz */ + /* 1 = 200MHz */ + /* 2 = 266MHz */ + /* 3 = 333MHz */ /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */ - /* 0=2.0 */ - /* 1=3.0 */ - /* 2=4.0 */ - /* 3=5.0 */ - /* 4=6.0 */ + /* 0 = 2.0 */ + /* 1 = 3.0 */ + /* 2 = 4.0 */ + /* 3 = 5.0 */ + /* 4 = 6.0 */ u8 TrwtWB; u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/ u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/ @@ -852,7 +852,7 @@ struct amd_s3_persistent_data { #define SB_SWNodeHole 8 /* Remapping of Node Base on this Node to create a gap.*/ #define SB_HWHole 9 /* Memory Hole created on this Node using HW remapping.*/ #define SB_Over400MHz 10 /* DCT freq >= 400MHz flag*/ -#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/ +#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/ #define SB_DQSRcvLimit 12 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/ #define SB_ExtConfig 13 /* Indicator the default setting for extend PCI configuration support*/ @@ -862,73 +862,73 @@ struct amd_s3_persistent_data { ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0 = NPT L1 + 1 = NPT M2 + 2 = NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200MHz (DDR400) - 266=266MHz (DDR533) - 333=333MHz (DDR667) - 400=400MHz (DDR800)*/ + 200 = 200MHz (DDR400) + 266 = 266MHz (DDR533) + 333 = 333MHz (DDR667) + 400 = 400MHz (DDR800)*/ #define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */ #define NV_ECC_CAP 5 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0 = Platform not capable + 1 = Platform is capable*/ #define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0 = Normal + 1 = R4 (4-Rank Registered DIMMs in AMD server configuration) + 2 = S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4 = 4 times bypass (normal for non-UMA systems) + 7 = 7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2 = 8 times (normal for non-UMA systems) + 3 = 16 times (normal for UMA systems)*/ /*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0 = Auto, no user limit + 1 = Auto, user limit provided in NV_MemCkVal + 2 = Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200MHz - 1=266MHz - 2=333MHz - 3=400MHz*/ + 0 = 200MHz + 1 = 266MHz + 2 = 333MHz + 3 = 400MHz*/ /*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0 = normal + 1 = enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0 = Exit current node init if any DIMM has SPD checksum error + 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0 = skip DQS training + 1 = perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0 = disable (normal) + 1 = enable (4 beat burst when width is 64-bits)*/ /*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0 = per Channel control + 1 = per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ /*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) @@ -936,8 +936,8 @@ struct amd_s3_persistent_data { #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0 = disable + 1 = enable */ /*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -949,13 +949,13 @@ struct amd_s3_persistent_data { #define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0 = disable Spare + 1 = enable Spare */ /* Chip Select Spare Control bit 1-4: Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0 = disable + 1 = enable*/ #define NV_Unganged 62 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index a7fac8f..74fadde 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -37,7 +37,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi) __asm__ volatile ( "rdtsc" : "=a" (*lo), "=d"(*hi) - ); + ); } static inline void _cpu_id(u32 addr, u32 *val) @@ -57,7 +57,7 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for (i=31; i>0; i--) { + for (i = 31; i > 0; i--) { if (x & (1<<i)) { ret = i; break; @@ -73,7 +73,7 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for (i=0; i<32; i++) { + for (i = 0; i < 32; i++) { if (x & (1<<i)) { ret = i; break; @@ -83,9 +83,9 @@ static u32 bsf(u32 x) return ret; } -#define _MFENCE asm volatile ( "mfence") +#define _MFENCE asm volatile ("mfence") -#define _SFENCE asm volatile ( "sfence" ) +#define _SFENCE asm volatile ("sfence") /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") @@ -301,7 +301,7 @@ static u32 stream_to_int(u8 *p) val = 0; - for (i=3; i>=0; i--) { + for (i = 3; i >= 0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c index 3f01308..d6480ab 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c @@ -50,7 +50,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, * : ODC_CTL - Output Driver Compensation Control Register Value * : CMDmode - CMD mode */ -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c index 6c25f2c..30cf10e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c @@ -33,8 +33,8 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, /* call back to wrapper not needed ManualChannelInterleave_D(); */ /* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */ - /* Manually set: typ=5, otherwise typ=7. */ - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */ + /* Manually set: typ = 5, otherwise typ = 7. */ + DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */ if (DctSelIntLvAddr & 1) { DctSelIntLvAddr >>= 1; @@ -67,7 +67,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, if (dct1_size == dct0_size) { dct1_size = 0; DctSelHi = 0x04; /* DctSelHiRngEn = 0 */ - } else if (dct1_size > dct0_size ) { + } else if (dct1_size > dct0_size) { dct1_size = dct0_size; DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 3f56765..e42a127 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -45,7 +45,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); - if ( val & (1<<CSEnable)) { + if (val & (1<<CSEnable)) { EnChipSels++; reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */ val = Get_NB32_DCT(dev, dct, reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 06a70e6..64c53c6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -247,12 +247,12 @@ static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, u8 channel; u8 direction; - for (channel = 0; channel < 2; channel++){ + for (channel = 0; channel < 2; channel++) { for (direction = 0; direction < 2; direction++) { pDCTstat->Channel = channel; /* Channel A or B */ pDCTstat->Direction = direction; /* Read or write */ CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel); - print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2); pDCTstat->ByteLane = 8; StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel); @@ -294,7 +294,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); DQSDelay1 = pDCTstat->DQSDelay; - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; } else { DQSDelay = DQSDelay1 - DQSDelay0; @@ -306,7 +306,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, DQSDelay >>= 8; /* 256 */ - if (DQSDelay0>DQSDelay1) { + if (DQSDelay0 > DQSDelay1) { DQSDelay = DQSDelay1 - DQSDelay; } else { DQSDelay += DQSDelay1; @@ -493,7 +493,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, } print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4); - SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ + SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */ print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2); @@ -556,7 +556,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D(); /* Read and compare pattern */ - bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ /* If all lanes have already failed testing bypass remaining re-read attempt(s) */ if (bytelane_test_results == 0x0) @@ -650,7 +650,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, ResetTargetWTIO_D(); /* Read and compare pattern from the base test address */ - bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */ + bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */ /* Store any lanes that passed testing for later use */ for (lane = 0; lane < 8; lane++) @@ -661,7 +661,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, if ((!dual_rank) || (dual_rank && (Receiver & 0x1))) { #ifdef PRINT_PASS_FAIL_BITMAPS - for (iter = 0; iter < 64; iter++) { + for (iter = 0; iter < 64; iter++) { if (dqs_read_results_array[0][lane][iter]) printk(BIOS_DEBUG, "+"); else @@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -834,7 +834,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1583,7 +1583,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1843,7 +1843,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD); p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { val = p[i]; printk(BIOS_DEBUG, " %02x", val); } @@ -1863,7 +1863,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1890,11 +1890,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); if (pDCTstat->Status & (1<<SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ - for (i=0; i<16*18; i++) + for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; } else { pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */ - for (i=0; i<16*9; i++) + for (i = 0; i < 16*9; i++) buf[i] = TestPatternJD1a_D[i]; } pDCTstat->PtrPatternBufA = (u32)buf; @@ -1966,10 +1966,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat, else dct = 0; - if (ChipSel < MAX_CS_SUPPORTED){ + if (ChipSel < MAX_CS_SUPPORTED) { reg = 0x40 + (ChipSel << 2); val = Get_NB32_DCT(dev, dct, reg); - if (val & ( 1 << 0)) + if (val & (1 << 0)) ret = 1; } @@ -2058,7 +2058,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat } bytelane = 0; /* bytelane counter */ - bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */ + bitmap = 0xFFFF; /* bytelane test bitmap, 1 = pass */ MEn1Results = 0xFFFF; BeatCnt = 0; for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ @@ -2102,7 +2102,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat if (!bitmap) break; - if (bytelane == 0){ + if (bytelane == 0) { BeatCnt += 4; if (!(pDCTstat->Status & (1 << SB_128bitmode))) { if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */ @@ -2132,7 +2132,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat, u32 addr_lo) { /* Flush functions in mct_gcc.h */ - if (pDCTstat->Pattern == 0){ + if (pDCTstat->Pattern == 0) { FlushDQSTestPattern_L9(addr_lo); } else { FlushDQSTestPattern_L18(addr_lo); @@ -2349,9 +2349,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val &= ~0xe007c01f; - /* unganged mode DCT0+DCT1, sys addr of DCT1=node + /* unganged mode DCT0+DCT1, sys addr of DCT1 = node * base+DctSelBaseAddr+local ca base*/ - if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) { + if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) { reg = 0x110; dword = Get_NB32(dev, reg); dword &= 0xfffff800; @@ -2365,7 +2365,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, val += dword; } } else { - /* sys addr=node base+local cs base */ + /* sys addr = node base+local cs base */ val += pDCTstat->DCTSysBase; /* New stuff */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 5d31849..16cebed 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -36,7 +36,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * * Conditions for setting background scrubber. * 1. node is present - * 2. node has dram functioning (WE=RE=1) + * 2. node has dram functioning (WE = RE = 1) * 3. all eccdimms (or bit 17 of offset 90,fn 2) * 4. no chip-select gap exists * @@ -152,10 +152,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if (pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); @@ -210,7 +210,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if ((val & 3)==3) { /* Node has dram populated */ + if ((val & 3) == 3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -325,8 +325,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if ((val & 3)==3) { /* Node has dram populated*/ - if ( isDramECCEn_D(pDCTstat)) { + if ((val & 3) == 3) { /* Node has dram populated*/ + if (isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -353,8 +353,8 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) } else { ch_end = 2; } - for (i=0; i<ch_end; i++) { - if (pDCTstat->DIMMValidDCT[i] > 0){ + for (i = 0; i < ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0) { reg = 0x90; /* Dram Config Low */ val = Get_NB32_DCT(dev, i, reg); if (val & (1<<DimmEcEn)) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 8ed2bef..558b3e3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -34,11 +34,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Set temporary top of memory from Node structure data. * Adjust temp top of memory down to accommodate 32-bit IO space. - * Bottom40bIO=top of memory, right justified 8 bits + * Bottom40bIO = top of memory, right justified 8 bits * (defines dram versus IO space type) - * Bottom32bIO=sub 4GB top of memory, right justified 8 bits + * Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, + * Cache32bTOP = sub 4GB top of WB cacheable memory, * right justified 8 bits */ @@ -82,8 +82,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ addr = 0x204; /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ - /* Limit=TOP_MEM|TOM2*/ - /* Base=0*/ + /* Limit = TOP_MEM|TOM2*/ + /* Base = 0*/ printk(BIOS_DEBUG, "\t CPUMemTyping: Cache32bTOP:%x\n", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); /* Base */ @@ -112,10 +112,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En=1 */ + lo |= (1<<21); /* MtrrTom2En = 1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En=0 */ + lo &= ~(1<<21); /* MtrrTom2En = 0 */ lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); @@ -146,7 +146,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path - * to maximize MTRR usage efficiency. Base=0 is a special case where we + * to maximize MTRR usage efficiency. Base = 0 is a special case where we * start with the descending path. Correct Mask for region is * 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1 */ @@ -172,17 +172,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curSize = valx; valx += curBase; } - curLimit = valx; /*eax=curBase, edx=curLimit*/ + curLimit = valx; /*eax = curBase, edx = curLimit*/ valx = val>>24; val <<= 8; /* now program the MTRR */ val |= MtrrType; /* set cache type (UC or WB)*/ _WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/ - val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/ + val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/ valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */ val <<= 8; - val |= ( 1 << 11); /* set MTRR valid*/ + val |= (1 << 11); /* set MTRR valid*/ addr++; _WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/ val = curLimit; @@ -213,9 +213,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat /*====================================================================== * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ - /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits + /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) - * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */ + * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */ Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8; @@ -234,7 +234,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while ( addr < 0x20C) { + while (addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index 9a769ad..bf84171 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -68,7 +68,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, NodesWmem++; Base &= 0xFFFF0000; /* Base[39:8] */ - if (pDCTstat->Status & (1 << SB_HWHole )) { + if (pDCTstat->Status & (1 << SB_HWHole)) { /* to get true amount of dram, * subtract out memory hole if HW dram remapping */ @@ -83,7 +83,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); if (DctSelBase) { DctSelBase <<= 8; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { DctSelBase -= HWHoleSz; } @@ -100,7 +100,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, MemSize &= 0xFFFF0000; MemSize += 0x00010000; MemSize -= Base; - if ( pDCTstat->Status & (1 << SB_HWHole)) { + if (pDCTstat->Status & (1 << SB_HWHole)) { MemSize -= HWHoleSz; } if (Node == 0) { @@ -139,7 +139,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, if (DoIntlv) { MCTMemClr_D(pMCTstat, pDCTstatA); /* Program Interleaving enabled on Node 0 map only.*/ - MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */ + MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */ Dct0MemSize <<= bsf(Nodes); MemSize0 += HWHoleSz; Base = ((Nodes - 1) << 8) | 3; @@ -180,7 +180,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if ( Node == 0) { + if (Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 951a712..ac24c6d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -336,14 +336,14 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val); if (is_fam15h()) { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); if ((cw == 2) || (cw == 8) || (cw == 10)) precise_ndelay_fam15(pMCTstat, 6000); } } else { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { mct_Wait(1600); val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 670d640..18af172 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -912,7 +912,7 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat, /* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */ if (Get_NB32_DCT(dev, dct, 0x94) & (1 << RDqsEn)) { u8 bit; - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ bit = (ret >> 21) << 1; if ((dct & 1) != 0) bit ++; @@ -1063,7 +1063,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) printk(BIOS_DEBUG, "%s: Start\n", __func__); /*1.Program MrsAddress[10]=1 - 2.Set SendZQCmd=1 + 2.Set SendZQCmd = 1 */ dword = Get_NB32_DCT(dev, dct, 0x7C); dword &= ~0xFFFFFF; @@ -1071,7 +1071,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) dword |= 1 << SendZQCmd; Set_NB32_DCT(dev, dct, 0x7C, dword); - /* Wait for SendZQCmd=0 */ + /* Wait for SendZQCmd = 0 */ do { dword = Get_NB32_DCT(dev, dct, 0x7C); } while (dword & (1 << SendZQCmd)); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 8024179..345e630 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -76,7 +76,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for (i=0;i<16;i++) { + for (i = 0; i < 16; i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -560,7 +560,7 @@ static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDC SetUpperFSbase(testaddr); testaddr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { testaddr += 8; /* second channel */ } @@ -636,7 +636,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -986,7 +986,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ wrmsr(HWCR, msr); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -996,7 +996,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1013,10 +1013,10 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1246,7 +1246,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1500,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1510,7 +1510,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1527,10 +1527,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; - for (i=0;i<8; i++) { + for (i = 0; i < 8; i++) { valDTD = p[i]; printk(BIOS_DEBUG, " %03x", valDTD); } @@ -1604,7 +1604,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, ch_end = 2; cr4 = read_cr4(); - if (cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1720,7 +1720,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1730,7 +1730,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1745,7 +1745,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { - if (pDCTstat->DIMMValidDCT[dct] == 0 ) { + if (pDCTstat->DIMMValidDCT[dct] == 0) { return 8; } else { return 0; @@ -1766,7 +1766,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat) ch_end = 2; } - for (ch=0; ch<ch_end; ch++) { + for (ch = 0; ch < ch_end; ch++) { reg = 0x78; val = Get_NB32_DCT(dev, ch, reg); val &= ~(1 << DqsRcvEnTrain); @@ -1800,14 +1800,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, } /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; } - /* if flag=0, set DqsRcvEn value to reg. */ + /* if flag = 0, set DqsRcvEn value to reg. */ /* get the register index from table */ index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ @@ -1852,7 +1852,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); if ((package_type == PT_L1) /* Socket F (1207) */ || (package_type == PT_M2) /* Socket AM3 */ - || (package_type == PT_S1)) { /* Socket S1g<x> */ + || (package_type == PT_S1)) { /* Socket S1g < x> */ cpu_val_n = 10; cpu_val_p = 11; } else { @@ -1950,7 +1950,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for (i=0;i<2; i++){ + for (i = 0; i < 2; i++) { InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1972,8 +1972,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* FIXME: add Cx support */ dword = 0x00000000; - for (i=1; i<=3; i++) { - for (j=0; j<dn; j++) + for (i = 1; i <= 3; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); @@ -1981,14 +1981,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for (i=5; i<=6; i++) { - for (j=0; j<dn; j++) + for (i = 5; i <= 6; i++) { + for (j = 0; j < dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for (j=0; j<dn; j++) + for (j = 0; j < dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword); } @@ -2087,7 +2087,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -2427,5 +2427,5 @@ void mct_Wait(u32 cycles) saved = lo; do { _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles ); + } while (lo - saved < cycles); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index d535735..30cf19b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -49,7 +49,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for (i=0; i < 8; i++) { + for (i = 0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 2f4d4da..7f67824 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -58,7 +58,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 bn; bn = 8; - for ( i=0;i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; if (val > max) { @@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ /* val += Pass1MemClkDly; */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 15eb67e..b35e79e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -144,7 +144,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); @@ -159,7 +159,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -180,7 +180,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if (!_SSE2){ + if (!_SSE2) { cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } @@ -207,7 +207,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ - for (i=0; i<2; i++) + for (i = 0; i < 2; i++) pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; @@ -239,7 +239,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) addr_lo = addr<<8; _EXECFENCE; - for (i=0; i<(16*3); i++) { + for (i = 0; i<(16*3); i++) { val = read32_fs(addr_lo); val_test = test_buf[i]; @@ -284,11 +284,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; for (ch = ch_start; ch < ch_end; ch++) { - for (d=0; d<4; d++) { - for (Byte = 0; Byte<bn; Byte++) { + for (d = 0; d < 4; d++) { + for (Byte = 0; Byte < bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if (tmp>Max) { + if (tmp > Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -371,7 +371,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, valx = (val) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */ val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4); - val = ((val & 0x1f) + 4 ) * 3; + val = ((val & 0x1f) + 4) * 3; /* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */ valxx = val << 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 44ea6e8..47c5004 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -426,7 +426,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, } } - /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns */ + /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */ mct_Wait(250); if (pDCTstat->Status & (1 << SB_Registered)) { @@ -474,9 +474,9 @@ void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct=0, set */ + Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct=1, set */ + Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */ } } void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, @@ -484,8 +484,8 @@ void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat, { if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */ if (pDCTstat->MirrPresU_NumRegR & 0x55) - Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct=0, clear */ + Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */ if (pDCTstat->MirrPresU_NumRegR & 0xAA) - Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct=1, clear */ + Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */ } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 5c30bc5..cb69f60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -140,15 +140,15 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D00000C; + Addr = 0x0D00000C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -157,7 +157,7 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT Value = bitTestReset(Value, 4); /* for x8 only */ Value = bitTestReset(Value, 5); /* for hardware WL training */ AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D030F0C; + Addr = 0x4D030F0C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -453,22 +453,22 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank_count == 1) { - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ } else { if (rank == 0) - term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */ + term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */ else - term = 0x00; /* Rtt_Nom=OFF */ + term = 0x00; /* Rtt_Nom = OFF */ } } } else { if (frequency_index < 5) - term = 0x0044; /* Rtt_Nom=RZQ/6=40 Ohm */ + term = 0x0044; /* Rtt_Nom = RZQ/6 = 40 Ohm */ else - term = 0x0204; /* Rtt_Nom=RZQ/8=30 Ohm */ + term = 0x0204; /* Rtt_Nom = RZQ/8 = 30 Ohm */ } return term; @@ -482,15 +482,15 @@ static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ } else { if (rank_count == 1) - term = 0x00; /* Rtt_WR=off */ + term = 0x00; /* Rtt_WR = off */ else - term = 0x200; /* Rtt_WR=RZQ/4=60 Ohm */ + term = 0x200; /* Rtt_WR = RZQ/4 = 60 Ohm */ } } else { - term = 0x400; /* Rtt_WR=RZQ/2=120 Ohm */ + term = 0x400; /* Rtt_WR = RZQ/2 = 120 Ohm */ } return term; @@ -558,7 +558,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -618,7 +618,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; /* All ranks of the target DIMM are set to write levelization mode. */ if (wl) @@ -702,8 +702,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -720,7 +720,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -779,14 +779,14 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required * DDR3-defined function for write levelization. */ - tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */ + tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level = 0, Qoff = 0 */ /* Retrieve normal settings of the MRS control word and clear Rtt_Nom */ if (is_fam15h()) { tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff; tempW &= ~(0x0244); } else { - /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */ + /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */ tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn); if (tempW2) @@ -811,7 +811,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_Nom to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; /* Program MrsAddress[5,1]=output driver impedance control (DIC) */ if (is_fam15h()) { @@ -877,8 +877,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */ - tempW=tempW|((tempW1&0x00700000)>>17); + /* tempW = tempW|(((tempW1>>20)&0x7)<<3); */ + tempW = tempW|((tempW1&0x00700000)>>17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) tempW+=0x8; @@ -895,7 +895,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, } /* Apply Rtt_WR to the MRS control word */ - tempW=tempW|tempW1; + tempW = tempW|tempW1; tempW = swapAddrBits_wl(pDCTstat, dct, tempW); if (is_fam15h()) set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, @@ -939,7 +939,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - u8 WrLvOdt1=0; + u8 WrLvOdt1 = 0; if (is_fam15h()) { /* On Family15h processors, the value for the specific CS being targetted @@ -954,7 +954,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui cs = (dimm * 2) + rank; /* Fetch preprogammed ODT pattern from configuration registers */ - dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs>3)?0x23c:0x238)); + dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs > 3)?0x23c:0x238)); if ((cs == 7) || (cs == 3)) WrLvOdt1 = ((dword >> 24) & 0xf); else if ((cs == 6) || (cs == 2)) @@ -1045,25 +1045,25 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui } else { - /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ + /* Program WrLvOdtEn = 1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */ if (dct) { - Addl_Data_Offset=0x198; - Addl_Data_Port=0x19C; + Addl_Data_Offset = 0x198; + Addl_Data_Port = 0x19C; } else { - Addl_Data_Offset=0x98; - Addl_Data_Port=0x9C; + Addl_Data_Offset = 0x98; + Addl_Data_Port = 0x9C; } - Addr=0x0D008000; + Addr = 0x0D008000; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); Value = bitTestSet(Value, 12); AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); - Addr=0x4D088F00; + Addr = 0x4D088F00; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset, DctAccessDone, DctAccessDone)) == 0); @@ -1371,7 +1371,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 while (ByteLane < lane_count) { /* This subtract 0xC workaround might be temporary. */ - if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { + if ((pDCTData->WLPass == 2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) { tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane]; tempW -= 0xC; pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 6589a39..97cadcb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -351,12 +351,12 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x11c = pci_read_config32(dev_fn2, 0x11c); data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0); data->f3x44 = pci_read_config32(dev_fn3, 0x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i); } data->msr00000250 = rdmsr_uint64_t(0x00000250); data->msr00000258 = rdmsr_uint64_t(0x00000258); - for (i=0; i<8; i++) + for (i = 0; i < 8; i++) data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8)); data->msr000002ff = rdmsr_uint64_t(0x000002ff); data->msrc0010010 = rdmsr_uint64_t(0xc0010010); @@ -393,7 +393,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x204 = read_config32_dct(dev_fn2, node, channel, 0x204); data->f2x208 = read_config32_dct(dev_fn2, node, channel, 0x208); data->f2x20c = read_config32_dct(dev_fn2, node, channel, 0x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x210[i] = read_config32_dct_nbpstate(dev_fn2, node, channel, i, 0x210); data->f2x214 = read_config32_dct(dev_fn2, node, channel, 0x214); data->f2x218 = read_config32_dct(dev_fn2, node, channel, 0x218); @@ -407,7 +407,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fe003 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe003); data->f2x9cx0d0fe013 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_1f[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f001f | (i << 8)); data->f2x9cx0d0f201f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f201f); data->f2x9cx0d0f211f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f211f); @@ -419,11 +419,11 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc11f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc11f); data->f2x9cx0d0fc21f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc21f); data->f2x9cx0d0f4009 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f4009); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_02[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0002 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_06[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0006 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_8_0_0a[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f000a | (i << 8)); data->f2x9cx0d0f2002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2002); @@ -450,7 +450,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fc031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc031); data->f2x9cx0d0fc131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc131); data->f2x9cx0d0fc231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); @@ -463,8 +463,8 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x94 = read_config32_dct(dev_fn2, node, channel, 0x94); /* Stage 6 */ - for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx00 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x00); data->f2x9cx0a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0a); @@ -478,33 +478,33 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0fe007 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe007); /* Stage 10 */ - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx10[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x10 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx20[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x20 + i); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_3_1[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x01 + i) + (0x100 * j)); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) data->f2x9cx3_0_0_7_5[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x05 + i) + (0x100 * j)); data->f2x9cx0d = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_13[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0013 | (i << 8)); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) data->f2x9cx0d0f0_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0030 | (i << 8)); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) data->f2x9cx0d0f2_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2030 | (i << 8)); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) data->f2x9cx0d0f8_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4)); data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) data->f2x9cx40[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x40 + i); } @@ -599,28 +599,28 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste continue; /* Restore training parameters */ - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); if (IS_ENABLED(CONFIG_DIMM_DDR3)) { - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); } /* Restore MaxRdLatency */ if (is_fam15h()) { - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); } else { write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); @@ -682,7 +682,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); - for (i=0; i<16; i++) { + for (i = 0; i < 16; i++) { wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]); } wrmsr_uint64_t(0x00000250, data->msr00000250); @@ -692,7 +692,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste * destroying CAR while still executing from CAR! * For now, skip restoration... */ - // for (i=0; i<8; i++) + // for (i = 0; i < 8; i++) // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); wrmsr_uint64_t(0x000002ff, data->msr000002ff); wrmsr_uint64_t(0xc0010010, data->msrc0010010); @@ -760,7 +760,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x204, data->f2x204); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x208, data->f2x208); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x20c, data->f2x20c); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x214, data->f2x214); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x218, data->f2x218); @@ -773,7 +773,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x240, data->f2x240); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, data->f2x9cx0d0fe013); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f001f | (i << 8), data->f2x9cx0d0f0_8_0_1f[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f201f, data->f2x9cx0d0f201f); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f211f, data->f2x9cx0d0f211f); @@ -795,7 +795,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc031, data->f2x9cx0d0fc031); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc131, data->f2x9cx0d0fc131); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc231, data->f2x9cx0d0fc231); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); @@ -899,8 +899,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<9; i++) - for (j=0; j<3; j++) + for (i = 0; i < 9; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x00, data->f2x9cx00); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0a, data->f2x9cx0a); @@ -920,11 +920,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste dword |= (0x3 << 13); /* DisAutoComp, DisablePredriverCal = 1 */ write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, dword); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0006 | (i << 8), data->f2x9cx0d0f0_8_0_06[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f000a | (i << 8), data->f2x9cx0d0f0_8_0_0a[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0002 | (i << 8), (0x8000 | data->f2x9cx0d0f0_8_0_02[i])); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8006, data->f2x9cx0d0f8006); @@ -1024,25 +1024,25 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]); - for (i=0; i<4; i++) - for (j=0; j<3; j++) + for (i = 0; i < 4; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d, data->f2x9cx0d); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0013 | (i << 8), data->f2x9cx0d0f0_f_0_13[i]); - for (i=0; i<9; i++) + for (i = 0; i < 9; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0030 | (i << 8), data->f2x9cx0d0f0_f_0_30[i]); - for (i=0; i<4; i++) + for (i = 0; i < 4; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2030 | (i << 8), data->f2x9cx0d0f2_f_0_30[i]); - for (i=0; i<2; i++) - for (j=0; j<3; j++) + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f8_8_4_0[i][j]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f812f, data->f2x9cx0d0f812f); } @@ -1056,9 +1056,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); - for (i=0; i<12; i++) + for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]); } } diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 92979ab..5eaff2c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -63,7 +63,7 @@ UPDATE AS NEEDED #endif #ifndef MEM_MAX_LOAD_FREQ -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ #define MEM_MAX_LOAD_FREQ 933 #define MEM_MIN_PLATFORM_FREQ_FAM10 400 #define MEM_MIN_PLATFORM_FREQ_FAM15 333 diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 143468a..d121f35 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -347,7 +347,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ uint8_t dimm; for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { @@ -473,7 +473,7 @@ static void mctHookAfterDramInit(void) { } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ static void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); @@ -481,7 +481,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32))); // is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + if (((pDCTstat->PresetmaxFreq == 1333)||(nbPstate1supported)) &&(!pDCTstat->GangedMode)) { /* DisableCf8ExtCfg */ msr.hi &= ~(3 << (51 - 32)); @@ -491,15 +491,15 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) static void vErratum414(struct DCTStatStruc *pDCTstat) { - int dct=0; + int dct = 0; for (; dct < 2 ; dct++) { int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); - int powerDown = dRAMConfigHi & (1 << PowerDownEn ); - int ddr3 = dRAMConfigHi & (1 << Ddr3Mode ); + int powerDown = dRAMConfigHi & (1 << PowerDownEn); + int ddr3 = dRAMConfigHi & (1 << Ddr3Mode); int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel); - if (powerDown && ddr3 && pchgPDModeSel ) - Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); + if (powerDown && ddr3 && pchgPDModeSel) + Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel)); } } #endif @@ -507,7 +507,7 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) { vErratum372(pDCTstatA); @@ -516,7 +516,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt #endif } -#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index c10428d..9581527 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -78,7 +78,7 @@ static void rd890_enable(device_t dev) 0, (devfn >> 3), (devfn & 0x07), dev->enabled); /* we only do this once */ - if (devfn==0) { + if (devfn == 0) { /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index f21d717..3b02016 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -35,24 +35,24 @@ struct gliutable }; struct gliutable gliu0table[] = { - {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable gliu1table[] = { - {.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ - {.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */ + {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, + {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; @@ -64,51 +64,51 @@ struct msrinit }; struct msrinit ClockGatingDefault[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* All On */ struct msrinit ClockGatingAllOn[] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}}, - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}}, + {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* Performance */ struct msrinit ClockGatingPerformance[] = { - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */ + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; /* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable[] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */ - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */ - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */ - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */ - {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */ + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */ + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */ + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */ + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */ + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */ + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */ + {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */ {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ }; @@ -422,7 +422,7 @@ static uint64_t getShadow(void) msr_t msr = { 0, 0 }; msr = rdmsr(GLIU0_P2D_SC_0); - return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; + return (((uint64_t) msr.hi) << 32) | msr.lo; } /* Set the cache RConf registers for the memory hole. diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 303d64a..0bae76d 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -88,7 +88,7 @@ static void pll_reset(void) wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); /* If the "we've already been here" flag is set, don't reconfigure the pll */ - if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) ) + if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED)) { /* we haven't configured the PLL; do it now */ /* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */ @@ -145,8 +145,8 @@ static void pll_reset(void) /* CheckPCIsync: */ /* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */ /* look up the real divider... if we get a 0 we have serious problems */ - if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % - (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) ) + if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % + (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2))) { SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET; } diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index db10138..6e66d7d 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -97,7 +97,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ printk(BIOS_DEBUG, "BEFORT CTZ\n"); dimm_size = __builtin_ctz(dimm_size); - printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n"); + printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n"); if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */ printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); @@ -130,7 +130,7 @@ static void auto_size_dimm(unsigned int dimm) * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), * so lower 3 address bits are dont_cares. So from the table above, * it's easier to see what the old code is doing: if for example, - * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K. + * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K. */ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; @@ -142,10 +142,10 @@ static void auto_size_dimm(unsigned int dimm) } printk(BIOS_DEBUG, ">11address test\n"); spd_byte -= 7; - if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */ - spd_byte = 7; /* which means >16k so set to disabled */ + if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */ + spd_byte = 7; /* which means > 16k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */ printk(BIOS_DEBUG, "RDMSR CF07\n"); msr = rdmsr(MC_CF07_DATA); @@ -230,7 +230,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */ static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0; /************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 2ba4a04..a40a628 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -91,7 +91,7 @@ struct msr_defaults { /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index c540f9a..395d925 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -106,7 +106,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ banner("BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); - banner("TEST DIMM SIZE>8"); + banner("TEST DIMM SIZE > 8"); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n"); post_code(ERROR_DENSITY_DIMM); @@ -131,12 +131,12 @@ static void auto_size_dimm(unsigned int dimm) *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) -*; *AP=autoprecharge bit +*; *AP = autoprecharge bit * *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), *;so lower 3 address bits are dont_cares.So from the table above, -*;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), -*;it adds 3 to get 10, then does 2^10=1K. Get it?*/ +*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h), +*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; banner("MAXCOLADDR"); @@ -147,10 +147,10 @@ static void auto_size_dimm(unsigned int dimm) } banner(">12address test"); spd_byte -= 7; - if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ - spd_byte = 7; /* which means >32k so set to disabled */ + if (spd_byte > 5) { /* if the value is above 6 it means > 12 address lines */ + spd_byte = 7; /* which means > 32k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */ banner("RDMSR CF07"); msr = rdmsr(MC_CF07_DATA); @@ -182,7 +182,7 @@ static void checkDDRMax(void) } /* I don't think you need this check. - if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ + if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) { printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n"); post_code(POST_PLL_MEM_FAIL); hcf(); @@ -242,7 +242,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, static u8 getcasmap(u32 dimm, u16 glspeed) { u16 dimm_speed; - u8 spd_byte, casmap, casmap_shift=0; + u8 spd_byte, casmap, casmap_shift = 0; /************************** DIMM0 **********************************/ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); @@ -730,8 +730,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* Set PMode0 Sensitivity Counter */ - msr.lo = 0; /* pmode 0=0 most aggressive */ - msr.hi = 0x200; /* pmode 1=200h */ + msr.lo = 0; /* pmode 0 = 0 most aggressive */ + msr.hi = 0x200; /* pmode 1 = 200h */ wrmsr(MC_CF_PMCTR, msr); /* Set PMode1 Up delay enable */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index 689203a..c2b3aac 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR2) { Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PMOD) { Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ @@ -60,7 +60,7 @@ Device(PBR3) { Name(_ADR, 0x00030000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS3) } /* APIC mode */ + If(PMOD) { Return(APS3) } /* APIC mode */ Return (PS3) /* PIC Mode */ } /* end _PRT */ } /* end PBR3 */ diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 889db62a..50eee51 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -35,9 +35,9 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA if ((dev == 0) || (config == 0)) return AGESA_ERROR; - if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 0f9e5f5..8a40280 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -88,10 +88,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<node_nums; i++) + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -101,10 +101,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -131,7 +131,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -160,7 +160,7 @@ static u32 amdfam15_nodeid(device_t dev) unsigned busn; busn = dev->bus->secondary; - if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)){ + if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; } else { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -403,8 +403,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate )) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) break; } else @@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -687,7 +687,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -811,11 +811,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -981,7 +981,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1059,10 +1059,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index cde5182..022b347 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -105,7 +105,7 @@ Device(PBRA) { Name(_ADR, 0x00030003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ + If(PMOD) { Return(APSA) } /* APIC mode */ Return (PSA) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -115,7 +115,7 @@ Device(PBRB) { Name(_ADR, 0x00030004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ + If(PMOD) { Return(APSB) } /* APIC mode */ Return (PSB) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ @@ -125,7 +125,7 @@ Device(PBRC) { Name(_ADR, 0x00030005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ + If(PMOD) { Return(APSC) } /* APIC mode */ Return (PSC) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index efee0a4..1ca0df9 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -134,7 +134,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -396,9 +396,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) } /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1059,10 +1058,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1081,10 +1080,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index 4e6d13e..f74b31a 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -50,7 +50,7 @@ Device(PBR4) { Name(_ADR, 0x00020001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PMOD) { Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -60,7 +60,7 @@ Device(PBR5) { Name(_ADR, 0x00020002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ + If(PMOD) { Return(APS5) } /* APIC mode */ Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -70,7 +70,7 @@ Device(PBR6) { Name(_ADR, 0x00020003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PMOD) { Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -80,7 +80,7 @@ Device(PBR7) { Name(_ADR, 0x00020004) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ + If(PMOD) { Return(APS7) } /* APIC mode */ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ @@ -90,7 +90,7 @@ Device(PBR8) { Name(_ADR, 0x00020005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ + If(PMOD) { Return(APS8) } /* APIC mode */ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6d5418a..b778da5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -83,9 +83,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -97,7 +97,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -107,10 +107,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -141,7 +141,7 @@ static void get_fx_devs(void) if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } static u32 f1_read_config32(unsigned reg) @@ -417,9 +417,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -646,7 +645,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -709,7 +708,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -841,11 +840,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -1011,7 +1010,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1090,10 +1089,10 @@ static void cpu_bus_scan(device_t dev) siblings = 0; //default one core } int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { u32 lapicid_start = 0; /* @@ -1112,10 +1111,10 @@ static void cpu_bus_scan(device_t dev) if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", i, j, apic_id); device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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Patch set updated for coreboot: northbridge/via: Add space around operators
by HAOUAS Elyes
18 Sep '16
18 Sep '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at
https://review.coreboot.org/16623
-gerrit commit 5e1a51215cd520061cd5e640f3f175fc6d9e07c8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Sep 17 18:57:12 2016 +0200 northbridge/via: Add space around operators Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/via/cn700/raminit.c | 8 +- src/northbridge/via/cn700/vga.c | 22 ++--- src/northbridge/via/cx700/agp.c | 2 +- src/northbridge/via/cx700/early_smbus.c | 2 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/cx700/raminit.c | 8 +- src/northbridge/via/cx700/vga.c | 10 +- src/northbridge/via/vx800/dev_init.c | 144 ++++++++++++++-------------- src/northbridge/via/vx800/dram_init.h | 2 +- src/northbridge/via/vx800/drdy_bl.c | 32 +++---- src/northbridge/via/vx800/freq_setting.c | 14 +-- src/northbridge/via/vx800/lpc.c | 12 +-- src/northbridge/via/vx800/uma_ram_setting.c | 8 +- src/northbridge/via/vx800/vga.c | 18 ++-- 14 files changed, 142 insertions(+), 142 deletions(-) diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index f85f68e..e4384ce 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -258,9 +258,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { u8 reg; - /* Set WR=5 */ + /* Set WR = 5 */ pci_write_config8(ctrl->d0f3, 0x61, 0xe0); - /* Set CAS=4 */ + /* Set CAS = 4 */ pci_write_config8(ctrl->d0f3, 0x62, 0xfa); /* DRAM timing-3 */ pci_write_config8(ctrl->d0f3, 0x63, 0xca); @@ -283,7 +283,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(ctrl->d0f3, 0x52, 0x33); pci_write_config8(ctrl->d0f3, 0x53, 0x3f); - /* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */ + /* Set to DDR2 SDRAM, BL = 8 (0xc8, 0xc0 for bl = 4) */ pci_write_config8(ctrl->d0f3, 0x6c, 0xc8); /* DRAM Bus Turn-Around Setting */ @@ -426,7 +426,7 @@ static void sdram_enable(device_t dev, u8 *rank_address) /* 6. Mode register set. */ PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n"); - /* Safe value for now, BL=8, WR=5, CAS=4 */ + /* Safe value for now, BL = 8, WR = 5, CAS = 4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 10b7f65..4925f2b 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -35,16 +35,16 @@ static int via_cn700_int15_handler(void) { - int res=0; + int res = 0; printk(BIOS_DEBUG, "via_cn700_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f19: break; case 0x5f18: - X86_EAX=0x5f; - X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - X86_ECX=0x060; - res=1; + X86_EAX = 0x5f; + X86_EBX = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + X86_ECX = 0x060; + res = 1; break; case 0x5f00: X86_EAX = 0x8600; @@ -55,14 +55,14 @@ static int via_cn700_int15_handler(void) res = 1; break; case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + res = 1; break; case 0x5f0f: - X86_EAX=0x860f; + X86_EAX = 0x860f; break; default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", diff --git a/src/northbridge/via/cx700/agp.c b/src/northbridge/via/cx700/agp.c index 927fa21..deada76 100644 --- a/src/northbridge/via/cx700/agp.c +++ b/src/northbridge/via/cx700/agp.c @@ -38,7 +38,7 @@ static void agp_bridge_init(device_t dev) /* * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer - * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b + * We must set RAGP8X = 1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b */ north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0); reg8 = pci_read_config8(north_dev, 0xb5); diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 6109ea0..44aa743 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -142,7 +142,7 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0xff, SMBBLKDAT); } - //for (i=0; i < len; i++) + //for (i = 0; i < len; i++) // outb(data[i],SMBBLKDAT); outb(dev, SMBXMITADD); diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 2d74316..e9e4d98 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -87,7 +87,7 @@ static void setup_pm(device_t dev) /* set ACPI irq to 9 */ pci_write_config8(dev, 0x82, 0x49); - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ pci_write_config16(dev, 0x84, 0x609a); /* SMI output level to low, 7.5us throttle clock */ diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 7d3fcbe..14a17d4 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -90,7 +90,7 @@ #define REGISTERPRESET(bus,dev,fun,bdfspec) \ { u8 j, reg; \ - for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ + for (j = 0; j < (sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \ printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \ printk(BIOS_DEBUG, "\n"); \ @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) @@ -1050,7 +1050,7 @@ static void step_2_19(const struct mem_controller *ctrl) /* Step 17. Mode register set. Wait 200us. */ printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n"); - //safe value for now, BL=8, WR=4, CAS=4 + //safe value for now, BL = 8, WR = 4, CAS = 4 do_ram_command(ctrl, RAM_COMMAND_MRS); udelay(200); diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 16f0ea0..7cb84d2 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -42,7 +42,7 @@ static int via_cx700_int15_handler(void) { - int res=0; + int res = 0; u8 mem_speed; #define MEMORY_SPEED_66MHZ (0 << 4) @@ -83,7 +83,7 @@ static int via_cx700_int15_handler(void) X86_ECX = 0x00000000; // 0 -> default // TV Layout - default X86_EDX = (X86_EDX & 0xffffff00) | 0; - res=1; + res = 1; break; case 0x5f0b: /* Get Expansion Setting */ @@ -91,12 +91,12 @@ static int via_cx700_int15_handler(void) X86_ECX = X86_ECX & 0xffffff00; // non-expansion // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion - res=1; + res = 1; break; case 0x5f0f: /* VGA Post Completion */ X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f; - res=1; + res = 1; break; case 0x5f18: @@ -113,7 +113,7 @@ static int via_cx700_int15_handler(void) X86_EBX |= memory_mapping[mem_speed]; - res=1; + res = 1; break; default: diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 8196050..7cd557a 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -38,13 +38,13 @@ static const u8 DramRegTbl[][3] = { /* Reg AND OR */ {0x50, 0x11, 0xEE}, // DDR default MA7 for DRAM init {0x51, 0x11, 0x60}, // DDR default MA3 for CHB init - {0x52, 0x00, 0x33}, // DDR use BA0=M17, BA1=M18, - {0x53, 0x00, 0x3F}, // DDR BA2=M19 + {0x52, 0x00, 0x33}, // DDR use BA0 = M17, BA1 = M18, + {0x53, 0x00, 0x3F}, // DDR BA2 = M19 - {0x54, 0x00, 0x00}, // default PR0=VR0; PR1=VR1 - {0x55, 0x00, 0x00}, // default PR2=VR2; PR3=VR3 - {0x56, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 - {0x57, 0x00, 0x00}, // default PR4=VR4; PR5=VR5 + {0x54, 0x00, 0x00}, // default PR0 = VR0; PR1 = VR1 + {0x55, 0x00, 0x00}, // default PR2 = VR2; PR3 = VR3 + {0x56, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5 + {0x57, 0x00, 0x00}, // default PR4 = VR4; PR5 = VR5 {0x60, 0x00, 0x00}, // disable fast turn-around {0x65, 0x00, 0xD9}, // AGP timer = 0XD; Host timer = 8; @@ -317,15 +317,15 @@ Purpose : Initialize DDR2 by standard sequence ===================================================================*/ // DLL: Enable Reset -static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 CL=6(Burst type=interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -334,20 +334,20 @@ static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 #define CHA_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHA_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h -// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHA_DDR2_Twr_table[5] = { CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 }; -#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +#define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) { @@ -527,14 +527,14 @@ Purpose : Initialize DDR2 of CHB by standard sequence Reference : ===================================================================*/ /*// DLL: Enable Reset -static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) -//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) +static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) +//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -543,17 +543,17 @@ static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // #define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h -// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 }; -#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) +#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) +//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) +//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) +// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) void InitDDR2CHB( DRAM_SYS_ATTR *DramAttr ) @@ -568,27 +568,27 @@ void InitDDR2CHB( // step3. //disable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data &= ~0x03; pci_write_config8(MEMCTRL, 0x69, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 4. Initialize CHB begin - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data |= 0x40; pci_write_config8(MEMCTRL, 0xd3, Data); //Step 5. NOP command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd7, Data); //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -603,25 +603,25 @@ void InitDDR2CHB( // Step 8. // all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step10. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -634,25 +634,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step12. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step13. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -665,13 +665,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step15. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -682,21 +682,21 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xda, Data); //step16. all banks precharge command enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); // step17. issue precharge all cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step18. CBR cycle enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x20; pci_write_config8(MEMCTRL, 0xd7, Data); @@ -706,7 +706,7 @@ void InitDDR2CHB( for (Idx = 0; Idx < 8; Idx++) { // issue CBR cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -716,12 +716,12 @@ void InitDDR2CHB( } //step22. MSR enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -730,11 +730,11 @@ void InitDDR2CHB( //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- //Burst Length : really offset Rx6c[1] - Data=pci_read_config8(MEMCTRL, 0x6C); + Data = pci_read_config8(MEMCTRL, 0x6C); BL = (Data & 0x02) >> 1; // CL = really offset RX62[2:0] - Data=pci_read_config8(MEMCTRL, 0x62); + Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x03; AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); @@ -744,7 +744,7 @@ void InitDDR2CHB( } //Write recovery : really offset Rx63[7:5] - Data=pci_read_config8(MEMCTRL, 0x63); + Data = pci_read_config8(MEMCTRL, 0x63); Twr = (Data & 0xE0) >> 5; AccessAddr += CHB_DDR2_Twr_table[Twr]; @@ -758,25 +758,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xFF00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1); pci_write_config8(MEMCTRL, 0xd7, Data); //step 24. issue MRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -790,25 +790,25 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step 27. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); //step 25. EMRS enable - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x18; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -821,13 +821,13 @@ void InitDDR2CHB( Data = (u8)((AccessAddr & 0xff00) >> 8); pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); //step 29. issue EMRS cycle - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; @@ -840,29 +840,29 @@ void InitDDR2CHB( Data = 0x00; pci_write_config8(MEMCTRL, 0xda, Data); - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xF9; pci_write_config8(MEMCTRL, 0xd7, Data); //step 30. normal SDRAM Mode - Data=pci_read_config8(MEMCTRL, 0xd7); + Data = pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd7, Data); - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xC7; Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); //step 31. exit the initialization mode - Data=pci_read_config8(MEMCTRL, 0xd3); + Data = pci_read_config8(MEMCTRL, 0xd3); Data &= 0xBF; pci_write_config8(MEMCTRL, 0xd3, Data); //step 32. Enable bank paging and multi page - Data=pci_read_config8(MEMCTRL, 0x69); + Data = pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; pci_write_config8(MEMCTRL, 0x69, Data); } @@ -878,7 +878,7 @@ Output : Void Purpose : Initialize DDR2 of CHC by standard sequence Reference : ===================================================================*/ -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) +// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index 6fa1877..e4e143a 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -75,7 +75,7 @@ #define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ #define SPD_SDRAM_DIMM_RANKS 5 /*Number of RANKS on this assembly */ #define SPD_SDRAM_MOD_DATA_WIDTH 6 /*Data width of this assembly */ -#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL=X) */ +#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL = X) */ #define SPD_SDRAM_TAC_X 10 /*Access time for highest CL */ #define SPD_SDRAM_CONFIG_TYPE 11 /*Non-parity , Parity or ECC */ #define SPD_SDRAM_REFRESH 12 /*Refresh rate/type */ diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 634b8a8..b9466b9 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -42,14 +42,14 @@ // a.RDRPH(MD input internal timing control) // b.CAS Latency // RDELAYMD(1bit) = bit0 of (CL + RDRPH) -// for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD=1 (bit0) -// RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0) +// for example: RDRPH = 10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD = 1 (bit0) +// RDRPH = 00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD = 0 (bit0) // 2. CPU Frequency // 3. DRAM Frequency // // According to above conditions, we create different tables: -// 1. RDELAYMD=0 : for integer CAS latency(ex. CL=3) -// 2. RDELAYMD=1 : for non-integer CAS latency(ex. CL=2.5) +// 1. RDELAYMD = 0 : for integer CAS latency(ex. CL = 3) +// 2. RDELAYMD = 1 : for non-integer CAS latency(ex. CL = 2.5) // 3. Normal performance // 4. Top performance : // Using phase0 to a case has better performance. @@ -439,7 +439,7 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - //Data=pci_read_config8(PCI_DEV(0,0,2), 0x55); + //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55); //Data = Data & (~0x20); //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data); @@ -538,17 +538,17 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) /*This routine process the ability for North Bridge side burst functionality There are 3 variances that are valid: - 1. DIMM BL=8, chipset BL=8 - 2. DIMM BL=4, chipset BL=4 - 3. DIMM BL=4, chipset BL=8 (only happened on Dual channel) + 1. DIMM BL = 8, chipset BL = 8 + 2. DIMM BL = 4, chipset BL = 4 + 3. DIMM BL = 4, chipset BL = 8 (only happened on Dual channel) Device 0 function 2 HOST:REG54[4] must be 1 when 128-bit mode. Since DIMM will be initialized in each rank individually, - 1.If all DIMM BL=4, DIMM will initialize BL=4 first, + 1.If all DIMM BL = 4, DIMM will initialize BL = 4 first, then check dual_channel flag to enable VIA_NB2HOST_REG54[4]. - 2.If all DIMM BL=8, DIMM will initialize BL=8 first, - then check dual_channel flag for re-initialize DIMM BL=4. + 2.If all DIMM BL = 8, DIMM will initialize BL = 8 first, + then check dual_channel flag for re-initialize DIMM BL = 4. also VIA_NB2HOST_REG54[4] need to be enabled. -Chipset_BL8==>chipset side can set burst length=8 +Chipset_BL8==>chipset side can set burst length = 8 two register need to set 1. Device 0 function 2 HOST:REG54[4] 2. Device 0 function 3 DRAM:REG6C[3] @@ -557,7 +557,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) { u8 Data, BL; u8 Sockets; - /*SPD byte16 bit3,2 describes the burst length supported. bit3=1 support BL=8 bit2=1 support BL=4 */ + /*SPD byte16 bit3,2 describes the burst length supported. bit3 = 1 support BL = 8 bit2 = 1 support BL = 4 */ BL = 0x0c; for (Sockets = 0; Sockets < 2; Sockets++) { if (DramAttr->DimmInfo[Sockets].bPresence) { @@ -568,9 +568,9 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) } } - /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL=4 ; =1 BL=8 */ + /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */ - if (BL & 0x08) /*All Assembly support BL=8 */ + if (BL & 0x08) /*All Assembly support BL = 8 */ BL = 0x8; /*set bit3 */ else BL = 0x00; /*clear bit3 */ @@ -582,7 +582,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) if (DramAttr->RankNumChB > 0) { BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH]; //Rx6c[1], CHB burst length - if (BL & 0x08) /*CHB support BL=8 */ + if (BL & 0x08) /*CHB support BL = 8 */ BL = 0x2; /*set bit1 */ else BL = 0x00; /*clear bit1 */ diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index dc2e1bd..6e11704 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -196,13 +196,13 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } /* cycle time value - 0x25-->2.5ns Freq=400 DDR800 - 0x30-->3.0ns Freq=333 DDR667 - 0x3D-->3.75ns Freq=266 DDR533 - 0x50-->5.0ns Freq=200 DDR400 - 0x60-->6.0ns Freq=166 DDR333 - 0x75-->7.5ns Freq=133 DDR266 - 0xA0-->10.0ns Freq=100 DDR200 + 0x25-->2.5ns Freq = 400 DDR800 + 0x30-->3.0ns Freq = 333 DDR667 + 0x3D-->3.75ns Freq = 266 DDR533 + 0x50-->5.0ns Freq = 200 DDR400 + 0x60-->6.0ns Freq = 166 DDR333 + 0x75-->7.5ns Freq = 133 DDR266 + 0xA0-->10.0ns Freq = 100 DDR200 */ if (CycTime <= 0x25) { DramAttr->DramFreq = DIMMFREQ_800; diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 00c1999..c50ec84 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -108,7 +108,7 @@ static void setup_pm(device_t dev) /* set ACPI irq to 9 */ pci_write_config8(dev, 0x82, 0x49); - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ // pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? @@ -337,13 +337,13 @@ static void southbridge_init(struct device *dev) fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) - #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. - 1 enable SLP# asserts in C3 state PMIORx26<1> =1 - 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 - 3 CLKRUN# is always asserted PMIORx26<3> =0 + #3 write 0x17 in to PMIO = VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. + 1 enable SLP# asserts in C3 state PMIORx26<1> = 1 + 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> = 1 + 3 CLKRUN# is always asserted PMIORx26<3> = 0 4 Disable PCISTP# When CLKRUN# is asserted 1: PCISTP# will not assert When CLKRUN# is asserted - PMIORx26<4> =1 + PMIORx26<4> = 1 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. VRDSLP will be active in either this bit set in C3 or LVL4 register read PMIORx26<0> =0 diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 6cfb1b9..bf59093 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -141,7 +141,7 @@ void SetUMARam(void) pci_write_config8(vga_dev, 0xb2, ByteVal); //set M1 size - //ByteVal=pci_read_config8(MEMCTRL, 0xa3); + //ByteVal = pci_read_config8(MEMCTRL, 0xa3); //ByteVal = 0x02; //pci_write_config8(MEMCTRL, 0xa3, ByteVal); @@ -216,7 +216,7 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal=inb(0x03C2); + // ByteVal = inb(0x03C2); // ByteVal |= 0x01; // outb(ByteVal,0x03C2); @@ -318,7 +318,7 @@ void SetUMARam(void) outb(0x22, 0x03c5); //start : For enable snapshot mode control - // program 3C5 for SNAPSHOT Mode control, set RxF3h=1Ah + // program 3C5 for SNAPSHOT Mode control, set RxF3h = 1Ah outb(0xf3, 0x03c4); ByteVal = inb(0x03c5); ByteVal = (ByteVal & 0xE5) | 0x1A; @@ -393,7 +393,7 @@ void SetUMARam(void) 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; - //for (i=0;i<0xc0;i++) + //for (i = 0;i < 0xc0;i++) for (i = 0; i < 0x40; i++) { outb(table3c0space[i], 0x03c0 + i); diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 61d4563..664e915 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -48,13 +48,13 @@ static int via_vx800_int15_handler(void) { - int res=0; + int res = 0; printk(BIOS_DEBUG, "via_vx800_int15_handler\n"); switch(X86_EAX & 0xffff) { case 0x5f19: - X86_EAX=0x5f; - X86_ECX=0x03; - res=1; + X86_EAX = 0x5f; + X86_ECX = 0x03; + res = 1; break; case 0x5f18: { @@ -104,11 +104,11 @@ static int via_vx800_int15_handler(void) res = 1; break; case 0x5f02: - X86_EAX=0x5f; - X86_EBX= (X86_EBX & 0xffff0000) | 2; - X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only - X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default - res=1; + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + res = 1; break; case 0x5f0f: X86_EAX = 0x005f;
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