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October 2016
- 1 participants
- 1281 discussions

New patch to review for coreboot: nb/i945/early_init.c: Add FSB800 to Egress Port Virtual Channel
by HAOUAS Elyes Oct. 31, 2016
by HAOUAS Elyes Oct. 31, 2016
Oct. 31, 2016
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17198
-gerrit
commit 87a95314ac841968b1a54a0202d10bd6545d7001
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Oct 31 18:55:04 2016 +0100
nb/i945/early_init.c: Add FSB800 to Egress Port Virtual Channel
This is based on vendor bios.
It needs test.
Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/northbridge/intel/i945/early_init.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 4373167..25a1f9c 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -233,6 +233,8 @@ static void i945_setup_egress_port(void)
reg32 &= 0xffffff00;
if ((MCHBAR32(CLKCFG) & 7) == 1)
reg32 |= 0x0d; /* 533MHz */
+ if ((MCHBAR32(CLKCFG) & 7) == 2)
+ reg32 |= 0x14; /* 800MHz */
if ((MCHBAR32(CLKCFG) & 7) == 3)
reg32 |= 0x10; /* 667MHz */
EPBAR32(0x2c) = reg32;
@@ -249,6 +251,11 @@ static void i945_setup_egress_port(void)
EPBAR32(EPVC1IST + 4) = 0x009c009c;
}
+ if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */
+ EPBAR32(EPVC1IST + 0) = 0x00f000f0;
+ EPBAR32(EPVC1IST + 4) = 0x00f000f0;
+ }
+
if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */
EPBAR32(EPVC1IST + 0) = 0x00c000c0;
EPBAR32(EPVC1IST + 4) = 0x00c000c0;
1
0

Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao Oct. 31, 2016
by Lijian Zhao Oct. 31, 2016
Oct. 31, 2016
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17181
-gerrit
commit 0032143e1add5ddb4919708a065a0b91f6872cea
Author: Lijian Zhao <lijian.zhao(a)intel.com>
Date: Fri Oct 28 11:01:09 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.
Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 60 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++
2 files changed, 63 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..c958c16
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+#define PMIO_LIMIT 0x480
+
+scope (\_SB) {
+ Device (IPC1)
+ {
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
+ Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
+ Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
+ IO (Decode16, ACPI_PMIO_BASE, PMIO_LIMIT,
+ 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store (PMC_BAR0, IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store (PMC_SRAM_BASE_0, SBAS)
+
+ Return (^RBUF)
+ }
+ }
+}
\ No newline at end of file
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 1c10f1a..e3ee1ae 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -46,5 +46,8 @@ Scope (\_SB)
/* eMMC */
#include "scs.asl"
+/* PMC IPC controller */
+#include "pmc_ipc.asl"
+
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
1
0

Oct. 31, 2016
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17177
-gerrit
commit f131c39a127f9478893df9ca4f18d7987bdcfbed
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Oct 28 09:13:52 2016 -0700
google/eve: Add new board
Add the eve board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:58666
TEST=build and boot on eve board
Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/Kconfig | 66 +++++
src/mainboard/google/eve/Kconfig.name | 2 +
src/mainboard/google/eve/Makefile.inc | 32 +++
src/mainboard/google/eve/acpi/dptf.asl | 97 +++++++
src/mainboard/google/eve/acpi/ec.asl | 14 +
src/mainboard/google/eve/acpi/superio.asl | 14 +
src/mainboard/google/eve/acpi_tables.c | 14 +
src/mainboard/google/eve/board_info.txt | 6 +
src/mainboard/google/eve/boardid.c | 27 ++
src/mainboard/google/eve/bootblock.c | 30 +++
src/mainboard/google/eve/chromeos.c | 86 +++++++
src/mainboard/google/eve/chromeos.fmd | 38 +++
src/mainboard/google/eve/devicetree.cb | 286 +++++++++++++++++++++
src/mainboard/google/eve/dsdt.asl | 70 +++++
src/mainboard/google/eve/ec.c | 43 ++++
src/mainboard/google/eve/ec.h | 73 ++++++
src/mainboard/google/eve/gpio.h | 232 +++++++++++++++++
src/mainboard/google/eve/mainboard.c | 35 +++
src/mainboard/google/eve/ramstage.c | 23 ++
src/mainboard/google/eve/romstage.c | 49 ++++
src/mainboard/google/eve/smihandler.c | 48 ++++
src/mainboard/google/eve/spd/Makefile.inc | 39 +++
src/mainboard/google/eve/spd/empty.spd.hex | 16 ++
.../eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex | 16 ++
.../google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex | 16 ++
src/mainboard/google/eve/spd/spd.c | 116 +++++++++
src/mainboard/google/eve/spd/spd.h | 35 +++
27 files changed, 1523 insertions(+)
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
new file mode 100644
index 0000000..c21d22a
--- /dev/null
+++ b/src/mainboard/google/eve/Kconfig
@@ -0,0 +1,66 @@
+if BOARD_GOOGLE_EVE
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ID_AUTO
+ select BOARD_ROMSIZE_KB_16384
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select I2C_TPM
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_USES_FSP2_0
+ select MMCONF_SUPPORT
+ select SOC_INTEL_SKYLAKE
+ select TPM2
+
+config CHROMEOS
+ select LID_SWITCH
+
+config DRIVERS_I2C_GENERIC
+ def_bool y
+
+config DRIVERS_PS2_KEYBOARD
+ default y
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x50
+
+config DRIVER_TPM_I2C_IRQ
+ int
+ default 64 # GPE0_DW2_00 (GPP_E0)
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "EVE TEST 1394"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "google/eve"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Eve"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Eve"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/google/eve/Kconfig.name b/src/mainboard/google/eve/Kconfig.name
new file mode 100644
index 0000000..88cc6d3
--- /dev/null
+++ b/src/mainboard/google/eve/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_EVE
+ bool "Eve"
diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc
new file mode 100644
index 0000000..8723e0c
--- /dev/null
+++ b/src/mainboard/google/eve/Makefile.inc
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+
+romstage-y += boardid.c
+
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += boardid.c
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl
new file mode 100644
index 0000000..95985f6
--- /dev/null
+++ b/src/mainboard/google/eve/acpi/dptf.asl
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 99
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Ambient"
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "Charger"
+#define DPTF_TSR1_PASSIVE 55
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "DRAM"
+#define DPTF_TSR2_PASSIVE 50
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_TSR3_SENSOR_ID 4
+#define DPTF_TSR3_SENSOR_NAME "eMMC"
+#define DPTF_TSR3_PASSIVE 50
+#define DPTF_TSR3_CRITICAL 75
+
+#undef DPTF_ENABLE_FAN_CONTROL
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Ambient */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Charger */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on DRAM */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
+
+ /* CPU Effect on eMMC */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on Charger (TSR1) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on eMMC (TSR3) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 2500, /* PowerLimitMinimum */
+ 4500, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 250 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 7000, /* PowerLimitMinimum */
+ 7000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/eve/acpi/ec.asl b/src/mainboard/google/eve/acpi/ec.asl
new file mode 100644
index 0000000..7782851
--- /dev/null
+++ b/src/mainboard/google/eve/acpi/ec.asl
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/google/eve/acpi/superio.asl b/src/mainboard/google/eve/acpi/superio.asl
new file mode 100644
index 0000000..7782851
--- /dev/null
+++ b/src/mainboard/google/eve/acpi/superio.asl
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/google/eve/acpi_tables.c b/src/mainboard/google/eve/acpi_tables.c
new file mode 100644
index 0000000..7782851
--- /dev/null
+++ b/src/mainboard/google/eve/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/google/eve/board_info.txt b/src/mainboard/google/eve/board_info.txt
new file mode 100644
index 0000000..0c4de9e
--- /dev/null
+++ b/src/mainboard/google/eve/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Eve
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/eve/boardid.c b/src/mainboard/google/eve/boardid.c
new file mode 100644
index 0000000..e33c094
--- /dev/null
+++ b/src/mainboard/google/eve/boardid.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t board_id(void)
+{
+ MAYBE_STATIC int id = -1;
+
+ if (id < 0)
+ id = google_chromeec_get_board_version();
+
+ return id;
+}
diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c
new file mode 100644
index 0000000..2c524f4
--- /dev/null
+++ b/src/mainboard/google/eve/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+static void early_config_gpio(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c
new file mode 100644
index 0000000..63615b3
--- /dev/null
+++ b/src/mainboard/google/eve/chromeos.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <rules.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "gpio.h"
+#include "ec.h"
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH,
+ gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_lid_switch(void)
+{
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+}
+
+int get_developer_mode_switch(void)
+{
+ /* No physical developer mode switch. */
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ /* Check if the EC has posted the keyboard recovery event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int clear_recovery_mode_switch(void)
+{
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd
new file mode 100644
index 0000000..58b6127
--- /dev/null
+++ b/src/mainboard/google/eve/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff000000 0x1000000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0xe00000 {
+ RW_SECTION_A@0x0 0x3f0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x3dffc0
+ RW_FWID_A@0x3effc0 0x40
+ }
+ RW_SECTION_B@0x3f0000 0x3f0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x3dffc0
+ RW_FWID_B@0x3effc0 0x40
+ }
+ RW_MRC_CACHE@0x7e0000 0x10000
+ RW_ELOG@0x7f0000 0x4000
+ RW_SHARED@0x7f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x7f8000 0x2000
+ RW_NVRAM@0x7fa000 0x6000
+ RW_LEGACY(CBFS)@0x800000 0x200000
+ WP_RO@0xa00000 0x400000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x3f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x300000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
new file mode 100644
index 0000000..d825acf
--- /dev/null
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -0,0 +1,286 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable" = "1"
+ register "deep_s5_enable" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "XdciEnable" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "0"
+ register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+ register "SendVrMbxCmd" = "1" # IMVP8 workaround
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root port 1.
+ register "PcieRpEnable[0]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ # RP 1 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[0]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_LONG" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_FLEX" # Camera
+ register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_LONG" # Type-C Port 2
+ register "usb2_ports[6]" = "USB2_PORT_MID" # Type-A Port
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
+
+ register "i2c[0].voltage" = "I2C_VOLTAGE_3V3" # Touchscreen
+ register "i2c[1].voltage" = "I2C_VOLTAGE_3V3" # TPM
+ register "i2c[2].voltage" = "I2C_VOLTAGE_1V8" # Touchpad
+ register "i2c[3].voltage" = "I2C_VOLTAGE_1V8" # Display
+ register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # Audio
+
+ # Enable I2C1 bus early for TPM access
+ register "i2c[1].early_init" = "1"
+ register "i2c[1].speed" = "I2C_SPEED_FAST"
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoPci,
+ [PchSerialIoIndexSpi1] = PchSerialIoPci,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ register "speed_shift_enable" = "1"
+ register "dptf_enable" = "1"
+ register "tdp_pl2_override" = "7"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ATML0001""
+ register "desc" = ""Atmel Touchscreen""
+ register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ device i2c 4b on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ATML0001""
+ register "desc" = ""Atmel Touchscreen Bootloader""
+ register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ device i2c 27 on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device i2c 50 on end
+ end
+ end # I2C #1
+ device pci 15.2 on
+ chip drivers/i2c/generic
+ register "hid" = ""ATML0000""
+ register "desc" = ""Atmel Touchpad""
+ register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "probed" = "1"
+ device i2c 4a on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ATML0000""
+ register "desc" = ""Atmel Touchpad Bootloader""
+ register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "probed" = "1"
+ device i2c 26 on end
+ end
+ end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PCI_EXP"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
new file mode 100644
index 0000000..2882d50
--- /dev/null
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ec.h"
+#include "gpio.h"
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ /* global NVS and variables */
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <soc/intel/skylake/acpi/cpu.asl>
+
+ Scope (\_SB)
+ {
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ #include "acpi/dptf.asl"
+ }
+}
diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c
new file mode 100644
index 0000000..868714a
--- /dev/null
+++ b/src/mainboard/google/eve/ec.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h
new file mode 100644
index 0000000..4cdf3db
--- /dev/null
+++ b/src/mainboard/google/eve/ec.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include "gpio.h"
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+#endif
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
new file mode 100644
index 0000000..38d725e
--- /dev/null
+++ b/src/mainboard/google/eve/gpio.h
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* Power rail control signals */
+#define EN_PP3300_DX_TOUCH GPP_C22
+#define EN_PP3300_DX_CAM GPP_D12
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */
+/* ESPI_IO0 */
+/* ESPI_IO1 */
+/* ESPI_IO2 */
+/* ESPI_IO3 */
+/* ESPI_CS# */
+/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
+/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
+/* ESPI_CLK */
+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
+/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
+/* ESPI_RESET# */
+/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
+/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
+/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */
+/* VRALERT# */ PAD_CFG_NC(GPP_B2),
+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */
+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5),
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
+/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7),
+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */ PAD_CFG_NC(GPP_B14),
+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */
+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */
+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */
+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */
+/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */
+/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */
+/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */
+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */
+/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
+
+/* SMBCLK */ PAD_CFG_NC(GPP_C0),
+/* SMBDATA */ PAD_CFG_NC(GPP_C1),
+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
+/* SML0CLK */ PAD_CFG_NC(GPP_C3),
+/* SML0DATA */ PAD_CFG_NC(GPP_C4),
+/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
+/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1DATA */ PAD_CFG_NC(GPP_C7),
+/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */
+/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */
+/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
+/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
+/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
+/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
+/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+
+/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
+/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
+/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
+/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */
+/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
+/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
+/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
+/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
+/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */
+/* SATALED# */ PAD_CFG_NC(GPP_E8),
+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */
+/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */
+/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */
+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */
+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */
+/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
+/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
+/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
+/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
+
+/* The next 4 pads are for bit banging the amplifiers, default to I2S */
+/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */
+/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */
+/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* DISPLAY */
+/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* DISPLAY */
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
+/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */
+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* RSVD */ PAD_CFG_NC(GPP_F23),
+
+/* SD_CMD */ PAD_CFG_NC(GPP_G0),
+/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
+/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
+/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
+/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
+/* SD_CD# */ PAD_CFG_NC(GPP_G5),
+/* SD_CLK */ PAD_CFG_NC(GPP_G6),
+/* SD_WP */ PAD_CFG_NC(GPP_G7),
+
+/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
+/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */
+/* RSVD */ PAD_CFG_NC(GPD7),
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */
+/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */
+/* LANPHYC */ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
+/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c
new file mode 100644
index 0000000..bffc9e6
--- /dev/null
+++ b/src/mainboard/google/eve/mainboard.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/eve/ramstage.c b/src/mainboard/google/eve/ramstage.c
new file mode 100644
index 0000000..be3676a
--- /dev/null
+++ b/src/mainboard/google/eve/ramstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
new file mode 100644
index 0000000..4ae87fd
--- /dev/null
+++ b/src/mainboard/google/eve/romstage.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <stddef.h>
+#include <fsp/soc_binding.h>
+#include <soc/romstage.h>
+#include "spd/spd.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 1, 0, 2, 3, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 3, 2, 7, 6 } };
+ /* Rcomp resistor */
+ const u16 rcomp_resistor[] = { 200, 81, 162 };
+ /* Rcomp target */
+ const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+
+ memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map));
+ memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map));
+ memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
+ memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
+
+ mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+ mem_cfg->MemorySpdDataLen = SPD_LEN;
+}
diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c
new file mode 100644
index 0000000..879131c
--- /dev/null
+++ b/src/mainboard/google/eve/smihandler.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <gpio.h>
+#include <soc/smm.h>
+#include "ec.h"
+#include "gpio.h"
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+static void mainboard_gpio_smi_sleep(u8 slp_typ)
+{
+ /* Power down the rails on any sleep type */
+ gpio_set(EN_PP3300_DX_TOUCH, 0);
+ gpio_set(EN_PP3300_DX_CAM, 0);
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ mainboard_gpio_smi_sleep(slp_typ);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc
new file mode 100644
index 0000000..f63cc8b
--- /dev/null
+++ b/src/mainboard/google/eve/spd/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google Inc.
+## Copyright (C) 2016 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = empty # 0b0000
+SPD_SOURCES += samsung_dimm_K4E8E324EB # 0b0001
+SPD_SOURCES += empty # 0b0010
+SPD_SOURCES += empty # 0b0011
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0100
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/eve/spd/empty.spd.hex b/src/mainboard/google/eve/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/google/eve/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex b/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
new file mode 100644
index 0000000..2f66a2a
--- /dev/null
+++ b/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 80 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4A 54 4D 4C 41 52 2D 4E
+55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex b/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex
new file mode 100644
index 0000000..7d72967
--- /dev/null
+++ b/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 32 34 45 42 2D 45 47 43 46 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c
new file mode 100644
index 0000000..bac5107
--- /dev/null
+++ b/src/mainboard/google/eve/spd/spd.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#include "../gpio.h"
+#include "spd.h"
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO,
+ "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+ banks, ranks, rows, cols, capmb);
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+uintptr_t mainboard_get_spd_data(void)
+{
+ char *spd_file;
+ size_t spd_file_len;
+ int spd_index;
+
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+
+ spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+ /* Load SPD data from CBFS */
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /* make sure we have at least one SPD in the file. */
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* Make sure we did not overrun the buffer */
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
+ spd_index = 1;
+ }
+
+ spd_index *= SPD_LEN;
+ mainboard_print_spd_info((uint8_t *)(spd_file + spd_index));
+
+ return (uintptr_t)(spd_file + spd_index);
+}
diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h
new file mode 100644
index 0000000..9c2b26b
--- /dev/null
+++ b/src/mainboard/google/eve/spd/spd.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+#define SPD_MANU_OFF 148
+
+uintptr_t mainboard_get_spd_data(void);
+
+#endif
1
0

Oct. 31, 2016
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16952
-gerrit
commit 013c1ac04c7c8b995cbf2ecbc84115e6a2a0d69f
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Oct 5 17:47:32 2016 +0200
drivers/intel/gma: Hook up libgfxinit
Add `libgfxinit` as another option for native graphics initialization.
For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has
to be called by the respective northbridge/soc code.
A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and
implement the Ada package `GMA.Mainboard` with a single function `ports`
that returns a list of ports to be probed for displays.
v2: Update 3rdparty/libgfxinit to its latest master commit to make
things buildable within coreboot.
v3: Another update to 3rdparty/libgfxinit. Including support to select
the I2C port for VGA.
Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
3rdparty/libgfxinit | 2 +-
src/device/Kconfig | 18 +++++-
src/drivers/intel/gma/Kconfig | 51 ++++++++++++++++
src/drivers/intel/gma/Makefile.inc | 23 ++++++++
src/drivers/intel/gma/gma.adb | 117 +++++++++++++++++++++++++++++++++++++
src/drivers/intel/gma/gma.ads | 43 ++++++++++++++
src/drivers/intel/gma/i915.h | 3 +
7 files changed, 255 insertions(+), 2 deletions(-)
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
index 83693c8..6a35667 160000
--- a/3rdparty/libgfxinit
+++ b/3rdparty/libgfxinit
@@ -1 +1 @@
-Subproject commit 83693c8d7d87f5cebe120abdf25951c9e212b319
+Subproject commit 6a3566773f3b52550ebf0d042154958a2403bb40
diff --git a/src/device/Kconfig b/src/device/Kconfig
index c7dfe9c..78314bf 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -24,7 +24,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT
# FIXME Ugly hack to allow Z9s driver native framebuffer configuration
config NATIVE_VGA_INIT_USE_EDID
bool
- default n if DRIVERS_XGI_Z9S
+ default n if DRIVERS_XGI_Z9S || MAINBOARD_USE_LIBGFXINIT
default y if !DRIVERS_XGI_Z9S
config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
@@ -42,6 +42,22 @@ config MAINBOARD_DO_NATIVE_VGA_INIT
If unsure, say N.
+config MAINBOARD_HAS_LIBGFXINIT
+ def_bool n
+ help
+ Selected by mainboards that implement support for `libgfxinit`.
+ Usually this requires a list of ports to be probed for displays.
+
+config MAINBOARD_USE_LIBGFXINIT
+ bool "Use libgfxinit for native graphics initialization"
+ depends on MAINBOARD_DO_NATIVE_VGA_INIT
+ depends on MAINBOARD_HAS_LIBGFXINIT
+ select RAMSTAGE_LIBHWBASE
+ default n
+ help
+ Use the SPARK library `libgfxinit` for the native graphics
+ initialization. This requires an Ada toolchain.
+
# TODO: Explain differences (if any) for onboard cards.
config VGA_ROM_RUN
bool "Run VGA Option ROMs"
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index 1cfab3d..9c0f227 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -36,3 +36,54 @@ config INTEL_INT15
config INTEL_GMA_ACPI
bool
default n
+
+config GFX_GMA_CPU
+ string
+ default "Skylake" if SOC_INTEL_SKYLAKE
+ default "Broadwell" if SOC_INTEL_BROADWELL
+ default "Haswell" if NORTHBRIDGE_INTEL_HASWELL
+ default "Ivybridge" if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default "Sandybridge" if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM
+
+config GFX_GMA_CPU_VARIANT
+ string
+ default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL
+ default "Normal"
+
+config GFX_GMA_INTERNAL_IS_EDP
+ bool
+ default n if GFX_GMA_INTERNAL_IS_LVDS
+ default y
+
+config GFX_GMA_INTERNAL_IS_LVDS
+ bool
+ default n
+
+config GFX_GMA_INTERNAL_PORT
+ string
+ default "DP" if GFX_GMA_INTERNAL_IS_EDP
+ default "LVDS"
+
+config GFX_GMA_ANALOG_I2C_HDMI_B
+ bool
+ default n
+
+config GFX_GMA_ANALOG_I2C_HDMI_C
+ bool
+ default n
+
+config GFX_GMA_ANALOG_I2C_HDMI_D
+ bool
+ default n
+
+config GFX_GMA_ANALOG_I2C_PORT
+ string
+ default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B
+ default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C
+ default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D
+ default "PCH_DAC"
+ help
+ Boards with a DVI-I connector share the I2C pins for both analog and
+ digital displays. In that case, the EDID for a VGA display has to be
+ read over the I2C interface of the coupled digital port.
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index 88b91f6..a4e007c 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -20,3 +20,26 @@ ifeq ($(CONFIG_VGA_ROM_RUN),y)
ramstage-$(CONFIG_INTEL_INT15) += int15.c
endif
ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
+
+
+ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y)
+
+$(call add-special-class,gfxinit)
+gfxinit-handler = $(eval ramstage-srcs += $(1)$(2))
+
+$(call add-special-class,gfxinit-gen)
+gfxinit-gen-handler = \
+ $(eval additional-dirs += $(dir $(2))) \
+ $(eval ramstage-srcs += $(2)) \
+ $(eval ramstage-ads-deps += $(2)) \
+ $(eval ramstage-adb-deps += $(2)) \
+ $(eval $(2): $(obj)/config.h)
+
+CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime
+
+subdirs-y += ../../../../3rdparty/libgfxinit
+
+ramstage-y += gma.ads
+ramstage-y += gma.adb
+
+endif # CONFIG_MAINBOARD_USE_LIBGFXINIT
diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb
new file mode 100644
index 0000000..7ebc4f8
--- /dev/null
+++ b/src/drivers/intel/gma/gma.adb
@@ -0,0 +1,117 @@
+with HW.GFX;
+with HW.GFX.Framebuffer_Filler;
+with HW.GFX.GMA;
+
+use HW.GFX;
+use HW.GFX.GMA;
+
+with GMA.Mainboard;
+
+package body GMA
+is
+
+ vbe_valid : boolean := false;
+
+ linear_fb_addr : word64;
+
+ fb : Framebuffer_Type;
+
+ function vbe_mode_info_valid return Interfaces.C.int
+ is
+ begin
+ return (if vbe_valid then 1 else 0);
+ end vbe_mode_info_valid;
+
+ procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer)
+ is
+ use type word32;
+ begin
+ framebuffer :=
+ (tag => 0,
+ size => 0,
+ physical_address => linear_fb_addr,
+ x_resolution => word32 (fb.Width),
+ y_resolution => word32 (fb.Height),
+ bytes_per_line => 4 * word32 (fb.Stride),
+ bits_per_pixel => 32,
+ reserved_mask_pos => 24,
+ reserved_mask_size => 8,
+ red_mask_pos => 16,
+ red_mask_size => 8,
+ green_mask_pos => 8,
+ green_mask_size => 8,
+ blue_mask_pos => 0,
+ blue_mask_size => 8);
+ end fill_lb_framebuffer;
+
+ ----------------------------------------------------------------------------
+
+ procedure gfxinit
+ (mmio_base : in word64;
+ linear_fb : in word64;
+ phys_fb : in word32;
+ lightup_ok : out Interfaces.C.int)
+ is
+ use type pos32;
+
+ ports : Port_List;
+ configs : Configs_Type;
+
+ success : boolean;
+
+ stride : Width_Type;
+ max_h : pos16 := 1;
+ max_v : pos16 := 1;
+ begin
+ lightup_ok := 0;
+
+ HW.GFX.GMA.Initialize
+ (MMIO_Base => mmio_base,
+ Success => success);
+
+ if success then
+ ports := Mainboard.ports;
+ HW.GFX.GMA.Scan_Ports (configs, ports);
+
+ if configs (Primary).Port /= Disabled then
+ for i in Config_Index loop
+ exit when configs (i).Port = Disabled;
+
+ max_h := pos16'max (max_h, configs (i).Mode.H_Visible);
+ max_v := pos16'max (max_v, configs (i).Mode.V_Visible);
+ end loop;
+
+ stride := ((Width_Type (max_h) + 63) / 64) * 64;
+ for i in Config_Index loop
+ exit when configs (i).Port = Disabled;
+
+ configs (i).Framebuffer :=
+ (Width => Width_Type (configs (i).Mode.H_Visible),
+ Height => Height_Type (configs (i).Mode.V_Visible),
+ BPC => 8,
+ Stride => stride,
+ Offset => 0);
+ end loop;
+
+ HW.GFX.GMA.Dump_Configs (configs);
+
+ fb :=
+ (Width => Width_Type (max_h),
+ Height => Height_Type (max_v),
+ BPC => 8,
+ Stride => stride,
+ Offset => 0);
+ HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb);
+ HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb);
+
+ HW.GFX.GMA.Update_Outputs (configs);
+
+ linear_fb_addr := linear_fb;
+ vbe_valid := true;
+
+ lightup_ok := 1;
+ end if;
+ end if;
+ end gfxinit;
+
+end GMA;
diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads
new file mode 100644
index 0000000..d912df1
--- /dev/null
+++ b/src/drivers/intel/gma/gma.ads
@@ -0,0 +1,43 @@
+with Interfaces.C;
+
+with HW;
+use HW;
+
+package GMA
+is
+
+ procedure gfxinit
+ (mmio_base : in word64;
+ linear_fb : in word64;
+ phys_fb : in word32;
+ lightup_ok : out Interfaces.C.int)
+ pragma Export (C, gfxinit, "gma_gfxinit");
+
+ ----------------------------------------------------------------------------
+
+ function vbe_mode_info_valid return Interfaces.C.int;
+ pragma Export (C, vbe_mode_info_valid, "vbe_mode_info_valid");
+
+ type lb_framebuffer is record
+ tag : word32;
+ size : word32;
+
+ physical_address : word64;
+ x_resolution : word32;
+ y_resolution : word32;
+ bytes_per_line : word32;
+ bits_per_pixel : word8;
+ red_mask_pos : word8;
+ red_mask_size : word8;
+ green_mask_pos : word8;
+ green_mask_size : word8;
+ blue_mask_pos : word8;
+ blue_mask_size : word8;
+ reserved_mask_pos : word8;
+ reserved_mask_size : word8;
+ end record;
+
+ procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer);
+ pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer");
+
+end GMA;
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index e0d665b..d9bb940 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -309,4 +309,7 @@ void
generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf,
struct device *dev, const char *idstr);
+/* interface to libgfxinit (gma.adb) */
+void gma_gfxinit(u64 mmio_base, u64 linear_fb, u32 phys_fb, int *success);
+
#endif
1
0

Patch set updated for coreboot: nb/intel/nehalem, sandybridge: Hook up libgfxinit
by Nico Huber Oct. 31, 2016
by Nico Huber Oct. 31, 2016
Oct. 31, 2016
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16953
-gerrit
commit 4e65fd6fa0bc15d4a0449a59fe87729a64c83135
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Oct 5 18:02:01 2016 +0200
nb/intel/nehalem,sandybridge: Hook up libgfxinit
Change-Id: I4288193c022cc0963b926b4b43834c222e41bb0d
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/northbridge/intel/nehalem/gma.c | 10 ++++++++--
src/northbridge/intel/sandybridge/gma.c | 10 ++++++++--
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 46d867f..a0d51d0 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -1024,8 +1024,14 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
- pio_res->base, lfb_res->base);
+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ int lightup_ok;
+ gma_gfxinit(gtt_res->base, lfb_res->base,
+ physbase, &lightup_ok);
+ } else {
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
+ }
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 1f52511..f050eb2 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -603,8 +603,14 @@ static void gma_func0_init(struct device *dev)
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
- int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase,
- mmiobase, graphics_base);
+ int lightup_ok;
+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ gma_gfxinit((uintptr_t)mmiobase, graphics_base,
+ physbase, &lightup_ok);
+ } else {
+ lightup_ok = i915lightup_sandy(&conf->gfx, physbase,
+ iobase, mmiobase, graphics_base);
+ }
if (lightup_ok)
gfx_set_init_done(1);
}
1
0

Patch set updated for coreboot: mb/kontron/ktqm77: Enable native gfx init through libgfxinit
by Nico Huber Oct. 31, 2016
by Nico Huber Oct. 31, 2016
Oct. 31, 2016
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17074
-gerrit
commit 36860b42f7093d71a11801c92d2a0af3ac502db0
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Oct 19 13:41:42 2016 +0200
mb/kontron/ktqm77: Enable native gfx init through libgfxinit
Change-Id: Ie16b3236e7378a2062b3081e4530d7a4791b4b66
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/mainboard/kontron/ktqm77/Kconfig | 4 ++++
src/mainboard/kontron/ktqm77/Makefile.inc | 2 ++
src/mainboard/kontron/ktqm77/gma-mainboard.ads | 21 +++++++++++++++++++++
3 files changed, 27 insertions(+)
diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig
index 77ad91b..d4a1e8a 100644
--- a/src/mainboard/kontron/ktqm77/Kconfig
+++ b/src/mainboard/kontron/ktqm77/Kconfig
@@ -12,6 +12,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select ENABLE_VMX
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_ANALOG_I2C_HDMI_B
+ select GFX_GMA_INTERNAL_IS_LVDS
config MAINBOARD_DIR
string
diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc
index 3dae61e..ea035d3 100644
--- a/src/mainboard/kontron/ktqm77/Makefile.inc
+++ b/src/mainboard/kontron/ktqm77/Makefile.inc
@@ -1 +1,3 @@
romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/kontron/ktqm77/gma-mainboard.ads b/src/mainboard/kontron/ktqm77/gma-mainboard.ads
new file mode 100644
index 0000000..cf86617
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/gma-mainboard.ads
@@ -0,0 +1,21 @@
+with HW.GFX.GMA;
+
+use HW.GFX.GMA;
+
+private package GMA.Mainboard is
+
+ -- For a three-pipe setup, bandwidth is shared between the 2nd and
+ -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely
+ -- have a high-resolution display attached first, `Internal` last.
+
+ ports : constant Port_List :=
+ (DP2,
+ DP3,
+ Digital1,
+ Digital2,
+ Digital3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
1
0

Oct. 31, 2016
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16951
-gerrit
commit 6e4dced10ef74db2f6ad5d6441606f5430a7a844
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Oct 5 17:46:49 2016 +0200
Hook up libhwbase in ramstage
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`.
This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.
v2: Also update 3rdparty/libhwbase to the latest master commit.
Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
3rdparty/libhwbase | 2 +-
src/Kconfig | 9 +++++++
src/console/Kconfig | 9 +++++++
src/console/Makefile.inc | 4 +++
src/console/hw-debug_sink.adb | 59 +++++++++++++++++++++++++++++++++++++++++++
src/console/hw-debug_sink.ads | 24 ++++++++++++++++++
src/lib/Makefile.inc | 10 ++++++++
src/lib/gnat/Makefile.inc | 2 +-
src/lib/hw-time-timer.adb | 48 +++++++++++++++++++++++++++++++++++
9 files changed, 165 insertions(+), 2 deletions(-)
diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase
index 5e9b1b5..aab715f 160000
--- a/3rdparty/libhwbase
+++ b/3rdparty/libhwbase
@@ -1 +1 @@
-Subproject commit 5e9b1b50e7ac90f68ca2ea798ef656ac863c2851
+Subproject commit aab715f166bf1b54cfbd6982e8df49248ea544d8
diff --git a/src/Kconfig b/src/Kconfig
index d6af6eb..1b915af 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1248,3 +1248,12 @@ config RAMSTAGE_ADA
def_bool n
help
Selected by features that use Ada code in ramstage.
+
+config RAMSTAGE_LIBHWBASE
+ def_bool n
+ select RAMSTAGE_ADA
+ help
+ Selected by features that require `libhwbase` in ramstage.
+
+config HWBASE_DYNAMIC_MMIO
+ def_bool y
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 8f74613..caf91ab 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -399,4 +399,13 @@ config NO_EARLY_BOOTBLOCK_POSTCODES
POST codes that go out before the chipset's bootblock initialization
can happen. This option suppresses those POST codes.
+config HWBASE_DEBUG_CB
+ bool
+ default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+ default n
+
+config HWBASE_DEBUG_NULL
+ def_bool y
+ depends on !HWBASE_DEBUG_CB
+
endmenu
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 059dea5..aa0dbf5 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -2,6 +2,10 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c
ramstage-y += init.c console.c
ramstage-y += post.c
ramstage-y += die.c
+ifeq ($(CONFIG_HWBASE_DEBUG_CB),y)
+ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.ads
+ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.adb
+endif
smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c
smm-$(CONFIG_SMM_TSEG) += die.c
diff --git a/src/console/hw-debug_sink.adb b/src/console/hw-debug_sink.adb
new file mode 100644
index 0000000..5a16556
--- /dev/null
+++ b/src/console/hw-debug_sink.adb
@@ -0,0 +1,59 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2015 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with Interfaces.C;
+
+use type Interfaces.C.int;
+
+package body HW.Debug_Sink is
+
+ Sink_Enabled : Boolean;
+
+ procedure console_tx_byte (chr : Interfaces.C.char);
+ pragma Import (C, console_tx_byte, "console_tx_byte");
+
+ procedure Put (Item : String) is
+ begin
+ if Sink_Enabled then
+ for Idx in Item'Range loop
+ console_tx_byte (Interfaces.C.To_C (Item (Idx)));
+ end loop;
+ end if;
+ end Put;
+
+ procedure Put_Char (Item : Character) is
+ begin
+ if Sink_Enabled then
+ console_tx_byte (Interfaces.C.To_C (Item));
+ end if;
+ end Put_Char;
+
+ procedure New_Line is
+ begin
+ Put_Char (Character'Val (16#0a#));
+ end New_Line;
+
+ ----------------------------------------------------------------------------
+
+ function console_log_level
+ (msg_level : Interfaces.C.int)
+ return Interfaces.C.int;
+ pragma Import (C, console_log_level, "console_log_level");
+
+ Msg_Level_BIOS_DEBUG : constant := 7;
+
+begin
+ Sink_Enabled := console_log_level (Msg_Level_BIOS_DEBUG) /= 0;
+end HW.Debug_Sink;
diff --git a/src/console/hw-debug_sink.ads b/src/console/hw-debug_sink.ads
new file mode 100644
index 0000000..322249e
--- /dev/null
+++ b/src/console/hw-debug_sink.ads
@@ -0,0 +1,24 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2015 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+package HW.Debug_Sink is
+
+ procedure Put (Item : String);
+
+ procedure Put_Char (Item : Character);
+
+ procedure New_Line;
+
+end HW.Debug_Sink;
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 67f8364..d654f27 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -261,3 +261,13 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL)
$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL)
$(RMODTOOL) -i $< -o $@
+
+ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y)
+
+$(call add-special-class,hw)
+hw-handler = $(eval ramstage-srcs += $$(addprefix $(1),$(2)))
+subdirs-y += ../../3rdparty/libhwbase
+
+ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb
+
+endif # CONFIG_RAMSTAGE_LIBHWBASE
diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc
index 394c838..9c68624 100644
--- a/src/lib/gnat/Makefile.inc
+++ b/src/lib/gnat/Makefile.inc
@@ -62,5 +62,5 @@ $(foreach arch,$(standard-archs), \
$(eval $(call libgnat-template,$(arch))))
ifeq ($(CONFIG_RAMSTAGE_ADA),y)
-ramstage-libs += $$(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a
+ramstage-libs += $(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a
endif
diff --git a/src/lib/hw-time-timer.adb b/src/lib/hw-time-timer.adb
new file mode 100644
index 0000000..643cc98
--- /dev/null
+++ b/src/lib/hw-time-timer.adb
@@ -0,0 +1,48 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2016 secunet Security Networks AG
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; version 2 of the License.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with Interfaces.C;
+
+package body HW.Time.Timer
+ with Refined_State => (Timer_State => null,
+ Abstract_Time => null)
+is
+
+ procedure Timer_Monotonic_Get (MT : out Interfaces.C.long);
+ pragma Import (C, Timer_Monotonic_Get, "timer_monotonic_get");
+
+ function Raw_Value_Min return T
+ with
+ SPARK_Mode => Off
+ is
+ Microseconds : Interfaces.C.long;
+ begin
+ Timer_Monotonic_Get (Microseconds);
+ return T (Microseconds);
+ end Raw_Value_Min;
+
+ function Raw_Value_Max return T
+ is
+ begin
+ return Raw_Value_Min + 1;
+ end Raw_Value_Max;
+
+ function Hz return T
+ is
+ begin
+ return 1_000_000;
+ end Hz;
+
+end HW.Time.Timer;
1
0

Oct. 31, 2016
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16944
-gerrit
commit 88430a483cb0fc86a1942747c6fdc9615c5e5107
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Fri Oct 7 12:58:17 2016 +0200
Add option to use Ada code in ramstage
Change-Id: I11417db21f16bf3007739a097d63fd592344bce3
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/Kconfig | 5 +++++
src/include/adainit.h | 23 +++++++++++++++++++++++
src/lib/gnat/Makefile.inc | 4 ++++
src/lib/hardwaremain.c | 3 +++
4 files changed, 35 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index e337a1a..d6af6eb 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1243,3 +1243,8 @@ config CHECKLIST_DATA_FILE_LOCATION
symbols contained only in <stage>_complete.dat will be flagged as
required and not implemented if a weak implementation is found in the
resulting image.
+
+config RAMSTAGE_ADA
+ def_bool n
+ help
+ Selected by features that use Ada code in ramstage.
diff --git a/src/include/adainit.h b/src/include/adainit.h
new file mode 100644
index 0000000..191fff1
--- /dev/null
+++ b/src/include/adainit.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ADAINIT_H
+#define _ADAINIT_H
+
+#if IS_ENABLED(CONFIG_RAMSTAGE_ADA)
+void ramstage_adainit(void);
+#else
+static inline void ramstage_adainit(void) {}
+#endif
+
+#endif /* _ADAINIT_H */
diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc
index 6ba274a..394c838 100644
--- a/src/lib/gnat/Makefile.inc
+++ b/src/lib/gnat/Makefile.inc
@@ -60,3 +60,7 @@ $(foreach arch,$(standard-archs), \
$(foreach arch,$(standard-archs), \
$(eval $(call libgnat-template,$(arch))))
+
+ifeq ($(CONFIG_RAMSTAGE_ADA),y)
+ramstage-libs += $$(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a
+endif
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index ab4d9f4..f529720 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -18,6 +18,7 @@
* C Bootstrap code for the coreboot
*/
+#include <adainit.h>
#include <arch/exception.h>
#include <bootstate.h>
#include <console/console.h>
@@ -429,6 +430,8 @@ static void boot_state_schedule_static_entries(void)
void main(void)
{
+ ramstage_adainit();
+
/* TODO: Understand why this is here and move to arch/platform code. */
/* For MMIO UART this needs to be called before any other printk. */
if (IS_ENABLED(CONFIG_ARCH_X86))
1
0

Oct. 31, 2016
Piotr Król (piotr.krol(a)3mdeb.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14138
-gerrit
commit edb7591dd97cb580e72be703ffbf6d8b687b4440
Author: Piotr Król <piotr.krol(a)3mdeb.com>
Date: Fri May 27 12:04:13 2016 +0200
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu…
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
src/mainboard/pcengines/apu2/BiosCallOuts.c | 157 ++++++++++++
src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex | 264 +++++++++++++++++++++
.../pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex | 261 ++++++++++++++++++++
src/mainboard/pcengines/apu2/Kconfig | 91 +++++++
src/mainboard/pcengines/apu2/Kconfig.name | 2 +
src/mainboard/pcengines/apu2/Makefile.inc | 41 ++++
src/mainboard/pcengines/apu2/OemCustomize.c | 121 ++++++++++
src/mainboard/pcengines/apu2/acpi/AmdImc.asl | 109 +++++++++
src/mainboard/pcengines/apu2/acpi/gpe.asl | 67 ++++++
src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 +++
src/mainboard/pcengines/apu2/acpi/routing.asl | 193 +++++++++++++++
src/mainboard/pcengines/apu2/acpi/si.asl | 23 ++
src/mainboard/pcengines/apu2/acpi/sleep.asl | 95 ++++++++
src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 36 +++
src/mainboard/pcengines/apu2/acpi_tables.c | 56 +++++
src/mainboard/pcengines/apu2/board_info.txt | 6 +
src/mainboard/pcengines/apu2/cmos.layout | 74 ++++++
src/mainboard/pcengines/apu2/devicetree.cb | 91 +++++++
src/mainboard/pcengines/apu2/dsdt.asl | 84 +++++++
src/mainboard/pcengines/apu2/gpio_ftns.c | 34 +++
src/mainboard/pcengines/apu2/gpio_ftns.h | 59 +++++
src/mainboard/pcengines/apu2/irq_tables.c | 103 ++++++++
src/mainboard/pcengines/apu2/mainboard.c | 195 +++++++++++++++
src/mainboard/pcengines/apu2/mptable.c | 166 +++++++++++++
src/mainboard/pcengines/apu2/romstage.c | 145 +++++++++++
src/southbridge/amd/pi/hudson/early_setup.c | 18 +-
26 files changed, 2527 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
new file mode 100644
index 0000000..bba8144
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <spd_cache.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "imc.h"
+#endif
+#include "hudson.h"
+#include <stdlib.h>
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
+
+
+/*
+ * Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM will fail to read the input temperature via I2C if other
+ * software switches the I2C address. AMD recommends using IMC
+ * to control fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = FALSE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->FchReset.SataEnable = hudson_sata_enable();
+ FchParams->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci1Enable = FALSE;
+ } else if (StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+
+ FchParams->Azalia.AzaliaEnable = AzDisable;
+
+ /* Fan Control */
+ oem_fan_control(FchParams);
+
+ /* XHCI configuration */
+ FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci1Enable = FALSE;
+
+ /* EHCI configuration */
+ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+ /* sata configuration */
+ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+ FchParams->Sata.SataDevSlpPort1 = 0;
+
+ FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ case SataRaid:
+ case SataAhci:
+ case SataAhci7804:
+ case SataLegacyIde:
+ FchParams->Sata.SataIdeMode = FALSE;
+ break;
+ case SataIde2Ahci:
+ case SataIde2Ahci7804:
+ default: /* SataNativeIde */
+ FchParams->Sata.SataIdeMode = TRUE;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
+
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ int index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/
+
+ u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
+ if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
+ if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
+
+ printk(BIOS_INFO, "Reading SPD index %d\n", index);
+
+ if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
new file mode 100644
index 0000000..a70db53
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
@@ -0,0 +1,264 @@
+# PCEngines 2Gb 1333
+
+# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+03
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6.0ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - OEM specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+15
+
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+b6 73
+
diff --git a/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
new file mode 100644
index 0000000..ac6b4c6
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
@@ -0,0 +1,261 @@
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+
+# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+08
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5 ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+20 08
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+15 44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+67 94
+
+
+
+
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
new file mode 100644
index 0000000..f09a220
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki(a)gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_PCENGINES_APU2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_PI_00730F01
+ select NORTHBRIDGE_AMD_PI_00730F01
+ select SOUTHBRIDGE_AMD_PI_AVALON
+ select SUPERIO_NUVOTON_NCT5104D
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select SPD_CACHE
+ select HUDSON_DISABLE_IMC
+ select USE_BLOBS
+
+config MAINBOARD_DIR
+ string
+ default pcengines/apu2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PCEngines apu2"
+
+config MAX_CPUS
+ int
+ default 4
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+config AGESA_BINARY_PI_FILE
+ string
+ default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
+
+choice
+ prompt "J19 pins 1-10"
+ default APU2_PINMUX_OFF_C
+
+config APU2_PINMUX_OFF_C
+ bool "disable"
+
+config APU2_PINMUX_GPIO0
+ bool "GPIO"
+
+config APU2_PINMUX_UART_C
+ bool "UART 0x3e8"
+
+endchoice
+
+choice
+ prompt "J19 pins 11-20"
+ default APU2_PINMUX_OFF_D
+
+config APU2_PINMUX_OFF_D
+ bool "disable"
+
+config APU2_PINMUX_GPIO1
+ bool "GPIO"
+
+config APU2_PINMUX_UART_D
+ bool "UART 0x2e8"
+
+endchoice
+
+endif # BOARD_PCENGINES_APU2
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
new file mode 100644
index 0000000..ab19ee4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PCENGINES_APU2
+ bool "APU2"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
new file mode 100644
index 0000000..e1a5f8d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -0,0 +1,41 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+romstage-y += gpio_ftns.c
+
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
new file mode 100644
index 0000000..06a8f3d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/AmdImc.asl b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
new file mode 100644
index 0000000..d3bb74e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl
new file mode 100644
index 0000000..cd366dc
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
new file mode 100644
index 0000000..0141481
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl
new file mode 100644
index 0000000..7cb7a2f
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/routing.asl
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 24 },
+ Package(){0x0002FFFF, 1, 0, 25 },
+ Package(){0x0002FFFF, 2, 0, 26 },
+ Package(){0x0002FFFF, 3, 0, 27 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl
new file mode 100644
index 0000000..2923471
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl
new file mode 100644
index 0000000..0734c8e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* clear USB wake up signal */
+ Store(1, USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
new file mode 100644
index 0000000..1643fe7
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
new file mode 100644
index 0000000..d5ebad4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
new file mode 100644
index 0000000..a69e616
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -0,0 +1,6 @@
+Board name: PC Engines APU2
+Board URL: http://www.pcengines.ch/apu2c2.htm
+Category: half
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout
new file mode 100644
index 0000000..d83bb14
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/cmos.layout
@@ -0,0 +1,74 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
new file mode 100644
index 0000000..3c5ec81
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 off end # USB EHCI0 usb[0:3] not connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
new file mode 100644
index 0000000..1fcd905
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+
+ } /* End \_SB scope */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
new file mode 100644
index 0000000..fd1fb3c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+#include "gpio_ftns.h"
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
+{
+ u8 bdata;
+ u8 *memptr;
+
+ memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);
+ *memptr = iomux_ftn;
+
+ memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ bdata = *memptr;
+ bdata &= 0x07;
+ bdata |= setting; /* set direction and data value */
+ *memptr = bdata;
+}
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
new file mode 100644
index 0000000..4f0cbaa
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GPIO_FTNS_H
+#define GPIO_FTNS_H
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+
+#define IOMUX_OFFSET 0xD00
+#define GPIO_OFFSET 0x1500
+
+//
+// Based on PC Engines APU2C schematics
+// http://www.pcengines.ch/schema/apu2c.pdf
+//
+#define IOMUX_GPIO_32 0x59 // MODESW
+#define IOMUX_GPIO_49 0x40 // STRAP0
+#define IOMUX_GPIO_50 0x41 // STRAP1
+#define IOMUX_GPIO_51 0x42 // PE3 Reset
+#define IOMUX_GPIO_55 0x43 // PE4 Reset
+#define IOMUX_GPIO_57 0x44 // LED1#
+#define IOMUX_GPIO_58 0x45 // LED2#
+#define IOMUX_GPIO_59 0x46 // LED3#
+#define IOMUX_GPIO_64 0x47 // PE3_WDIS
+#define IOMUX_GPIO_66 0x5B // SPKR
+#define IOMUX_GPIO_68 0x48 // PE4_WDIS
+#define IOMUX_GPIO_71 0x4D // PROCHOT
+
+#define GPIO_32 0x164 // MODESW
+#define GPIO_49 0x100 // STRAP0
+#define GPIO_50 0x104 // STRAP1
+#define GPIO_51 0x108 // PE3 Reset
+#define GPIO_55 0x10C // PE4 Reset
+#define GPIO_57 0x110 // LED1#
+#define GPIO_58 0x114 // LED2#
+#define GPIO_59 0x118 // LED3#
+#define GPIO_64 0x11C // PE3_WDIS
+#define GPIO_66 0x16C // SPKR
+#define GPIO_68 0x120 // PE4_WDIS
+#define GPIO_71 0x134 // PROCHOT
+
+#define GPIO_OUTPUT_ENABLE 23
+#define GPIO_OUTPUT_VALUE 22
+#define GPIO_PULL_DOWN_ENABLE 21
+#define GPIO_PULL_UP_ENABLE 20
+
+#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c
new file mode 100644
index 0000000..eaeed3f
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/irq_tables.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam16.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdee8, 0x2, 0xdee8, 0x3, 0xdee8, 0x4, 0xdee8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
new file mode 100644
index 0000000..98fe8dd
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <southbridge/amd/pi/hudson/pci_devs.h>
+#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
+#include <northbridge/amd/pi/00730F01/pci_devs.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#define SPD_SIZE 128
+#define PM_RTC_CONTROL 0x56
+#define PM_S_STATE_CONTROL 0xBA
+
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/22 INTA-C */
+ [0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/20/22 INTA-C */
+ [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device. Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01. This index will define
+ * the interrupt that it should use. Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
+ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
+ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
+ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
+ * once configuration file format for SPI flash storage is complete.
+ */
+#define SIO_PORT 0x2e
+
+static void config_gpio_mux(void)
+{
+ struct device *uart, *gpio;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_C;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO0;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_D;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO1;
+}
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ config_gpio_mux();
+
+ //
+ // Enable the RTC output
+ //
+ pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
+
+ //
+ // Enable power on from WAKE#
+ //
+ pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
new file mode 100644
index 0000000..896e637
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+#if 0
+u8 picr_data[FCH_INT_TABLE_SIZE] = {
+ 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+u8 intr_data[FCH_INT_TABLE_SIZE] = {
+ 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+
+#endif
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ /* Intialize the MP_Table */
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ /*
+ * Type 0: Processor Entries:
+ * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+ * CPU Signature (Stepping, Model, Family),
+ * Feature Flags
+ */
+ smp_write_processors(mc);
+
+ /*
+ * Type 1: Bus Entries:
+ * Bus ID, Bus Type
+ */
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /*
+ * Type 2: I/O APICs:
+ * APIC ID, Version, APIC Flags:EN, Address
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ /*
+ * Type 3: I/O Interrupt Table Entries:
+ * Int Type, Int Polarity, Int Level, Source Bus ID,
+ * Source Bus IRQ, Dest APIC ID, Dest PIN#
+ */
+
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+
+ /* SMBUS / ACPI */
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
+
+ /* SD card */
+ PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
+
+ /* SATA */
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
+
+ /* on board NIC & Slot PCIE */
+ PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
+ PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
+
+
+ /* GPP0 */
+ PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
+ /* GPP1 */
+ PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
+ /* GPP2 */
+ PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
+ /* GPP3 */
+ PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
+ /* GPP4 */
+ PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
+
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
new file mode 100644
index 0000000..f8ed63c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <Fch/Fch.h>
+#include "gpio_ftns.h"
+
+static void early_lpc_init(void);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ amd_initmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ early_lpc_init();
+
+ hudson_clk_output_48Mhz();
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
+
+ post_code(0x39);
+ AGESAWRAPPER(amdinitearly);
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
+
+
+static void early_lpc_init(void)
+{
+ u32 setting = 0x0;
+
+ //
+ // Configure output disabled, value low, pull up/down disabled
+ //
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ //
+ // Configure output enabled, value low, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ //
+ // Configure output enabled, value high, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 29809f1..553add9 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -25,12 +25,12 @@
#include <cbmem.h>
#include "hudson.h"
#include "pci_devs.h"
+#include <Fch/Fch.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>
-#include <Fch/Fch.h>
void configure_hudson_uart(void)
{
@@ -174,4 +174,20 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
+void hudson_clk_output_48Mhz(void)
+{
+ u32 data, *memptr;
+
+ /*
+ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
+ * 48Mhz will be on ball AP13 (FT3b package)
+ */
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+ data = *memptr;
+
+ /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
+ data &= (u32)~(1<<2);
+ *memptr = data;
+}
+
#endif
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Patch set updated for coreboot: nb/i945/raminit.c: Correct C*R0B00DQST values for i945GC
by HAOUAS Elyes Oct. 31, 2016
by HAOUAS Elyes Oct. 31, 2016
Oct. 31, 2016
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17197
-gerrit
commit 64fe93310aca2f00326382574a894bee6412fc16
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Oct 31 10:49:33 2016 +0100
nb/i945/raminit.c: Correct C*R0B00DQST values for i945GC
It needs test. Values based on vendor bios.
Change-Id: I2160f0ac73776b20e2cc1ff5bf77ebe98d2c2672
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/northbridge/intel/i945/raminit.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index dbd5d42..24f81aa 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1233,10 +1233,18 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */
- switch (sysinfo->memory_frequency) {
- case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */
- case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */
- case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */
+ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
+ switch (sysinfo->memory_frequency) {
+ case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */
+ case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */
+ case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */
+ }
+ } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ switch (sysinfo->memory_frequency) {
+ case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */
+ case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */
+ case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */
+ }
}
for (i = 0; i < 4; i++) {
1
0