coreboot-gerrit October 2015

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New patch to review for coreboot: WIP: x86/bootblock: Code reset entry and protected mode switch in NASM
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11794 -gerrit commit 7b83975e0fa510eb78dc3392603b374c62acfedf Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Oct 4 18:30:59 2015 -0700 WIP: x86/bootblock: Code reset entry and protected mode switch in NASM Now that we can use NASM, demonstrate its power by coding the reset vector entry and switch to protected mode in NASM, and removing the old implementation with GNU as. Note that src/cpu/x86/32bit/entry32.inc is kept for now, as it is needed by romstage. However, at this point, this patch series is concerned with the bootblock. Other stages will be updated later in the series. Change-Id: Iaeb63d015950cc9df265d00805735d3f8d18735e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/bootblock.S | 6 +- src/arch/x86/bootblock.ld | 3 +- src/cpu/x86/16bit/entry16.inc | 140 -------------------------------- src/cpu/x86/16bit/entry16.ld | 2 - src/cpu/x86/16bit/reset16.inc | 16 ---- src/cpu/x86/16bit/reset16.ld | 16 ---- src/cpu/x86/Makefile.inc | 2 + src/cpu/x86/reset_entry/reset16.ld | 16 ++++ src/cpu/x86/reset_entry/reset_entry.asm | 81 ++++++++++++++++++ 9 files changed, 103 insertions(+), 179 deletions(-) diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S index 645e491..d575aa4 100644 --- a/src/arch/x86/bootblock.S +++ b/src/arch/x86/bootblock.S @@ -22,9 +22,9 @@ * of the includes. */ #include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> + +.global legacy_bootblock_entry +legacy_bootblock_entry: #ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE #include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 6835430..8499b4d 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -18,8 +18,7 @@ */ #include <arch/x86/failover.ld> -#include <cpu/x86/16bit/entry16.ld> -#include <cpu/x86/16bit/reset16.ld> +#include <cpu/x86/reset_entry/reset16.ld> #include <arch/x86/id.ld> #if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc deleted file mode 100644 index 4dad1e5..0000000 --- a/src/cpu/x86/16bit/entry16.inc +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This software and ancillary information (herein called SOFTWARE) - * called LinuxBIOS is made available under the terms described here. - * - * The SOFTWARE has been approved for release with associated - * LA-CC Number 00-34. Unless otherwise indicated, this SOFTWARE has - * been authored by an employee or employees of the University of - * California, operator of the Los Alamos National Laboratory under - * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. - * - * The U.S. Government has rights to use, reproduce, and distribute this - * SOFTWARE. The public may copy, distribute, prepare derivative works - * and publicly display this SOFTWARE without charge, provided that this - * Notice and any statement of authorship are reproduced on all copies. - * - * Neither the Government nor the University makes any warranty, express - * or implied, or assumes any liability or responsibility for the use of - * this SOFTWARE. If SOFTWARE is modified to produce derivative works, - * such modified SOFTWARE should be clearly marked, so as not to confuse - * it with the version available from LANL. - * - * Copyright (C) 2000, Ron Minnich rminnich(a)lanl.gov - * Advanced Computing Lab, LANL - */ - - -/* Start code to put an i386 or later processor into 32-bit protected mode. - */ - -#include <arch/rom_segs.h> -.code16 -.globl _start -.type _start, @function - -_start: - cli - /* Save the BIST result */ - movl %eax, %ebp - - post_code(POST_RESET_VECTOR_CORRECT) - - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. Thanks to kmliu(a)sis.com.tw for this TLB fix. - */ - - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB*/ - - /* Invalidating the cache here seems to be a bad idea on - * modern processors. Don't. - * If we are hyperthreaded or we have multiple cores it is bad, - * for SMP startup. On Opterons it causes a 5 second delay. - * Invalidating the cache was pure paranoia in any event. - * If you cpu needs it you can write a cpu dependent version of - * entry16.inc. - */ - - /* Note: gas handles memory addresses in 16 bit code very poorly. - * In particular it doesn't appear to have a directive allowing you - * associate a section or even an absolute offset with a segment register. - * - * This means that anything except cs:ip relative offsets are - * a real pain in 16 bit mode. And explains why it is almost - * impossible to get gas to do lgdt correctly. - * - * One way to work around this is to have the linker do the - * math instead of the assembler. This solves the very - * pratical problem of being able to write code that can - * be relocated. - * - * An lgdt call before we have memory enabled cannot be - * position independent, as we cannot execute a call - * instruction to get our current instruction pointer. - * So while this code is relocateable it isn't arbitrarily - * relocatable. - * - * The criteria for relocation have been relaxed to their - * utmost, so that we can use the same code for both - * our initial entry point and startup of the second cpu. - * The code assumes when executing at _start that: - * (((cs & 0xfff) == 0) and (ip == _start & 0xffff)) - * or - * ((cs == anything) and (ip == 0)). - * - * The restrictions in reset16.inc mean that _start initially - * must be loaded at or above 0xffff0000 or below 0x100000. - * - * The linker scripts computes gdtptr16_offset by simply returning - * the low 16 bits. This means that the intial segment used - * when start is called must be 64K aligned. This should not - * restrict the address as the ip address can be anything. - * - * Also load an IDT with NULL limit to prevent the 16bit IDT being used - * in protected mode before c_start.S sets up a 32bit IDT when entering - * ram stage. In practise: CPU will shutdown on any exception. - * See IA32 manual Vol 3A 19.26 Interrupts. - */ - - movw %cs, %ax - shlw $4, %ax - movw $nullidt_offset, %bx - subw %ax, %bx - lidt %cs:(%bx) - movw $gdtptr16_offset, %bx - subw %ax, %bx - lgdtl %cs:(%bx) - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST to %eax */ - movl %ebp, %eax - - /* Now that we are in protected mode jump to a 32 bit code segment. */ - ljmpl $ROM_CODE_SEG, $__protected_start - - /** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment - * at 0x08, and a 4 GB data segment at 0x10; - */ -.align 4 -.globl gdtptr16 -gdtptr16: - .word gdt_end - gdt -1 /* compute the table limit */ - .long gdt /* we know the offset */ - -.align 4 -.globl nullidt -nullidt: - .word 0 /* limit */ - .long 0 - .word 0 - -.globl _estart -_estart: - .code32 diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld deleted file mode 100644 index 112d429..0000000 --- a/src/cpu/x86/16bit/entry16.ld +++ /dev/null @@ -1,2 +0,0 @@ - gdtptr16_offset = gdtptr16 & 0xffff; - nullidt_offset = nullidt & 0xffff; diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc deleted file mode 100644 index 33712d1..0000000 --- a/src/cpu/x86/16bit/reset16.inc +++ /dev/null @@ -1,16 +0,0 @@ - .section ".reset" - .code16 -.globl reset_vector -reset_vector: - .byte 0xe9 - .int _start - ( . + 2 ) - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 byte are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ - .org 0x8; - .code32 - jmp protected_start - .previous diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld deleted file mode 100644 index d0c4096..0000000 --- a/src/cpu/x86/16bit/reset16.ld +++ /dev/null @@ -1,16 +0,0 @@ -/* - * _ROMTOP : The top of the rom used where we - * need to put the reset vector. - */ - -SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); - _ROMTOP = 0xfffffff0; - . = _ROMTOP; - .reset . : { - KEEP(*(.reset)); - . = 15 ; - BYTE(0x00); - } -} diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index e9394b2..e046607 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_CACHE_AS_RAM) += car.c endif +bootblock-y += reset_entry/reset_entry.asm + subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c diff --git a/src/cpu/x86/reset_entry/reset16.ld b/src/cpu/x86/reset_entry/reset16.ld new file mode 100644 index 0000000..d0c4096 --- /dev/null +++ b/src/cpu/x86/reset_entry/reset16.ld @@ -0,0 +1,16 @@ +/* + * _ROMTOP : The top of the rom used where we + * need to put the reset vector. + */ + +SECTIONS { + /* Trigger an error if I have an unuseable start address */ + _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); + _ROMTOP = 0xfffffff0; + . = _ROMTOP; + .reset . : { + KEEP(*(.reset)); + . = 15 ; + BYTE(0x00); + } +} diff --git a/src/cpu/x86/reset_entry/reset_entry.asm b/src/cpu/x86/reset_entry/reset_entry.asm new file mode 100644 index 0000000..2878ef6 --- /dev/null +++ b/src/cpu/x86/reset_entry/reset_entry.asm @@ -0,0 +1,81 @@ +; +; The x86 journey, from embryo reset vector, to adult protected mode +; +; Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +; Subject to the GNU GPL v2, or (at your option) any later version. +; + +global _start +extern legacy_bootblock_entry + +ROM_CODE_SEG EQU 0x08 +ROM_DATA_SEG EQU 0x10 +POST_RESET_VECTOR_CORRECT EQU 0x01 + +%define post_code(code) \ + mov eax, code + out 0x80, eax + +section .reset + +reset_vector: bits 16 + jmp _start + + +section .text + +_start: bits 16 + ; + ; eax has BIST result, so try not to touch it + ; + mov esp, eax; + + post_code(POST_RESET_VECTOR_CORRECT) + + cli + + lidt [cs:idt] + o32 lgdt [cs:gdtr] ; for some reason, this needs a 32-bit operand size + + mov ecx, cr0 + and ecx, 0x7FFAFFD1 ; original bootblock did this + or ecx, 0x60000001 ; and this + mov cr0, ecx + + ; long jump to protected mode + jmp long ROM_CODE_SEG: protected_mode_start + +protected_mode_start: bits 32 + ; + ; eax still has BIST result. Don't touch it + ; + mov cx, ROM_DATA_SEG + mov ds, cx + mov es, cx + mov ss, cx + mov fs, cx + mov gs, cx + mov eax, esp + jmp legacy_bootblock_entry + +align 4 +gdtr: + dw gdt_size - 1 + dd gdt + +align 4 +gdt: + ; segment 0x00: unused + dw 0x0000, 0x0000 + db 0x00, 0x00, 0x00, 0x00 + ; segment 0x08: ROM_CODE_SEG + dw 0xffff, 0x0000 + db 0x00, 0x9b, 0xcf, 0x00 + ; segment 0x10: ROM_DATA_SEG + dw 0xffff, 0x0000 + db 0x00, 0x93, 0xcf, 0x00 +gdt_size EQU $ - gdt ; GNU as can't do this + +align 4 +idt: + dd 0x00000000, 0x00000000

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New patch to review for coreboot: arch/x86: Allow using NASM as an optional assembler
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11793 -gerrit commit b262953b325f40ec41a7ffbfe0e2e1210d40772a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 21:32:42 2015 -0700 arch/x86: Allow using NASM as an optional assembler Some people, such as Aaron and myself find GNU as and its ATT syntax to be hard to use and error-prone. Aaron knows of a few companies who produce coreboot code (or blobs), which are also migrating to NASM. It makes sense, from this point, to standardize on an assembler. This patch does create the somewhat sub-optimal situation where both NASM and GNU as can be used to create objects linked in a binary. The long term plan is to standardize on NASM, and replace the ROMCC parts of the bootblock with NASM assembly. Also, NASM does not use the C preprocessor. While it is possible to run NASM files through the C preprocessor, and allow tricks such as Change-Id: I6ec7db2d5893bb0b9943940c4f767a45ec32dc09 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e17fe11..f41255e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,13 +113,27 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) -$(objcbfs)/bootblock.debug: $$(bootblock-objs) +$(objcbfs)/bootblock.debug: $$(filter %.o,$$(bootblock-objs)) $$(filter %.ld,$$(bootblock-objs)) $$(nasm-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_common) $(LDFLAGS_x86) -static \ -o $@ -L$(obj) \ - $(filter %.o,$(bootblock-objs)) \ + $(filter %.o,$(bootblock-objs)) $(nasm-objs) \ -T $(obj)/arch/x86/bootblock.bootblock.ld \ +# +# Rules for turning NASM %. asm files into linkable %.o files +# +# Note that assembly files with the %.asm extension, are not automatically +# converted to a %.o in $(bootblock-objs). If we tried to do that, the generic +# rules would try to call the GNU compiler driver on the %.asm files. We do not +# want that, as GCC does not know how to handle them. Instead, we do this here, +# which allows us to maintain the logical separation. +# +nasm-objs = $(patsubst %.asm,%.o,$(filter %.asm,$(bootblock-objs))) + +$(obj)/%.bootblock.o: $(src)/%.asm $(obj)/config.h + @printf " NASM $(subst $(obj)/,,$(@))\n" + nasm -felf -o $@ $< endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64

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Patch set updated for coreboot: cpu/mtrr.h: Fix macro names for MTRR registers
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11761 -gerrit commit dc0736fa913df7dfa1439b981b08090c4763681e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Sep 30 20:23:09 2015 -0700 cpu/mtrr.h: Fix macro names for MTRR registers The old names are pathetic. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 8 +- src/cpu/amd/car/cache_as_ram.inc | 76 +++++++++---------- src/cpu/amd/car/disable_cache_as_ram.c | 10 +-- src/cpu/amd/model_fxx/model_fxx_init.c | 22 +++--- src/cpu/amd/pi/s3_resume.c | 8 +- src/cpu/amd/smm/smm_init.c | 6 +- src/cpu/intel/car/cache_as_ram.inc | 80 ++++++++++---------- src/cpu/intel/car/cache_as_ram_ht.inc | 46 ++++++------ src/cpu/intel/haswell/bootblock.c | 12 +-- src/cpu/intel/haswell/cache_as_ram.inc | 38 +++++----- src/cpu/intel/haswell/romstage.c | 8 +- src/cpu/intel/haswell/smmrelocate.c | 12 +-- src/cpu/intel/model_2065x/bootblock.c | 8 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 42 +++++------ src/cpu/intel/model_206ax/bootblock.c | 8 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 48 ++++++------ src/cpu/intel/model_6ex/cache_as_ram.inc | 38 +++++----- src/cpu/intel/smm/gen1/smmrelocate.c | 8 +- src/cpu/via/car/cache_as_ram.inc | 90 +++++++++++------------ src/cpu/x86/mp_init.c | 16 ++-- src/cpu/x86/mtrr/earlymtrr.c | 14 ++-- src/cpu/x86/mtrr/mtrr.c | 38 +++++----- src/drivers/intel/fsp1_1/cache_as_ram.inc | 8 +- src/include/cpu/x86/mtrr.h | 83 ++++++++++----------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 6 +- src/northbridge/intel/e7505/raminit.c | 6 +- src/northbridge/intel/nehalem/raminit.c | 12 +-- src/soc/intel/baytrail/bootblock/bootblock.c | 8 +- src/soc/intel/baytrail/cpu.c | 6 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 28 +++---- src/soc/intel/baytrail/romstage/romstage.c | 8 +- src/soc/intel/braswell/bootblock/bootblock.c | 8 +- src/soc/intel/braswell/cpu.c | 6 +- src/soc/intel/broadwell/bootblock/cpu.c | 12 +-- src/soc/intel/broadwell/include/soc/msr.h | 2 +- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 38 +++++----- src/soc/intel/broadwell/romstage/stack.c | 8 +- src/soc/intel/broadwell/smmrelocate.c | 12 +-- src/soc/intel/common/stack.c | 8 +- src/soc/intel/common/util.c | 50 ++++++------- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 8 +- src/soc/intel/fsp_baytrail/cpu.c | 6 +- src/soc/intel/skylake/bootblock/cpu.c | 14 ++-- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/msr.h | 2 +- src/soc/intel/skylake/smmrelocate.c | 12 +-- 46 files changed, 493 insertions(+), 496 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 98671f4..17364de 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -81,15 +81,15 @@ static void set_resume_cache(void) /* Enable caching for 0 - coreboot ram using variable mtrr */ msr.lo = 0 | MTRR_TYPE_WRBACK; msr.hi = 0; - wrmsr(MTRRphysBase_MSR(0), msr); - msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); /* Set the default memory type and disable fixed and enable variable MTRRs */ msr.hi = 0; msr.lo = (1 << 11); - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); enable_cache(); } diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 133daac..0b2bc60 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -76,9 +76,9 @@ cache_as_ram_setup: cvtsd2si %xmm3, %ebx /* Check if cpu_init_detected. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $MTRRdefTypeEn, %eax + andl $MTRR_DEF_TYPE_EN, %eax movl %eax, %ebx /* We store the status. */ jmp_if_k8(CAR_FAM10_out_post_errata) @@ -270,27 +270,27 @@ clear_fixed_var_mtrr_out: #if CacheSize > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx simplemask CacheSize, 0x8000 wrmsr #endif #if CacheSize > 0x10000 /* Enable caching for 64K-96K using fixed MTRR. */ - movl $MTRRfix4K_D0000_MSR, %ecx + movl $MTRR_FIX_4K_D0000, %ecx simplemask CacheSize, 0x10000 wrmsr #endif #if CacheSize > 0x18000 /* Enable caching for 96K-128K using fixed MTRR. */ - movl $MTRRfix4K_D8000_MSR, %ecx + movl $MTRR_FIX_4K_D8000, %ecx simplemask CacheSize, 0x18000 wrmsr #endif /* Enable caching for 0-32K using fixed MTRR. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx simplemask CacheSize, 0 wrmsr @@ -305,7 +305,7 @@ clear_fixed_var_mtrr_out: /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -316,19 +316,19 @@ clear_fixed_var_mtrr_out: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ jmp_if_k8(wbcache_post_fam10_setup) movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr /* Enable the MTRRs and IORRs in SYSCFG. */ @@ -462,35 +462,35 @@ cache_as_ram_switch_stack: all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000 /* var MTRR MSRs */ - .long MTRRphysBase_MSR(0) - .long MTRRphysMask_MSR(0) - .long MTRRphysBase_MSR(1) - .long MTRRphysMask_MSR(1) - .long MTRRphysBase_MSR(2) - .long MTRRphysMask_MSR(2) - .long MTRRphysBase_MSR(3) - .long MTRRphysMask_MSR(3) - .long MTRRphysBase_MSR(4) - .long MTRRphysMask_MSR(4) - .long MTRRphysBase_MSR(5) - .long MTRRphysMask_MSR(5) - .long MTRRphysBase_MSR(6) - .long MTRRphysMask_MSR(6) - .long MTRRphysBase_MSR(7) - .long MTRRphysMask_MSR(7) + .long MTRR_PHYS_BASE(0) + .long MTRR_PHYS_MASK(0) + .long MTRR_PHYS_BASE(1) + .long MTRR_PHYS_MASK(1) + .long MTRR_PHYS_BASE(2) + .long MTRR_PHYS_MASK(2) + .long MTRR_PHYS_BASE(3) + .long MTRR_PHYS_MASK(3) + .long MTRR_PHYS_BASE(4) + .long MTRR_PHYS_MASK(4) + .long MTRR_PHYS_BASE(5) + .long MTRR_PHYS_MASK(5) + .long MTRR_PHYS_BASE(6) + .long MTRR_PHYS_MASK(6) + .long MTRR_PHYS_BASE(7) + .long MTRR_PHYS_MASK(7) /* Variable IORR MTRR MSRs */ .long IORRBase_MSR(0) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index d3a3812..3b464b8 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -33,15 +33,15 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) msr.lo = 0; msr.hi = 0; - wrmsr(MTRRfix4K_C8000_MSR, msr); + wrmsr(MTRR_FIX_4K_C8000, msr); #if CONFIG_DCACHE_RAM_SIZE > 0x8000 - wrmsr(MTRRfix4K_C0000_MSR, msr); + wrmsr(MTRR_FIX_4K_C0000, msr); #endif #if CONFIG_DCACHE_RAM_SIZE > 0x10000 - wrmsr(MTRRfix4K_D0000_MSR, msr); + wrmsr(MTRR_FIX_4K_D0000, msr); #endif #if CONFIG_DCACHE_RAM_SIZE > 0x18000 - wrmsr(MTRRfix4K_D8000_MSR, msr); + wrmsr(MTRR_FIX_4K_D8000, msr); #endif /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ @@ -53,7 +53,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) msr.hi = 0; msr.lo = (1 << 11); - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); enable_cache(); } diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index a6561ee..268f1b2 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -105,12 +105,12 @@ static void save_mtrr_state(struct mtrr_state *state) { int i; for (i = 0; i < MTRR_COUNT; i++) { - state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i)); - state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i)); + state->mtrrs[i].base = rdmsr(MTRR_PHYS_BASE(i)); + state->mtrrs[i].mask = rdmsr(MTRR_PHYS_MASK(i)); } state->top_mem = rdmsr(TOP_MEM); state->top_mem2 = rdmsr(TOP_MEM2); - state->def_type = rdmsr(MTRRdefType_MSR); + state->def_type = rdmsr(MTRR_DEF_TYPE_MSR); } static void restore_mtrr_state(struct mtrr_state *state) @@ -119,12 +119,12 @@ static void restore_mtrr_state(struct mtrr_state *state) disable_cache(); for (i = 0; i < MTRR_COUNT; i++) { - wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base); - wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask); + wrmsr(MTRR_PHYS_BASE(i), state->mtrrs[i].base); + wrmsr(MTRR_PHYS_MASK(i), state->mtrrs[i].mask); } wrmsr(TOP_MEM, state->top_mem); wrmsr(TOP_MEM2, state->top_mem2); - wrmsr(MTRRdefType_MSR, state->def_type); + wrmsr(MTRR_DEF_TYPE_MSR, state->def_type); enable_cache(); } @@ -158,22 +158,22 @@ static void set_init_ecc_mtrrs(void) for (i = 0; i < MTRR_COUNT; i++) { msr_t zero; zero.lo = zero.hi = 0; - wrmsr(MTRRphysBase_MSR(i), zero); - wrmsr(MTRRphysMask_MSR(i), zero); + wrmsr(MTRR_PHYS_BASE(i), zero); + wrmsr(MTRR_PHYS_MASK(i), zero); } /* Write back cache the first 1MB */ msr.hi = 0x00000000; msr.lo = 0x00000000 | MTRR_TYPE_WRBACK; - wrmsr(MTRRphysBase_MSR(0), msr); + wrmsr(MTRR_PHYS_BASE(0), msr); msr.hi = 0x000000ff; msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800; - wrmsr(MTRRphysMask_MSR(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); /* Set the default type to write combining */ msr.hi = 0x00000000; msr.lo = 0xc00 | MTRR_TYPE_WRCOMB; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); /* Set TOP_MEM to 4G */ msr.hi = 0x00000001; diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 943fd97..88b5713 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -271,15 +271,15 @@ static void set_resume_cache(void) /* Enable caching for 0 - coreboot ram using variable mtrr */ msr.lo = 0 | MTRR_TYPE_WRBACK; msr.hi = 0; - wrmsr(MTRRphysBase_MSR(0), msr); - msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); /* Set the default memory type and disable fixed and enable variable MTRRs */ msr.hi = 0; msr.lo = (1 << 11); - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); enable_cache(); } diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 2e9a4c9..e13f24f 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -39,7 +39,7 @@ void smm_init(void) /* Back up MSRs for later restore */ syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR); + mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); /* MTRR changes don't like an enabled cache */ disable_cache(); @@ -57,7 +57,7 @@ void smm_init(void) /* set DRAM access to 0xa0000 */ msr.lo = 0x18181818; msr.hi = 0x18181818; - wrmsr(MTRRfix16K_A0000_MSR, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); /* enable the extended features */ msr = syscfg_orig; @@ -73,7 +73,7 @@ void smm_init(void) /* Restore SYSCFG and MTRR */ wrmsr(SYSCFG_MSR, syscfg_orig); - wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig); + wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); enable_cache(); /* CPU MSR are set in CPU init */ diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index f9be6e8..6ef8604 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -54,7 +54,7 @@ CacheAsRam: */ xorl %eax, %eax xorl %edx, %edx - movl $MTRRfix64K_00000_MSR, %ecx + movl $MTRR_FIX_64K_00000, %ecx wrmsr /* @@ -102,16 +102,16 @@ SIPI_Delay: /* Wait for the Logical AP to complete initialization. */ LogicalAP_SIPINotdone: - movl $MTRRfix64K_00000_MSR, %ecx + movl $MTRR_FIX_64K_00000, %ecx rdmsr orl %eax, %eax jz LogicalAP_SIPINotdone NotHtProcessor: /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr /* Clear all MTRRs. */ @@ -131,35 +131,35 @@ clear_fixed_var_mtrr: all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000 /* var MTRR MSRs */ - .long MTRRphysBase_MSR(0) - .long MTRRphysMask_MSR(0) - .long MTRRphysBase_MSR(1) - .long MTRRphysMask_MSR(1) - .long MTRRphysBase_MSR(2) - .long MTRRphysMask_MSR(2) - .long MTRRphysBase_MSR(3) - .long MTRRphysMask_MSR(3) - .long MTRRphysBase_MSR(4) - .long MTRRphysMask_MSR(4) - .long MTRRphysBase_MSR(5) - .long MTRRphysMask_MSR(5) - .long MTRRphysBase_MSR(6) - .long MTRRphysMask_MSR(6) - .long MTRRphysBase_MSR(7) - .long MTRRphysMask_MSR(7) + .long MTRR_PHYS_BASE(0) + .long MTRR_PHYS_MASK(0) + .long MTRR_PHYS_BASE(1) + .long MTRR_PHYS_MASK(1) + .long MTRR_PHYS_BASE(2) + .long MTRR_PHYS_MASK(2) + .long MTRR_PHYS_BASE(3) + .long MTRR_PHYS_MASK(3) + .long MTRR_PHYS_BASE(4) + .long MTRR_PHYS_MASK(4) + .long MTRR_PHYS_BASE(5) + .long MTRR_PHYS_MASK(5) + .long MTRR_PHYS_BASE(6) + .long MTRR_PHYS_MASK(6) + .long MTRR_PHYS_BASE(7) + .long MTRR_PHYS_MASK(7) .long 0x000 /* NULL, end of table */ @@ -219,13 +219,13 @@ clear_fixed_var_mtrr_out: #if CacheSize > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx simplemask CacheSize, 0x8000 wrmsr #endif /* Enable caching for 0-32K using fixed MTRR. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx simplemask CacheSize, 0 wrmsr @@ -235,7 +235,7 @@ clear_fixed_var_mtrr_out: * Enable write base caching so we can do execute in place (XIP) * on the flash ROM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -246,9 +246,9 @@ clear_fixed_var_mtrr_out: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -332,13 +332,13 @@ lout: movl %eax, %cr0 /* Clear sth. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx xorl %edx, %edx xorl %eax, %eax wrmsr #if CONFIG_DCACHE_RAM_SIZE > 0x8000 - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx wrmsr #endif @@ -346,9 +346,9 @@ lout: * Set the default memory type and disable fixed * and enable variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr /* Enable cache. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 193ad41..6eb50ba 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -61,7 +61,7 @@ clear_mtrrs: post_code(0x21) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -95,9 +95,9 @@ addrsize_no_MSR: */ addrsize_set_high: xorl %eax, %eax - movl $MTRRphysMask_MSR(0), %ecx + movl $MTRR_PHYS_MASK(0), %ecx wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx wrmsr movl $LAPIC_BASE_MSR, %ecx not %edx @@ -188,7 +188,7 @@ hyper_threading_cpu: post_code(0x26) /* Wait for sibling CPU to start. */ -1: movl $(MTRRphysBase_MSR(0)), %ecx +1: movl $(MTRR_PHYS_BASE(0)), %ecx rdmsr andl %eax, %eax jnz sipi_complete @@ -211,7 +211,7 @@ ap_init: post_code(0x28) /* MTRR registers are shared between HT siblings. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(1<<12), %eax xorl %edx, %edx wrmsr @@ -230,21 +230,21 @@ sipi_complete: post_code(0x2a) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx + movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x2b) @@ -308,7 +308,7 @@ no_msr_11e: #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -319,9 +319,9 @@ no_msr_11e: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -356,9 +356,9 @@ no_msr_11e: post_code(0x34) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x35) @@ -382,24 +382,24 @@ no_msr_11e: post_code(0x38) /* Enable Write Back and Speculative Reads for low RAM. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(0), %ecx + movl $MTRR_PHYS_MASK(0), %ecx rdmsr - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #if CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #endif @@ -413,9 +413,9 @@ no_msr_11e: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index f5d0f6c..8d0c53c 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -44,10 +44,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void set_flex_ratio_to_tdp_nominal(void) @@ -113,12 +113,12 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); /* Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); halt(); diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0978bfb..b8df2a1 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -73,31 +73,31 @@ clear_mtrrs: post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -134,7 +134,7 @@ clear_mtrrs: movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -145,19 +145,19 @@ clear_mtrrs: orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x27) /* Enable caching for ram init code to run faster */ - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(2), %ecx - movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(2), %ecx + movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr @@ -197,9 +197,9 @@ before_romstage: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -220,9 +220,9 @@ before_romstage: /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx wrmsr - movl $MTRRphysMask_MSR(2), %ecx + movl $MTRR_PHYS_MASK(2), %ecx wrmsr post_code(0x33) @@ -246,7 +246,7 @@ before_romstage: /* Get number of MTRRs. */ popl %ebx - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx 1: testl %ebx, %ebx jz 1f @@ -279,9 +279,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9c238ca..3bb1090 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -117,14 +117,14 @@ static void *setup_romstage_stack_after_car(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -135,7 +135,7 @@ static void *setup_romstage_stack_after_car(void) * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -146,7 +146,7 @@ static void *setup_romstage_stack_after_car(void) * to cacheable it provides faster access when relocating the SMM * handler as well as using the TSEG region for other purposes. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index ab94f9a..00e2d55 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -73,8 +73,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); - wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); + wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_emrr(struct smm_relocation_params *relo_params) @@ -214,7 +214,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) update_save_state(cpu, relo_params, runtime); /* Write EMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRRcap_MSR); + mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -272,7 +272,7 @@ static void fill_in_relocation_params(struct device *dev, /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -283,14 +283,14 @@ static void fill_in_relocation_params(struct device *dev, * on the number of physical address bits supported. */ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ params->uncore_emrr_base.lo = emrr_base; params->uncore_emrr_base.hi = 0; params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRRphysMaskValid; + MTRR_PHYS_MASK_VALID; params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index b6a2442..edffe14 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -43,10 +43,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -60,7 +60,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index cfa3b6b..f36af2b 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -48,8 +48,8 @@ wait_for_sipi: jc wait_for_sipi post_code(0x21) - /* Clean-up MTRRdefType_MSR. */ - movl $MTRRdefType_MSR, %ecx + /* Clean-up MTRR_DEF_TYPE_MSR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr @@ -69,7 +69,7 @@ clear_mtrrs: jnz clear_mtrrs /* Zero out all variable range MTRRs. */ - movl $MTRRcap_MSR, %ecx + movl $MTRR_CAP_MSR, %ecx rdmsr andl $0xff, %eax shl $1, %eax @@ -85,24 +85,24 @@ clear_var_mtrrs: post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -139,7 +139,7 @@ clear_var_mtrrs: movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -150,9 +150,9 @@ clear_var_mtrrs: orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x27) @@ -189,9 +189,9 @@ before_romstage: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -228,12 +228,12 @@ before_romstage: /* Enable Write Back and Speculative Reads for the first MB * and ramstage. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr @@ -241,12 +241,12 @@ before_romstage: /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(1), %ecx + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif @@ -261,9 +261,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index d41afb2..416b484 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -44,10 +44,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a3f1c64..04c0808 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -68,31 +68,31 @@ clear_mtrrs: post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -129,7 +129,7 @@ clear_mtrrs: movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -140,19 +140,19 @@ clear_mtrrs: orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x27) /* Enable caching for ram init code to run faster */ - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(2), %ecx - movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(2), %ecx + movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr @@ -189,9 +189,9 @@ before_romstage: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -212,9 +212,9 @@ before_romstage: /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx wrmsr - movl $MTRRphysMask_MSR(2), %ecx + movl $MTRR_PHYS_MASK(2), %ecx wrmsr post_code(0x33) @@ -236,12 +236,12 @@ before_romstage: /* Enable Write Back and Speculative Reads for the first MB * and ramstage. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr @@ -249,12 +249,12 @@ before_romstage: /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(1), %ecx + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif @@ -269,9 +269,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 271b756..16244fb 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -52,27 +52,27 @@ clear_mtrrs: jnz clear_mtrrs /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable L2 cache. */ @@ -102,7 +102,7 @@ clear_mtrrs: #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -113,9 +113,9 @@ clear_mtrrs: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -150,9 +150,9 @@ clear_mtrrs: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -176,23 +176,23 @@ clear_mtrrs: post_code(0x38) /* Enable Write Back and Speculative Reads for low RAM. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #if CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(1), %ecx + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif @@ -207,9 +207,9 @@ clear_mtrrs: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index bc14444..41ec39c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -63,8 +63,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); - wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); + wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); } /* The relocation work is actually performed in SMM context, but the code @@ -109,7 +109,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) save_state->smbase, save_state->iedbase, save_state); /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRRcap_MSR); + mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -142,7 +142,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; } diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index e8a4ee2..cc91c6e 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -44,9 +44,9 @@ CacheAsRam: invd /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr /* Clear all MTRRs. */ @@ -66,55 +66,55 @@ clear_fixed_var_mtrr: all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000 /* var MTRR MSRs */ - .long MTRRphysBase_MSR(0) - .long MTRRphysMask_MSR(0) - .long MTRRphysBase_MSR(1) - .long MTRRphysMask_MSR(1) - .long MTRRphysBase_MSR(2) - .long MTRRphysMask_MSR(2) - .long MTRRphysBase_MSR(3) - .long MTRRphysMask_MSR(3) - .long MTRRphysBase_MSR(4) - .long MTRRphysMask_MSR(4) - .long MTRRphysBase_MSR(5) - .long MTRRphysMask_MSR(5) - .long MTRRphysBase_MSR(6) - .long MTRRphysMask_MSR(6) - .long MTRRphysBase_MSR(7) - .long MTRRphysMask_MSR(7) + .long MTRR_PHYS_BASE(0) + .long MTRR_PHYS_MASK(0) + .long MTRR_PHYS_BASE(1) + .long MTRR_PHYS_MASK(1) + .long MTRR_PHYS_BASE(2) + .long MTRR_PHYS_MASK(2) + .long MTRR_PHYS_BASE(3) + .long MTRR_PHYS_MASK(3) + .long MTRR_PHYS_BASE(4) + .long MTRR_PHYS_MASK(4) + .long MTRR_PHYS_BASE(5) + .long MTRR_PHYS_MASK(5) + .long MTRR_PHYS_BASE(6) + .long MTRR_PHYS_MASK(6) + .long MTRR_PHYS_BASE(7) + .long MTRR_PHYS_MASK(7) .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx xorl %edx, %edx movl $(CacheBase | MTRR_TYPE_WRBACK), %eax wrmsr - movl $MTRRphysMask_MSR(0), %ecx + movl $MTRR_PHYS_MASK(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f, %edx - movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax + movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* * Enable write base caching so we can do execute in place (XIP) * on the flash ROM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -125,16 +125,16 @@ clear_fixed_var_mtrr_out: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Set the default memory type and enable fixed and variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn), %eax + movl $(MTRR_DEF_TYPE_EN), %eax wrmsr /* Enable cache. */ @@ -224,24 +224,24 @@ testok: /* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn), %eax + movl $(MTRR_DEF_TYPE_EN), %eax wrmsr /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx xorl %edx, %edx movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax wrmsr - movl $MTRRphysMask_MSR(0), %ecx + movl $MTRR_PHYS_MASK(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Cache XIP_ROM area to speedup coreboot code. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -252,9 +252,9 @@ testok: orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Enable cache. */ diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3c8450f..c72cf0a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -179,10 +179,10 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp) #define NUM_FIXED_MTRRS 11 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, - MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, - MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, + MTRR_FIX_64K_00000, MTRR_FIX_16K_80000, MTRR_FIX_16K_A0000, + MTRR_FIX_4K_C0000, MTRR_FIX_4K_C8000, MTRR_FIX_4K_D0000, + MTRR_FIX_4K_D8000, MTRR_FIX_4K_E0000, MTRR_FIX_4K_E8000, + MTRR_FIX_4K_F0000, MTRR_FIX_4K_F8000, }; static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) @@ -208,7 +208,7 @@ static int save_bsp_msrs(char *start, int size) msr_t msr; /* Determine number of MTRRs need to be saved. */ - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); num_var_mtrrs = msr.lo & 0xff; /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */ @@ -225,11 +225,11 @@ static int save_bsp_msrs(char *start, int size) } for (i = 0; i < num_var_mtrrs; i++) { - msr_entry = save_msr(MTRRphysBase_MSR(i), msr_entry); - msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry); + msr_entry = save_msr(MTRR_PHYS_BASE(i), msr_entry); + msr_entry = save_msr(MTRR_PHYS_MASK(i), msr_entry); } - msr_entry = save_msr(MTRRdefType_MSR, msr_entry); + msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry); return msr_count; } diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 9561d8d..2e31a6e 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -13,10 +13,10 @@ void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } #if !IS_ENABLED(CONFIG_CACHE_AS_RAM) @@ -36,7 +36,7 @@ const int addr_det = 0; static void do_early_mtrr_init(const unsigned long *mtrr_msrs) { /* Precondition: - * The cache is not enabled in cr0 nor in MTRRdefType_MSR + * The cache is not enabled in cr0 nor in MTRR_DEF_TYPE_MSR * entry32.inc ensures the cache is not enabled in cr0 */ msr_t msr; @@ -65,7 +65,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } @@ -99,7 +99,7 @@ static inline int early_mtrr_init_detected(void) * on both Intel and AMD cpus, at least * according to the documentation. */ - msr = rdmsr(MTRRdefType_MSR); - return msr.lo & MTRRdefTypeEn; + msr = rdmsr(MTRR_DEF_TYPE_MSR); + return msr.lo & MTRR_DEF_TYPE_EN; } #endif diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 1994a56..072b887 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -64,7 +64,7 @@ static void detect_var_mtrrs(void) { msr_t msr; - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); total_mtrrs = msr.lo & 0xff; @@ -81,19 +81,19 @@ void enable_fixed_mtrr(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); - msr.lo |= MTRRdefTypeEn | MTRRdefTypeFixEn; - wrmsr(MTRRdefType_MSR, msr); + msr = rdmsr(MTRR_DEF_TYPE_MSR); + msr.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void enable_var_mtrr(unsigned char deftype) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); msr.lo &= ~0xff; - msr.lo |= MTRRdefTypeEn | deftype; - wrmsr(MTRRdefType_MSR, msr); + msr.lo |= MTRR_DEF_TYPE_EN | deftype; + wrmsr(MTRR_DEF_TYPE_MSR, msr); } /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ @@ -250,11 +250,11 @@ static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; /* Fixed MTRR descriptors. */ static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { { PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000), - PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRRfix64K_00000_MSR }, + PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRR_FIX_64K_00000 }, { PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000), - PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRRfix16K_80000_MSR }, + PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRR_FIX_16K_80000 }, { PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000), - PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRRfix4K_C0000_MSR }, + PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRR_FIX_4K_C0000 }, }; static void calc_fixed_mtrrs(void) @@ -410,9 +410,9 @@ static void clear_var_mtrr(int index) { msr_t msr_val; - msr_val = rdmsr(MTRRphysMask_MSR(index)); - msr_val.lo &= ~MTRRphysMaskValid; - wrmsr(MTRRphysMask_MSR(index), msr_val); + msr_val = rdmsr(MTRR_PHYS_MASK(index)); + msr_val.lo &= ~MTRR_PHYS_MASK_VALID; + wrmsr(MTRR_PHYS_MASK(index), msr_val); } static void prep_var_mtrr(struct var_mtrr_state *var_state, @@ -453,7 +453,7 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state, regs->base.hi = rbase >> 32; regs->mask.lo = rsize; - regs->mask.lo |= MTRRphysMaskValid; + regs->mask.lo |= MTRR_PHYS_MASK_VALID; regs->mask.hi = rsize >> 32; } @@ -772,8 +772,8 @@ static void commit_var_mtrrs(const struct var_mtrr_solution *sol) /* Write out the variable MTRRs. */ disable_cache(); for (i = 0; i < sol->num_used; i++) { - wrmsr(MTRRphysBase_MSR(i), sol->regs[i].base); - wrmsr(MTRRphysMask_MSR(i), sol->regs[i].mask); + wrmsr(MTRR_PHYS_BASE(i), sol->regs[i].base); + wrmsr(MTRR_PHYS_MASK(i), sol->regs[i].mask); } /* Clear the ones that are unused. */ for (; i < total_mtrrs; i++) @@ -818,16 +818,16 @@ void x86_mtrr_check(void) msr_t msr; printk(BIOS_DEBUG, "\nMTRR check\n"); - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "Fixed MTRRs : "); - if (msr.lo & MTRRdefTypeFixEn) + if (msr.lo & MTRR_DEF_TYPE_FIX_EN) printk(BIOS_DEBUG, "Enabled\n"); else printk(BIOS_DEBUG, "Disabled\n"); printk(BIOS_DEBUG, "Variable MTRRs: "); - if (msr.lo & MTRRdefTypeEn) + if (msr.lo & MTRR_DEF_TYPE_EN) printk(BIOS_DEBUG, "Enabled\n"); else printk(BIOS_DEBUG, "Disabled\n"); diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index d4df67b..dc7b173 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -210,7 +210,7 @@ before_romstage: /* Clear all of the variable MTRRs. */ popl %ebx - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx clr %eax clr %edx @@ -227,7 +227,7 @@ before_romstage: 1: /* Get number of MTRRs. */ popl %ebx - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx 2: testl %ebx, %ebx jz 2f @@ -260,9 +260,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bd0b603..8fd4261 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -2,49 +2,46 @@ #define CPU_X86_MTRR_H /* These are the region types */ -#define MTRR_TYPE_UNCACHEABLE 0 -#define MTRR_TYPE_WRCOMB 1 -/*#define MTRR_TYPE_ 2*/ -/*#define MTRR_TYPE_ 3*/ -#define MTRR_TYPE_WRTHROUGH 4 -#define MTRR_TYPE_WRPROT 5 -#define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 - -#define MTRRcap_MSR 0x0fe - -#define MTRRcapSmrr (1 << 11) -#define MTRRcapWc (1 << 10) -#define MTRRcapFix (1 << 8) -#define MTRRcapVcnt 0xff - -#define MTRRdefType_MSR 0x2ff - -#define MTRRdefTypeEn (1 << 11) -#define MTRRdefTypeFixEn (1 << 10) -#define MTRRdefTypeType 0xff - -#define SMRRphysBase_MSR 0x1f2 -#define SMRRphysMask_MSR 0x1f3 - -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) - -#define MTRRphysMaskValid (1 << 11) - -#define NUM_FIXED_RANGES 88 -#define RANGES_PER_FIXED_MTRR 8 -#define MTRRfix64K_00000_MSR 0x250 -#define MTRRfix16K_80000_MSR 0x258 -#define MTRRfix16K_A0000_MSR 0x259 -#define MTRRfix4K_C0000_MSR 0x268 -#define MTRRfix4K_C8000_MSR 0x269 -#define MTRRfix4K_D0000_MSR 0x26a -#define MTRRfix4K_D8000_MSR 0x26b -#define MTRRfix4K_E0000_MSR 0x26c -#define MTRRfix4K_E8000_MSR 0x26d -#define MTRRfix4K_F0000_MSR 0x26e -#define MTRRfix4K_F8000_MSR 0x26f +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +#define MTRR_NUM_TYPES 7 + +#define MTRR_CAP_MSR 0x0fe + +#define MTRR_CAP_SMRR (1 << 11) +#define MTRR_CAP_WC (1 << 10) +#define MTRR_CAP_FIX (1 << 8) +#define MTRR_CAP_VCNT 0xff + +#define MTRR_DEF_TYPE_MSR 0x2ff +#define MTRR_DEF_TYPE_MASK 0xff +#define MTRR_DEF_TYPE_EN (1 << 11) +#define MTRR_DEF_TYPE_FIX_EN (1 << 10) + + +#define SMRR_PHYS_BASE 0x1f2 +#define SMRR_PHYS_MASK 0x1f3 + +#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) +#define MTRR_PHYS_MASK_VALID (1 << 11) + +#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 +#define MTRR_FIX_64K_00000 0x250 +#define MTRR_FIX_16K_80000 0x258 +#define MTRR_FIX_16K_A0000 0x259 +#define MTRR_FIX_4K_C0000 0x268 +#define MTRR_FIX_4K_C8000 0x269 +#define MTRR_FIX_4K_D0000 0x26a +#define MTRR_FIX_4K_D8000 0x26b +#define MTRR_FIX_4K_E0000 0x26c +#define MTRR_FIX_4K_E8000 0x26d +#define MTRR_FIX_4K_F0000 0x26e +#define MTRR_FIX_4K_F8000 0x26f #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 609cddf..59a5fef 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1634,13 +1634,13 @@ static void set_var_mtrr_dqs( zero.lo = zero.hi = 0; /* The invalid bit is kept in the mask, so we simply clear the relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); + wrmsr (MTRR_PHYS_MASK(reg), zero); } else { /* Bit 32-35 of MTRRphysMask should be set to 1 */ base.lo |= type; mask.lo |= 0x800; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); + wrmsr (MTRR_PHYS_BASE(reg), base); + wrmsr (MTRR_PHYS_MASK(reg), mask); } } diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index fc715bc..b48328f 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -986,10 +986,10 @@ static inline void __attribute__((always_inline)) */ /* Disable and invalidate all cache. */ - msr_t xip_mtrr = rdmsr(MTRRphysMask_MSR(1)); - xip_mtrr.lo &= ~MTRRphysMaskValid; + msr_t xip_mtrr = rdmsr(MTRR_PHYS_MASK(1)); + xip_mtrr.lo &= ~MTRR_PHYS_MASK_VALID; invd(); - wrmsr(MTRRphysMask_MSR(1), xip_mtrr); + wrmsr(MTRR_PHYS_MASK(1), xip_mtrr); invd(); RAM_DEBUG_MESSAGE("ECC state initialized.\n"); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c41310a..232a15a 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -2066,8 +2066,8 @@ static void disable_cache(void) { msr_t msr = {.lo = 0, .hi = 0 }; - wrmsr(MTRRphysBase_MSR(3), msr); - wrmsr(MTRRphysMask_MSR(3), msr); + wrmsr(MTRR_PHYS_BASE(3), msr); + wrmsr(MTRR_PHYS_MASK(3), msr); } static void enable_cache(unsigned int base, unsigned int size) @@ -2075,11 +2075,11 @@ static void enable_cache(unsigned int base, unsigned int size) msr_t msr; msr.lo = base | MTRR_TYPE_WRPROT; msr.hi = 0; - wrmsr(MTRRphysBase_MSR(3), msr); - msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn) + wrmsr(MTRR_PHYS_BASE(3), msr); + msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN) & 0xffffffff); msr.hi = 0x0000000f; - wrmsr(MTRRphysMask_MSR(3), msr); + wrmsr(MTRR_PHYS_MASK(3), msr); } static void flush_cache(u32 start, u32 size) @@ -4017,7 +4017,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc); #if !REAL - rdmsr (MTRRphysMask_MSR (3)); + rdmsr (MTRR_PHYS_MASK (3)); #endif collect_system_info(&info); diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 6d31add..f73ac46 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -29,10 +29,10 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -47,7 +47,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void setup_mmconfig(void) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 6b84c59..81e04ba 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -197,10 +197,10 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRRphysBase_MSR, smrr); + wrmsr(SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRRphysMask_MSR, smrr); + wrmsr(SMRR_PHYS_MASK, smrr); /* The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state @@ -264,7 +264,7 @@ static int smm_load_handlers(void) relo_attrs.smbase = (uint32_t)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRRphysMaskValid; + relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 583ec58..2106029 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Configure the default memory type to uncacheable as well as disable * fixed and variable range mtrrs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -95,34 +95,34 @@ wait_for_sipi: post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Set code caching up for romstage. */ - movl $(MTRRphysBase_MSR(1)), %ecx + movl $(MTRR_PHYS_BASE(1)), %ecx movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $(MTRRphysMask_MSR(1)), %ecx - movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(1)), %ecx + movl $(CODE_CACHE_MASK | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x26) @@ -198,9 +198,9 @@ before_romstage: post_code(0x2c) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr invd @@ -225,7 +225,7 @@ before_romstage: /* Get number of MTRRs. */ popl %ebx - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx 1: testl %ebx, %ebx jz 1f @@ -258,9 +258,9 @@ before_romstage: post_code(0x30) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x31) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index c7f66bb..81978b4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -311,14 +311,14 @@ static void *setup_stack_and_mttrs(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -329,7 +329,7 @@ static void *setup_stack_and_mttrs(void) * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -340,7 +340,7 @@ static void *setup_stack_and_mttrs(void) * provides faster access when relocating the SMM handler as well * as using the TSEG region for other purposes. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index f98f694..ca19210 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -30,10 +30,10 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -48,7 +48,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void setup_mmconfig(void) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 2ab8725..41a43ee 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -206,10 +206,10 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRRphysBase_MSR, smrr); + wrmsr(SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRRphysMask_MSR, smrr); + wrmsr(SMRR_PHYS_MASK, smrr); /* * The relocated handler runs with all CPUs concurrently. Therefore @@ -284,7 +284,7 @@ static int smm_load_handlers(void) relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRRphysMaskValid; + relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 83bd873..6e9d3a5 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -36,10 +36,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -54,7 +54,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void bootblock_mdelay(int ms) @@ -120,12 +120,12 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); /* Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); halt(); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 914a11f..7ed61f4 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -102,7 +102,7 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -/* MTRRcap_MSR bits */ +/* MTRR_CAP_MSR bits */ #define SMRR_SUPPORTED (1<<11) #define EMRR_SUPPORTED (1<<12) diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 3f1b12a..8359e4a 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -76,31 +76,31 @@ clear_mtrrs: post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -136,7 +136,7 @@ clear_mtrrs: movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -147,19 +147,19 @@ clear_mtrrs: orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x27) /* Enable caching for ram init code to run faster */ - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(2), %ecx - movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(2), %ecx + movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr @@ -217,9 +217,9 @@ before_romstage: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -240,9 +240,9 @@ before_romstage: /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx - movl $MTRRphysBase_MSR(2), %ecx + movl $MTRR_PHYS_BASE(2), %ecx wrmsr - movl $MTRRphysMask_MSR(2), %ecx + movl $MTRR_PHYS_MASK(2), %ecx wrmsr post_code(0x33) @@ -266,7 +266,7 @@ before_romstage: /* Get number of MTRRs. */ popl %ebx - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx 1: testl %ebx, %ebx jz 1f @@ -299,9 +299,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index ed8e9c3..e66ce75 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -82,14 +82,14 @@ void *setup_stack_and_mttrs(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -100,7 +100,7 @@ void *setup_stack_and_mttrs(void) * this area as cacheable so it can be used later for ramstage before * setting up the entire RAM as cacheable. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -111,7 +111,7 @@ void *setup_stack_and_mttrs(void) * provides faster access when relocating the SMM handler as well * as using the TSEG region for other purposes. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index f4525da..4d595f1 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -42,8 +42,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); - wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); + wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_emrr(struct smm_relocation_params *relo_params) @@ -183,7 +183,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) update_save_state(cpu, relo_params, runtime); /* Write EMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRRcap_MSR); + mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); @@ -241,7 +241,7 @@ static void fill_in_relocation_params(device_t dev, /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -252,14 +252,14 @@ static void fill_in_relocation_params(device_t dev, * on the number of physical address bits supported. */ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ params->uncore_emrr_base.lo = emrr_base; params->uncore_emrr_base.hi = 0; params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRRphysMaskValid; + MTRR_PHYS_MASK_VALID; params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; } diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c index 45e61f9..6cf03f2 100644 --- a/src/soc/intel/common/stack.c +++ b/src/soc/intel/common/stack.c @@ -95,7 +95,7 @@ void *setup_stack_and_mtrrs(void) /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -133,7 +133,7 @@ void *setup_stack_and_mtrrs(void) * of the FSP reserved memory region. */ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -152,7 +152,7 @@ void *setup_stack_and_mtrrs(void) smm_region(&smm_base, &smm_size); tseg_base = (uint32_t)smm_base; slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); num_mtrrs++; @@ -160,7 +160,7 @@ void *setup_stack_and_mtrrs(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index a6adfaf..591c100 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -77,10 +77,10 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr) msr_t s; } mttrcap; - mttrcap.s = rdmsr(MTRRcap_MSR); + mttrcap.s = rdmsr(MTRR_CAP_MSR); if (msr != NULL) *msr = mttrcap.u64; - return mttrcap.u64 & MTRRcapVcnt; + return mttrcap.u64 & MTRR_CAP_VCNT; } static const char *soc_display_mtrr_type(uint32_t type) @@ -105,13 +105,13 @@ static void soc_display_mtrr_fixed_types(uint64_t msr, uint32_t next_type; uint32_t type; - type = msr & MTRRdefTypeType; + type = msr & MTRR_DEF_TYPE_MASK; base_address = starting_address; next_address = base_address; for (index = 0; index < 64; index += 8) { next_address = starting_address + (memory_size * ((index >> 3) + 1)); - next_type = (msr >> index) & MTRRdefTypeType; + next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; if (next_type != type) { printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", base_address, next_address - 1, @@ -159,7 +159,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = rdmsr(MTRRfix64K_00000_MSR); + msr.s = rdmsr(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -173,9 +173,9 @@ static uint32_t soc_display_mtrrcap(void) printk(BIOS_DEBUG, "0x%016llx: IA32_MTRRCAP: %s%s%s%d variable MTRRs\n", msr, - (msr & MTRRcapSmrr) ? "SMRR, " : "", - (msr & MTRRcapWc) ? "WC, " : "", - (msr & MTRRcapFix) ? "FIX, " : "", + (msr & MTRR_CAP_SMRR) ? "SMRR, " : "", + (msr & MTRR_CAP_WC) ? "WC, " : "", + (msr & MTRR_CAP_FIX) ? "FIX, " : "", variable_mtrrs); return variable_mtrrs; } @@ -187,12 +187,12 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = rdmsr(MTRRdefType_MSR); + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, - (msr.u64 & MTRRdefTypeEn) ? " E," : "", - (msr.u64 & MTRRdefTypeFixEn) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & MTRRdefTypeType))); + (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", + (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", + soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); } static void soc_display_variable_mtrr(uint32_t msr_reg, int index, @@ -212,13 +212,13 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_a.s = rdmsr(msr_reg); msr_m.s = rdmsr(msr_reg + 1); - if (msr_m.u64 & MTRRphysMaskValid) { + if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", msr_a.u64, index, base_address, - soc_display_mtrr_type(msr_a.u64 & MTRRdefTypeType)); + soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; length = (~mask & address_mask) + 1; printk(BIOS_DEBUG, @@ -243,32 +243,32 @@ asmlinkage void soc_display_mtrrs(void) variable_mtrrs = soc_display_mtrrcap(); soc_display_mtrr_def_type(); soc_display_64k_mtrr(); - soc_display_16k_mtrr(MTRRfix16K_80000_MSR, 0x80000, + soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000"); - soc_display_16k_mtrr(MTRRfix16K_A0000_MSR, 0xa0000, + soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000"); - soc_display_4k_mtrr(MTRRfix4K_C0000_MSR, 0xc0000, + soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000"); - soc_display_4k_mtrr(MTRRfix4K_C8000_MSR, 0xc8000, + soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000"); - soc_display_4k_mtrr(MTRRfix4K_D0000_MSR, 0xd0000, + soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000"); - soc_display_4k_mtrr(MTRRfix4K_D8000_MSR, 0xd8000, + soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000"); - soc_display_4k_mtrr(MTRRfix4K_E0000_MSR, 0xe0000, + soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000"); - soc_display_4k_mtrr(MTRRfix4K_E8000_MSR, 0xe8000, + soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000"); - soc_display_4k_mtrr(MTRRfix4K_F0000_MSR, 0xf0000, + soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000"); - soc_display_4k_mtrr(MTRRfix4K_F8000_MSR, 0xf8000, + soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000"); address_bits = cpu_phys_address_size(); address_mask = (1ULL << address_bits) - 1; /* Display the variable MTRRs */ for (i = 0; i < variable_mtrrs; i++) - soc_display_variable_mtrr(MTRRphysBase_MSR(i), i, + soc_display_variable_mtrr(MTRR_PHYS_BASE(i), i, address_mask); } } diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 50d321b..41b911e 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -52,10 +52,10 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } /* @@ -80,7 +80,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void setup_mmconfig(void) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index c7ee582..8fe1df3 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -173,10 +173,10 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRRphysBase_MSR, smrr); + wrmsr(SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRRphysMask_MSR, smrr); + wrmsr(SMRR_PHYS_MASK, smrr); /* The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state @@ -243,7 +243,7 @@ static int smm_load_handlers(void) relo_attrs.smbase = (uint32_t)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRRphysMaskValid; + relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6c5ab4f..b1cdee5 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -44,10 +44,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void bootblock_mdelay(int ms) @@ -167,14 +167,14 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); /* * Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) soft_reset(); } @@ -194,7 +194,7 @@ static void patch_microcode(void) * MTRRCAP[12]. Check for this feature and avoid reloading the * same microcode during early cpu initialization. */ - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1f26093..0abfa80 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -582,6 +582,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * MTRRCAP[12]. Check for this feature and avoid reloading the * same microcode during cpu initialization. */ - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4239b36..d514231 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -103,7 +103,7 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -/* MTRRcap_MSR bits */ +/* MTRR_CAP_MSR bits */ #define SMRR_SUPPORTED (1<<11) #define PRMRR_SUPPORTED (1<<12) diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 4b6f1c4..8d2c545 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -44,8 +44,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); - wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); + wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); } static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) @@ -191,7 +191,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) update_save_state(cpu, relo_params, runtime); /* Write EMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRRcap_MSR); + mtrr_cap = rdmsr(MTRR_CAP_MSR); if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } @@ -230,7 +230,7 @@ static void fill_in_relocation_params(device_t dev, /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -243,14 +243,14 @@ static void fill_in_relocation_params(device_t dev, */ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; params->emrr_base.hi = 0; - params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ params->uncore_emrr_base.lo = emrr_base; params->uncore_emrr_base.hi = 0; params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRRphysMaskValid; + MTRR_PHYS_MASK_VALID; params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; }

1 0

New patch to review for coreboot: arch/x86/bootblock: Do not include non-code files in bootblock.S
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11792 -gerrit commit 8df4298bb93bd4a5f68aa1f2c6ac5c8ff405c237 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Oct 4 17:47:36 2015 -0700 arch/x86/bootblock: Do not include non-code files in bootblock.S Since we can now link the bootblock, it no longer makes sense to use a monolithic bootblock.S. Code segments must still be included as the order in bootblock.S determines code flow. However, we can now link data or descriptor parts, such as id.inc, or fit.inc. Change-Id: I08e86e92d82bd2138194ed42652f268b0764aa54 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/bootblock.S | 5 ----- src/arch/x86/id.S | 20 ++++++++++++++++++++ src/arch/x86/id.inc | 20 -------------------- src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/fit/Makefile.inc | 1 + src/cpu/intel/fit/fit.S | 30 ++++++++++++++++++++++++++++++ src/cpu/intel/fit/fit.inc | 30 ------------------------------ 8 files changed, 53 insertions(+), 55 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 95ebb6a..e17fe11 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -84,6 +84,7 @@ endif # Add the assembly file that pulls in the rest of the dependencies in # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. +bootblock-y += id.S bootblock-y += bootblock.S bootblock-y += walkcbfs.S $(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S index bea178d..645e491 100644 --- a/src/arch/x86/bootblock.S +++ b/src/arch/x86/bootblock.S @@ -25,11 +25,6 @@ #include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> -#include <arch/x86/id.inc> - -#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.inc> -#endif #ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE #include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S new file mode 100644 index 0000000..a3df25e --- /dev/null +++ b/src/arch/x86/id.S @@ -0,0 +1,20 @@ +#include <build.h> + + .section ".id", "a", @progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ +.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ +.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc deleted file mode 100644 index a3df25e..0000000 --- a/src/arch/x86/id.inc +++ /dev/null @@ -1,20 +0,0 @@ -#include <build.h> - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 6f07e30..904aa5d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -3,6 +3,7 @@ # # Therefore: ONLY include Makefile.inc from socket directories! +subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc new file mode 100644 index 0000000..4b540ba --- /dev/null +++ b/src/cpu/intel/fit/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += fit.S diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S new file mode 100644 index 0000000..e4595c0 --- /dev/null +++ b/src/cpu/intel/fit/fit.S @@ -0,0 +1,30 @@ +.section ".fit_pointer", "a", @progbits + .code32 +.global fit_pointer +fit_pointer: +.long fit_table +.long 0 +.previous + +.section ".rom.data", "a", @progbits +.align 16 +.global fit_table +.global fit_table_end +fit_table: +/* Address for type 0 is '_FIT_ ' */ +.long 0x5449465f +.long 0x2020205f +/* + * There is 1 entry in the table. Other tools will have to update the size + * and checksum when adding entries. + */ +.long 0x00000001 +/* Version */ +.word 0x0100 +/* Type 0 with checksum valid. */ +.byte 0x80 +/* Checksum byte - must add to zero. */ +.byte 0x7d +.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 +fit_table_end: +.previous diff --git a/src/cpu/intel/fit/fit.inc b/src/cpu/intel/fit/fit.inc deleted file mode 100644 index e4595c0..0000000 --- a/src/cpu/intel/fit/fit.inc +++ /dev/null @@ -1,30 +0,0 @@ -.section ".fit_pointer", "a", @progbits - .code32 -.global fit_pointer -fit_pointer: -.long fit_table -.long 0 -.previous - -.section ".rom.data", "a", @progbits -.align 16 -.global fit_table -.global fit_table_end -fit_table: -/* Address for type 0 is '_FIT_ ' */ -.long 0x5449465f -.long 0x2020205f -/* - * There is 1 entry in the table. Other tools will have to update the size - * and checksum when adding entries. - */ -.long 0x00000001 -/* Version */ -.word 0x0100 -/* Type 0 with checksum valid. */ -.byte 0x80 -/* Checksum byte - must add to zero. */ -.byte 0x7d -.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 -fit_table_end: -.previous

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Patch set updated for coreboot: x86/bootblock: Use LDFLAGS_bootblock to enable garbage collection
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11781 -gerrit commit e2a1169177927734172f90cad32c2991f8e98680 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 10:59:13 2015 -0700 x86/bootblock: Use LDFLAGS_bootblock to enable garbage collection The x86 bootblock linking is a mess. The bootblock is treated in a very special manner, and never received the update to link-time garbage collection. On newer x86 platforms, the boot media is no longer memory-mapped. That means we need to do a lot more setup in the bootblock. ROMCC is unsuitable for this task, and walkcbfs only works on memory-mapped CBFS. We need to revise the x86 bootflow for this new case. The approach this patch series takes is to perform CAR setup in the bootblock, and load the following stage (either romstage or verstage) from the boot media. This approach is not new, but has been done on our ARM ports for years. Since we will be adding .c files to the bootblock, it is prudent to use link-time garbage collection. This is also consistent to how we do things on other architectures. Unification FTW! Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 4 ++-- src/arch/x86/id.ld | 2 +- src/cpu/intel/fit/fit.ld | 2 +- src/cpu/x86/16bit/reset16.ld | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f16edcd..1bda5f6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -106,9 +106,9 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU $(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld + $(LD_bootblock) $(LDFLAGS_common) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld else - $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld + $(LD_bootblock) $(LDFLAGS_common) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld endif diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index cfd091d..99d13f1 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,6 +1,6 @@ SECTIONS { . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { - *(.id) + KEEP(*(.id)) } } diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld index 9ccfe82..5817e1d 100644 --- a/src/cpu/intel/fit/fit.ld +++ b/src/cpu/intel/fit/fit.ld @@ -1,6 +1,6 @@ SECTIONS { . = 0xffffffc0; .fit_pointer (.): { - *(.fit_pointer) + KEEP(*(.fit_pointer)) } } diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index a31a580..d0c4096 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -9,7 +9,7 @@ SECTIONS { _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { - *(.reset) + KEEP(*(.reset)); . = 15 ; BYTE(0x00); }

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Patch set updated for coreboot: arch/x86/bootblock: Link in object files selected with bootblock-y
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11783 -gerrit commit 57475142923328f30774a0ee3679ec674716eb36 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:17:56 2015 -0700 arch/x86/bootblock: Link in object files selected with bootblock-y As part of preparing for systems with non-memory-mapped media, we want to be able to call into C code. This change allows us to link C code directly into the bootblock. The steps of going from bootblock main() to CAR setup to C code will be implemented in subsequent patches. Note that a few files selected with bootblock-y will now be compiled for the bootblock as well, but since we enabled garbage collection, they will not be included in the final binary. Change-Id: I5ca6dcaf176f5469c6a3bb925859399123493bc6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 7 +++++-- src/arch/x86/failover.ld | 3 +++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fba07c7..7c07de2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -110,10 +110,13 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ -$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld +# $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_common) $(LDFLAGS_x86) -static \ - -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld + -o $@ -L$(obj) \ + $(filter %.o,$(bootblock-objs)) \ + -T $(obj)/arch/x86/bootblock.bootblock.ld \ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index d7aa47e..89d5449 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -41,6 +41,8 @@ SECTIONS *(.rom.text); *(.rom.data); *(.rom.data.*); + *(.text); + *(.text.*); *(.rodata.*); _erom = .; } >rom = 0xff @@ -63,6 +65,7 @@ SECTIONS *(.note) *(.comment.*) *(.note.*) + *(.eh_frame) *(.iplt) *(.rel.*) *(.igot.*)

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Patch set updated for coreboot: arch/x86/Makefile.inc: Simplify rule for bootblock.debug
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11782 -gerrit commit 23e4f5bc35f683b77b1fe49727afc1165f515f7f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:24:00 2015 -0700 arch/x86/Makefile.inc: Simplify rule for bootblock.debug The only difference between the ifeq/else/endif guarded rules is the linker flags specific to x86. Set those flags elsewhere, in a variable, and only use one rule for bootblock.debug. Change-Id: I986a93e0418f05fb273512d7efe0573052493332 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1bda5f6..fba07c7 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -74,6 +74,13 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) +# x86-specific linker flags +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) +LDFLAGS_x86 := -m elf_i386 --oformat elf32-i386 +else +LDFLAGS_x86 := -m elf_x86_64 --oformat elf64-x86-64 +endif + # Add the assembly file that pulls in the rest of the dependencies in # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. @@ -105,11 +112,8 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOU $(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) $(LDFLAGS_common) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld -else - $(LD_bootblock) $(LDFLAGS_common) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld -endif + $(LD_bootblock) $(LDFLAGS_common) $(LDFLAGS_x86) -static \ + -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64

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Patch set updated for coreboot: arch/x86: Link walkcbfs.S instead on including it in bootblock.S
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11785 -gerrit commit bc563e2a34e90bdfc82a3726b9efde55624327df Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 16:17:41 2015 -0700 arch/x86: Link walkcbfs.S instead on including it in bootblock.S The code flow doesn't fall through to walkcbfs, as it does in the rest of bootblock.S. Instead, walkcbfs is called (albeit via a jmp). The linker cannot know this when walkcbfs.S is included directly. When we use a CAR bootblock, we lose several hundred bytes because walkcbfs is not garbage-collected, yet it isn't used. This problem is solved by assembling walkcbfs.S separately, and linking it. Change-Id: Ib3a976db09b9ff270b7677cb4f9db80b0b025e22 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/bootblock.S | 2 -- src/arch/x86/walkcbfs.S | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7c07de2..95ebb6a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -85,6 +85,7 @@ endif # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. bootblock-y += bootblock.S +bootblock-y += walkcbfs.S $(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc bootblock-y += bootblock.ld diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S index 7276c7a..bea178d 100644 --- a/src/arch/x86/bootblock.S +++ b/src/arch/x86/bootblock.S @@ -47,5 +47,3 @@ * needs to come after bootblock.inc. */ #include <generated/bootblock.inc> - -#include <arch/x86/walkcbfs.S> diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index 9c26d3c..0b91f57 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -18,6 +18,8 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) +.global walkcbfs_asm + /* * input %esi: filename * input %esp: return address (not pointer to return address!)

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Patch set updated for coreboot: arch/x86: Allow boot flow which runs CAR setup in bootblock
by Alexandru Gagniuc 05 Oct '15

05 Oct '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11784 -gerrit commit 180303ac40c16c9b6205b8afca5083e1f46aae30 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:42:26 2015 -0700 arch/x86: Allow boot flow which runs CAR setup in bootblock On systems with non-memory-mapped boot media we simply do not have enough space for romstage. This means that CAR setup and early boot media (e.g. SPI) drivers need to be implemented with minimal overhead. The bootblock is the best place to do this. Note that this patch does introduce a somewhat awkward boot flow: reset(gas) -> bootblock main (romcc) -> car setup (gas) -> car (gcc) However, we've chosen this path as it is least intrusive on the existing infrastructure. In the future, we will investigate the possiblity of eliminating the romcc step. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Kconfig | 6 ++++++ src/arch/x86/bootblock_simple.c | 27 ++++++++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 88b2592..59eeb87 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -56,6 +56,12 @@ config ARCH_RAMSTAGE_X86_64 bool default n +# This is a new bootflow, in which CAR setup is performed in the bootblock, then +# calls into C code (in the bootblock) +config CAR_BOOTBLOCK + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index adeecf7..1c8eb02 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -2,6 +2,24 @@ #include <bootblock_common.h> #include <halt.h> +static void advance_to_romstage(unsigned long bist) +{ + const char* target1 = "fallback/romstage"; + unsigned long entry; + entry = findstage(target1); + if (entry) call(entry, bist); + halt(); + +} + +static void advance_to_car_setup(unsigned long bist) +{ + __asm__ volatile( + "jmp bootblock_pre_car_entry" + :: "a" (bist) + ); +} + static void main(unsigned long bist) { if (boot_cpu()) { @@ -15,9 +33,8 @@ static void main(unsigned long bist) #endif } - const char* target1 = "fallback/romstage"; - unsigned long entry; - entry = findstage(target1); - if (entry) call(entry, bist); - halt(); + if (IS_ENABLED(CONFIG_CAR_BOOTBLOCK)) + advance_to_car_setup(bist); + else + advance_to_romstage(bist); }

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New patch to review for coreboot: mainboard/lenovo/t410: Add new port - NOT FOR MERGE
by Nicolas Reinecke 04 Oct '15

04 Oct '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11791 -gerrit commit f837c29f681f848e6a990fc7d532ea5f8f58ef0e Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Jul 4 23:37:06 2015 +0200 mainboard/lenovo/t410: Add new port - NOT FOR MERGE The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Testing in progress. Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/ec/acpi/Makefile.inc | 1 + src/mainboard/lenovo/t410/Kconfig | 50 ++++ src/mainboard/lenovo/t410/Kconfig.name | 2 + src/mainboard/lenovo/t410/Makefile.inc | 23 ++ src/mainboard/lenovo/t410/acpi/dock.asl | 78 +++++++ src/mainboard/lenovo/t410/acpi/ec.asl | 25 ++ src/mainboard/lenovo/t410/acpi/gpe.asl | 29 +++ src/mainboard/lenovo/t410/acpi/platform.asl | 148 ++++++++++++ src/mainboard/lenovo/t410/acpi/superio.asl | 1 + src/mainboard/lenovo/t410/acpi_tables.c | 29 +++ src/mainboard/lenovo/t410/board_info.txt | 5 + src/mainboard/lenovo/t410/cmos.default | 18 ++ src/mainboard/lenovo/t410/cmos.layout | 135 +++++++++++ src/mainboard/lenovo/t410/devicetree.cb | 186 +++++++++++++++ src/mainboard/lenovo/t410/dock.c | 69 ++++++ src/mainboard/lenovo/t410/dock.h | 26 +++ src/mainboard/lenovo/t410/dsdt.asl | 103 +++++++++ src/mainboard/lenovo/t410/gpio.h | 343 ++++++++++++++++++++++++++++ src/mainboard/lenovo/t410/hda_verb.c | 81 +++++++ src/mainboard/lenovo/t410/mainboard.c | 100 ++++++++ src/mainboard/lenovo/t410/romstage.c | 309 +++++++++++++++++++++++++ src/mainboard/lenovo/t410/smi.h | 26 +++ src/mainboard/lenovo/t410/smihandler.c | 192 ++++++++++++++++ 23 files changed, 1979 insertions(+) diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index efdd4b1..e52249c 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -3,5 +3,6 @@ ifeq ($(CONFIG_EC_ACPI),y) ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_T410) += ec.c endif diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig new file mode 100644 index 0000000..74d3e16 --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig @@ -0,0 +1,50 @@ +if BOARD_LENOVO_T410 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO + select DRIVERS_ICS_954309 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select MAINBOARD_HAS_LPC_TPM + +config MAINBOARD_DIR + string + default lenovo/t410 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T410" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 4 + +config CPU_ADDR_BITS + int + default 36 + +endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name new file mode 100644 index 0000000..d79cf39 --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_T410 + bool "ThinkPad T410" diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc new file mode 100644 index 0000000..932df82 --- /dev/null +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +romstage-y += dock.c +ramstage-y += dock.c diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl new file mode 100644 index 0000000..440bb39 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "smi.h" + +Scope (\_SB) +{ + Device(DOCK) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + /* connect dock */ + Store (1, \GP28) + Store (1, \_SB.PCI0.LPCB.EC.DKR1) + Store (1, \_SB.PCI0.LPCB.EC.DKR2) + Store (1, \_SB.PCI0.LPCB.EC.DKR3) + } else { + /* disconnect dock */ + Store (0, \GP28) + Store (0, \_SB.PCI0.LPCB.EC.DKR1) + Store (0, \_SB.PCI0.LPCB.EC.DKR2) + Store (0, \_SB.PCI0.LPCB.EC.DKR3) + } + Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Return (Local0) + } + + Method(_STA, 0, NotSerialized) + { + Return (\_SB.PCI0.LPCB.EC.DKR1) + } + } +} + +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q45, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q58, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } + + Method(_Q37, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } +} diff --git a/src/mainboard/lenovo/t410/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl new file mode 100644 index 0000000..1bacbba --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl new file mode 100644 index 0000000..9a95342 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "smi.h" +Scope (\_GPE) +{ + Method(_L18, 0, NotSerialized) + { + /* Read EC register to clear wake status */ + Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + } +} diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl new file mode 100644 index 0000000..1e46a43 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Not implemented. */ + Return(Package(){0,0}) +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + /* TRAP(71) */ /* TODO */ + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } + } + } +} diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl new file mode 100644 index 0000000..03b65bc --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c new file mode 100644 index 0000000..40831c3 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <string.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <southbridge/intel/ibexpeak/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/lenovo/t410/board_info.txt b/src/mainboard/lenovo/t410/board_info.txt new file mode 100644 index 0000000..2d104405 --- /dev/null +++ b/src/mainboard/lenovo/t410/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t410/cmos.default b/src/mainboard/lenovo/t410/cmos.default new file mode 100644 index 0000000..5b4e634 --- /dev/null +++ b/src/mainboard/lenovo/t410/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Disable +wlan=Enable +touchpad=Enable +trackpoint=Enable +fn_ctrl_swap=Disable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout new file mode 100644 index 0000000..1f34d0a --- /dev/null +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2013 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode + +#422 2 r 0 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + +#427 557 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb new file mode 100644 index 0000000..3f2dc14 --- /dev/null +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -0,0 +1,186 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "1" # + register "gpu_panel_power_up_delay" = "1" # + register "gpu_panel_power_down_delay" = "600" # + register "gpu_panel_power_backlight_on_delay" = "0" # + register "gpu_panel_power_backlight_off_delay" = "0" # + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" + + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x87" + register "event7_enable" = "0x89" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x2d" + end + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2193 + end + device pci 02.0 on # VGA controller + subsystemid 0x17aa 0x215a + end + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + # 0:HDD Bay 1:ODD Bay 4:eSATA Combo Connector + register "sata_port_map" = "0x13" + + register "gpe0_en" = "0x20022046" + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen3_dec" = "0x1c1681" + register "gen4_dec" = "0x040069" + + register "p_cnt_throttling_supported" = "1" + register "c2_latency" = "1" + register "docking_supported" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 off end # MEI + device pci 16.2 on # IDE/SATA + subsystemid 0x17aa 0x2161 + end + + device pci 19.0 on # Ethernet + subsystemid 0x17aa 0x2153 + end + + device pci 1a.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x215e + end + + device pci 1c.0 on end # PCIe Port #1 (wlan) + device pci 1c.1 off end # PCIe Port #2 (wwan) + device pci 1c.2 off end # PCIe Port #3 (wusb) + device pci 1c.3 on end # PCIe Port #4 (ExpressCard) + device pci 1c.4 on + subsystemid 0x17aa 0x2133 + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x2134 + end + end + end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe) + + device pci 1d.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2166 + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on # IDE/SATA + subsystemid 0x17aa 0x2168 + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x2167 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.6 on # Thermal Subsystem + subsystemid 0x17aa 0x2190 + end + end + end +end diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c new file mode 100644 index 0000000..913c66c --- /dev/null +++ b/src/mainboard/lenovo/t410/dock.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#define __SIMPLE_DEVICE__ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> +#include "dock.h" + +void h8_mainboard_init_dock(void) +{ + if (dock_present()) { + printk(BIOS_DEBUG, "dock is connected\n"); + dock_connect(); + } else + printk(BIOS_DEBUG, "dock is not connected\n"); +} + +void dock_connect(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + ec_set_bit(0x02, 0); + ec_set_bit(0x1a, 0); + ec_set_bit(0xfe, 4); + + outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); +} + +void dock_disconnect(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + ec_clr_bit(0x02, 0); + ec_clr_bit(0x1a, 0); + ec_clr_bit(0xfe, 4); + + outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); +} + +int dock_present(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u8 st = inb(gpiobase + 0x0c); + + return ((st >> 3) & 7) != 7; +} diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h new file mode 100644 index 0000000..f590dcb --- /dev/null +++ b/src/mainboard/lenovo/t410/dock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef THINKPAD_T410_DOCK_H +#define THINKPAD_T410_DOCK_H + +extern void dock_connect(void); +extern void dock_disconnect(void); +extern int dock_present(void); +#endif diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl new file mode 100644 index 0000000..bc2073e --- /dev/null +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, /* DSDT revision: ACPI v3.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20130325 /* OEM revision */ +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + /* General Purpose Events */ + #include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + Device (UNCR) + { + Name (_BBN, 0xFF) + Name (_ADR, 0x00) + Name (RID, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* Granularity */ + 0x00FF, /* Range Minimum */ + 0x00FF, /* Range Maximum */ + 0x0000, /* Translation Offset */ + 0x0001, /* Length */ + ,, ) + }) + Device (SAD) + { + Name (_ADR, 0x01) + Name (RID, 0x00) + OperationRegion (SADC, PCI_Config, 0x00, 0x0100) + Field (SADC, DWordAcc, NoLock, Preserve) + { + Offset (0x40), + PAM0, 8, + PAM1, 8, + PAM2, 8, + PAM3, 8, + PAM4, 8, + PAM5, 8, + PAM6, 8 + } + } + } + } + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + + /* Dock support code */ + #include "acpi/dock.asl" +} diff --git a/src/mainboard/lenovo/t410/gpio.h b/src/mainboard/lenovo/t410/gpio.h new file mode 100644 index 0000000..1e6847e --- /dev/null +++ b/src/mainboard/lenovo/t410/gpio.h @@ -0,0 +1,343 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef LENOVO_T410_GPIO_H +#define LENOVO_T410_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map t410_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .reset = &pch_gpio_set1_reset, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c new file mode 100644 index 0000000..7e40e81 --- /dev/null +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa214c, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa214c), + + /* NID 0x19: Headphone jack. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x042110f0), + + /* NID 0x1A: Dock mic jack. */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x61a190f0), + + /* NID 0x1B: Mic jack. */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x04a110f0), + + /* NID 0x1C: Dock headphone jack. */ + AZALIA_PIN_CFG(0x0, 0x1C, 0x612140f0), + + /* NID 0x1D: EAPD detect. */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40f001f0), + + /* NID 0x1E */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x40f001f0), + + /* NID 0x1F */ + AZALIA_PIN_CFG(0x0, 0x1F, 0x901701f0), + + /* NID 0x20 */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40f001f0), + + /* NID 0x22 */ + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + + /* NID 0x23: Internal mic boost volume. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), + + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17aa21b5, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ + AZALIA_SUBVENDOR(0x3, 0x17AA21B5), + + /* NID 0x04. */ + AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c new file mode 100644 index 0000000..7afa5a6 --- /dev/null +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <string.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <ec/lenovo/pmh7/pmh7.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <arch/x86/include/arch/acpigen.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <cpu/x86/lapic.h> +#include <smbios.h> +#include <version.h> +#include <drivers/lenovo/lenovo.h> +#include "dock.h" + +static acpi_cstate_t cst_entries[] = { + {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}}, + {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}}, + {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} + +static void mainboard_init(device_t dev) +{ + /* Configure SPI. */ // XXX short version ? + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + +} + +static void mainboard_enable(device_t dev) +{ + device_t dev0; + u16 pmbase; + + dev->ops->init = mainboard_init; + + pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + PMBASE) & 0xff80; + + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); + + outl(0, pmbase + SMI_EN); + + enable_lapic(); + /* enable GPIOs */ // XXX redundant? + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, + DEFAULT_GPIOBASE | 1); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, + 0x10); + + /* If we're resuming from suspend, blink suspend LED */ + dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + ec_write(0x0c, 0xc7); + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_LFP, 2); + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c new file mode 100644 index 0000000..b5d407d --- /dev/null +++ b/src/mainboard/lenovo/t410/romstage.c @@ -0,0 +1,309 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <cbmem.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <arch/early_variables.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <ec/acpi/ec.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <tpm.h> +#include "gpio.h" +#include "dock.h" + +static void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN | GAMEL_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); + pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); + + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); +} + +static void rcba_config(void) +{ + southbridge_configure_default_intmap(); + + static const u32 rcba_dump3[] = { + /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, + /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, + /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, + /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, + /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, + /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, + /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, + /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, + /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, + /* 3420 */ 0x00000000, 0x00060010, 0x0000000d, 0x00000000, + /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, + /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3500 */ 0x2000055f, 0x2000055f, 0x2000074b, 0x2000014b, + /* 3510 */ 0x2000014b, 0x2000074b, 0x2000074b, 0x2000074b, + /* 3520 */ 0x2000055f, 0x2000055f, 0x2000074b, 0x2000074b, + /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, + /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, + /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, + /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, + /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, + /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + unsigned i; + for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void) RCBA32(4 * i + 0x3310); + } +} + +static inline void write_acpi32(u32 addr, u32 val) +{ + outl(val, DEFAULT_PMBASE | addr); +} + +static inline void write_acpi16(u32 addr, u16 val) +{ + outw(val, DEFAULT_PMBASE | addr); +} + +static inline u32 read_acpi32(u32 addr) +{ + return inl(DEFAULT_PMBASE | addr); +} + +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} + +void main(unsigned long bist) +{ + u32 reg32; + int s3resume = 0; + const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; + + timestamp_init(timestamp_get()); + + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + nehalem_early_initialization(NEHALEM_MOBILE); + + pch_enable_lpc(); + + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&t410_gpio_map); + + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + u8 reg8; + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + printk(BIOS_DEBUG, "a2: %02x\n", reg8); + if (!(reg8 & 0x20)) { + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } else { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + } else { + printk(BIOS_DEBUG, + "Resume from S3 detected, but disabled.\n"); + } + } + } + + /* Enable SMBUS. */ + enable_smbus(); + + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + write_acpi16(0x2, 0x0); + write_acpi32(0x28, 0x0); + write_acpi32(0x2c, 0x0); + if (!s3resume) { + read_acpi32(0x4); + read_acpi32(0x20); + read_acpi32(0x34); + write_acpi16(0x0, 0x900); + write_acpi32(0x20, 0xffff7ffe); + write_acpi32(0x34, 0x56974); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); + } + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + set_fsb_frequency(); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if (s3resume) { + void *resume_backup_memory; + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + quick_ram_check(); + } +#endif + +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/t410/smi.h b/src/mainboard/lenovo/t410/smi.h new file mode 100644 index 0000000..dd722c6 --- /dev/null +++ b/src/mainboard/lenovo/t410/smi.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_LENOVO_T410_SMI_H +#define MAINBOARD_LENOVO_T410_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 + +#endif diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c new file mode 100644 index 0000000..8585f48 --- /dev/null +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <delay.h> +#include "dock.h" +#include "smi.h" + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + case SMI_DOCK_CONNECT: + ec_clr_bit(0x03, 2); + udelay(250000); + dock_connect(); + ec_set_bit(0x03, 2); + /* set dock LED to indicate status */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); + break; + + case SMI_DOCK_DISCONNECT: + ec_clr_bit(0x03, 2); + dock_disconnect(); + break; + + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + case 0x18: + /* Fn-F9 key */ + case 0x27: + /* Power loss */ + case 0x50: + /* Undock Key */ + mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + break; + case 0x37: + case 0x58: + /* Dock Event */ + mainboard_io_trap_handler(SMI_DOCK_CONNECT); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_nehalem_finalize_smm(); + intel_model_2065x_finalize_smm(); + + mainboard_finalized = 1; + break; + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +}

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coreboot-gerrit October 2015