coreboot-gerrit January 2015

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Patch set updated for coreboot: 1930b40 vboot2: implement select_firmware for pre-romstage verification
by Marc Jones 13 Jan '15

13 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8160 -gerrit commit 1930b40c8eeae1672b7ca469ea5725e0e1d0dcd1 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:16:24 2014 -0700 vboot2: implement select_firmware for pre-romstage verification This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 --- src/arch/arm/Makefile.inc | 12 + src/arch/arm/armv7/Makefile.inc | 12 + src/arch/arm/bootblock.ld | 1 + src/arch/arm/libgcc/Makefile.inc | 4 + src/console/Makefile.inc | 4 + src/include/reset.h | 1 + src/lib/Makefile.inc | 6 + src/mainboard/google/nyan_blaze/Makefile.inc | 2 + src/mainboard/google/nyan_blaze/romstage.c | 4 + src/soc/nvidia/tegra124/Kconfig | 11 + src/soc/nvidia/tegra124/Makefile.inc | 8 + src/soc/nvidia/tegra124/verstage.c | 8 +- src/vendorcode/google/chromeos/Makefile.inc | 26 +++ src/vendorcode/google/chromeos/chromeos.h | 9 +- src/vendorcode/google/chromeos/vboot_handoff.c | 7 + src/vendorcode/google/chromeos/vboot_main.c | 311 +++++++++++++++++++++++++ 16 files changed, 423 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index ba7fb60..2caf48e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -68,6 +68,18 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(boo endif # CONFIG_ARCH_BOOTBLOCK_ARM ############################################################################### +# verification stage +############################################################################### + +verstage-y += early_console.c +verstage-y += div0.c +verstage-y += eabi_compat.c +verstage-y += memset.S +verstage-y += memcpy.S +verstage-y += memmove.S +verstage-y += stages.c + +############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 7e67178..0919a93 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -46,6 +46,18 @@ bootblock-S-ccopts += $(armv7_asm_flags) endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 +################################################################################ +## verification stage +################################################################################ + +verstage-c-ccopts += $(armv7_flags) +verstage-S-ccopts += $(armv7_asm_flags) +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception.c +verstage-y += exception_asm.S +verstage-y += mmu.c + ############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c1a6ccf 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -50,6 +50,7 @@ SECTIONS } : to_load = 0xff preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + verstage_preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index a1d325d..5e8858a 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) bootblock-y += $(libgcc_files) endif +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) +verstage-y += $(libgcc_files) +endif + ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) romstage-y += $(libgcc_files) endif diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d339500..64d980b 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -6,6 +6,10 @@ ramstage-y += die.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +verstage-y += vtxprintf.c +verstage-y += console.c +verstage-y += die.c + romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c diff --git a/src/include/reset.h b/src/include/reset.h index 9f117db..9430ffe 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -7,5 +7,6 @@ void hard_reset(void); #define hard_reset() do {} while(0) #endif void soft_reset(void); +void cpu_reset(void); #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9b5f56b..946012d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -24,6 +24,12 @@ bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-y += memchr.c bootblock-y += memcmp.c +verstage-y += delay.c +verstage-y += cbfs.c +verstage-y += memcmp.c +verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + + romstage-y += memchr.c romstage-y += memcmp.c $(foreach arch,$(ARCH_SUPPORTED),\ diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index b66cd55..02b3977 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -32,6 +32,8 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +verstage-y += reset.c + romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..480abd6 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -228,7 +228,11 @@ static void __attribute__((noinline)) romstage(void) cbmemc_reinit(); #endif +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + // vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); +#else vboot_verify_firmware(romstage_handoff_find_or_add()); +#endif timestamp_add(TS_START_COPYRAM, timestamp_get()); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index ea946e6..d9264fe 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -46,10 +46,12 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" + default 0x1e000 if VBOOT2_VERIFY_FIRMWARE default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" + default 0x1e080 if VBOOT2_VERIFY_FIRMWARE default 0x18080 config SYS_SDRAM_BASE @@ -62,6 +64,7 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex + default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE default 0x4002c000 config RAMSTAGE_BASE @@ -94,6 +97,14 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00017fe0 +config VBOOT_WORK_BUFFER_ADDRESS + hex "memory address of vboot work buffer" + default 0x40018000 + +config VBOOT_WORK_BUFFER_SIZE + hex "size of vboot work buffer" + default 0x00004000 + config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index b306412..4b0ec96 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -21,6 +21,14 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif verstage-y += verstage.c +verstage-y += cbfs.c +verstage-y += dma.c +verstage-y += monotonic_timer.c +verstage-y += spi.c +verstage-y += timer.c +verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/pinmux.c romstage-y += cbfs.c romstage-y += cbmem.c diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 234a89d..d85fc5c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,9 +1,15 @@ #include "verstage.h" +#include <vendorcode/google/chromeos/chromeos.h> /** * Stage entry point */ void vboot_main(void) { - for(;;); + /* Stub to force arm_init_caches to the top, before any stack/memory + * accesses */ + asm volatile ("bl arm_init_caches" + ::: "r0","r1","r2","r3","r4","r5","ip"); + + select_firmware(); } diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 12d35b6..cb3d9a6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -95,7 +95,33 @@ $(VB_LIB): endif ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +VB_SOURCE := vboot_reference VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a + +INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include +INCLUDES += -I$(VB_SOURCE)/firmware/include +verstage-y += vboot_main.c fmap.c chromeos.c + +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) +VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a +VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS_verstage))) +VBOOT_CFLAGS += $(verstage-c-ccopts) +VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes +VBOOT_CFLAGS += -DVBOOT_DEBUG + +$(VB2_LIB): $(obj)/config.h + @printf " MAKE $(subst $(obj)/,,$(@))\n" + $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + CC="$(CC_verstage)" \ + CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ + make -C $(VB_SOURCE) \ + BUILD=$(top)/$(dir $(VB2_LIB)) \ + V=$(V) \ + fwlib2 + mv $@ $@.tmp + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@ + $(VERSTAGE_LIB): $$(verstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" $(AR_verstage) rc $@.tmp $(verstage-objs) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a2ecac8..a799528 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,7 +46,7 @@ struct romstage_handoff; /* TODO(shawnn): Remove these CONFIGs and define default weak functions * that can be overridden in the platform / MB code. */ -#if CONFIG_VBOOT_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE /* * This is a dual purpose routine. If dest is non-NULL the region at * offset_addr will be read into the area pointed to by dest. If dest @@ -67,7 +67,8 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) return -1; } static inline int vboot_skip_display_init(void) { return 0; } -#endif +#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE */ + int vboot_get_sw_write_protect(void); #include "gnvs.h" @@ -85,4 +86,8 @@ static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #endif /* CONFIG_CHROMEOS_RAMOOPS */ +#if CONFIG_VBOOT2_VERIFY_FIRMWARE +void select_firmware(void); +#endif + #endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c index 7ef2c7e..7ea21ea 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -105,6 +105,12 @@ int __attribute((weak)) vboot_get_sw_write_protect(void) return 0; } +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + +void *vboot_get_payload(int *len) { return NULL; } + +#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ + static void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; @@ -131,6 +137,7 @@ static void *vboot_get_payload(size_t *len) return (void *)fwc->address; } +#endif static int vboot_locate_payload(struct payload *payload) { diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c new file mode 100644 index 0000000..9779d35 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -0,0 +1,311 @@ +#include <2api.h> +#include <2struct.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <reset.h> +#include <string.h> + +#include "chromeos.h" +#include "fmap.h" + +#define VBDEBUG(format, args...) \ + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) +#define TODO_BLOCK_SIZE 8192 +#define MAX_PARSED_FW_COMPONENTS 5 +#define ROMSTAGE_INDEX 2 + +struct component_entry { + uint32_t offset; + uint32_t size; +} __attribute__((packed)); + +struct components { + uint32_t num_components; + struct component_entry entries[MAX_PARSED_FW_COMPONENTS]; +} __attribute__((packed)); + +struct vboot_region { + uintptr_t offset_addr; + int32_t size; +}; + +/* exports */ + +void vb2ex_printf(const char *func, const char *fmt, ...) +{ + va_list args; + + printk(BIOS_INFO, "VB2:%s() ", func); + va_start(args, fmt); + printk(BIOS_INFO, fmt, args); + va_end(args); + + return; +} + +int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +{ + VBDEBUG("Clearing owner\n"); + return VB2_ERROR_UNKNOWN; +} + +int vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) +{ + VBDEBUG("Reading resource\n"); + return VB2_ERROR_UNKNOWN; +} + +/* locals */ + +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)&region->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + +static void reboot(void) +{ + cpu_reset(); +} + +static void recovery(void) +{ + void *entry; + + if (!in_ro()) + reboot(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry != (void *)-1) + stage_exit(entry); + + for(;;); +} + +static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main) +{ + uint32_t expected_size; + uint8_t block[TODO_BLOCK_SIZE]; + size_t block_size = sizeof(block); + uintptr_t offset; + int rv; + + expected_size = fw_main->size; + offset= fw_main->offset_addr; + + /* Start the body hash */ + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + if (rv) { + return rv; + } + + /* Extend over the body */ + while (expected_size) { + void *b; + if (block_size > expected_size) + block_size = expected_size; + + b = vboot_get_region(offset, block_size, block); + if (b == NULL) + return VB2_ERROR_UNKNOWN; + rv = vb2api_extend_hash(ctx, b, block_size); + if (rv) + return rv; + + expected_size -= block_size; + offset+= block_size; + } + + /* Check the result */ + rv = vb2api_check_hash(ctx); + if (rv) { + return rv; + } + + return VB2_SUCCESS; +} + +static int locate_fw_components(struct vb2_context *ctx, + struct vboot_region *fw_main, + struct components *fw_info) +{ + if (is_slot_a(ctx)) + locate_region("FW_MAIN_A", fw_main); + else + locate_region("FW_MAIN_B", fw_main); + if (fw_main->size < 0) + return 1; + + if (vboot_get_region(fw_main->offset_addr, + sizeof(*fw_info), fw_info) == NULL) + return 1; + return 0; +} + +static struct cbfs_stage *load_stage(struct vb2_context *ctx, + int stage_index, + struct vboot_region *fw_main, + struct components *fw_info) +{ + struct cbfs_stage *stage; + uint32_t fc_addr; + uint32_t fc_size; + + /* Check for invalid address. */ + fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; + fc_size = fw_info->entries[stage_index].size; + if (fc_addr == 0 || fc_size == 0) { + VBDEBUG("romstage address invalid.\n"); + return NULL; + } + + /* Loading to cbfs cache. This stage data must be retained until it's + * decompressed. */ + stage = vboot_get_region(fc_addr, fc_size, NULL); + + if (stage == NULL) { + VBDEBUG("Unable to load a stage.\n"); + return NULL; + } + + return stage; +} + +static void enter_stage(struct cbfs_stage *stage) +{ + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *) (uintptr_t)stage->load, 0, stage->memlen); + + if (cbfs_decompress(stage->compression, + (unsigned char *)stage + sizeof(*stage), + (void *) (uintptr_t) stage->load, + stage->len)) + return; + + VBDEBUG("Jumping to entry @%llx.\n", stage->entry); + stage_exit((void *)(uintptr_t)stage->entry); +} + +/** + * Save non-volatile and/or secure data if needed. + */ +static void save_if_needed(struct vb2_context *ctx) +{ + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { + VBDEBUG("Saving nvdata\n"); + //save_vbnv(ctx->nvdata); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + } + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + VBDEBUG("Saving secdata\n"); + //antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + } +} + +void __attribute__((noinline)) select_firmware(void) +{ + struct vb2_context ctx; + uint8_t *workbuf = (uint8_t *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS; + struct vboot_region fw_main; + struct components fw_info; + struct cbfs_stage *stage; + int rv; + + console_init(); + + /* Set up context */ + memset(&ctx, 0, sizeof(ctx)); + ctx.workbuf = workbuf; + ctx.workbuf_size = CONFIG_VBOOT_WORK_BUFFER_SIZE; + memset(ctx.workbuf, 0, ctx.workbuf_size); + + /* Read nvdata from a non-volatile storage */ + //read_vbnv(ctx.nvdata); + + /* Read secdata from TPM. Initialize TPM if secdata not found. We don't + * check the return value here because vb2api_fw_phase1 will catch + * invalid secdata and tell us what to do (=reboot). */ + //antirollback_read_space_firmware(&ctx); + + //if (get_developer_mode_switch()) + // ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; + //if (get_recovery_mode_switch()) { + // clear_recovery_mode_switch(); + // ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + //} + + /* Do early init */ + VBDEBUG("Phase 1\n"); + rv = vb2api_fw_phase1(&ctx); + if (rv) { + VBDEBUG("Recovery requested (%x)\n", rv); + /* If we need recovery mode, leave firmware selection now */ + save_if_needed(&ctx); + recovery(); + } + + /* Determine which firmware slot to boot */ + VBDEBUG("Phase 2\n"); + rv = vb2api_fw_phase2(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + /* Try that slot */ + VBDEBUG("Phase 3\n"); + rv = vb2api_fw_phase3(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + VBDEBUG("Phase 4\n"); + rv = locate_fw_components(&ctx, &fw_main, &fw_info); + if (rv) { + VBDEBUG("Failed to locate firmware components\n"); + reboot(); + } + rv = hash_body(&ctx, &fw_main); + stage = load_stage(&ctx, ROMSTAGE_INDEX, &fw_main, &fw_info); + if (stage == NULL) { + VBDEBUG("Failed to load stage\n"); + reboot(); + } + save_if_needed(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + reboot(); + } + + /* TODO: Do we need to lock secdata? */ + VBDEBUG("Locking TPM\n"); + + /* Load next stage and jump to it */ + VBDEBUG("Jumping to rw-romstage @%llx\n", stage->entry); + enter_stage(stage); + + /* Shouldn't reach here */ + VBDEBUG("Halting\n"); + for(;;); +}

1 0

Patch merged into coreboot/master: 320647a vboot2: add verstage
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit 320647abdad1ea6cdceb834933507677020ea388 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:09:47 2014 -0700 vboot2: add verstage Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0 Reviewed-on: http://review.coreboot.org/8159 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8159 for details. -gerrit

1 0

Patch merged into coreboot/master: 337de4c cbmem: Add support for new 'coreboot' compatible device tree binding
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit 337de4c0e539d3d055b916f40fc44067d1a13cd7 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jun 16 23:02:03 2014 -0700 cbmem: Add support for new 'coreboot' compatible device tree binding This patch brings the cbmem utility in line with the recent change to coreboot's device tree binding. Since trying to find the right node to place this binding has been so hard (and still isn't quite agreed upon), and because it's really the more correct thing to do, this code searches through the device tree for the 'coreboot' compatible property instead of looking up a hardcoded path. It also provides bullet-proof '#address-cells' handling that should work for any endianness and size. BUG=chrome-os-partner:29311 TEST=Ran cbmem -c and cbmem -t on Nyan_Big. Also straced the to make sure everything looks as expected. 'time cbmem -t' = ~35ms shows that there is no serious performance problem from the more thorough lookup code. Original-Change-Id: I806a21270ba6cec6e81232075749016eaf18508b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204274 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 3e64e28f684e60e8b300906c1abffee75ec6a5c2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0a0a4f69330d3d8c5c3ea92b55f5dde4d43fca65 Reviewed-on: http://review.coreboot.org/8141 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8141 for details. -gerrit

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Patch merged into coreboot/master: b3e0202 cbfs: add cbfs_read()
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit b3e0202fd45f415b4e92ad824e28d79fb9b33abf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 27 15:28:39 2014 -0500 cbfs: add cbfs_read() Allow for reading from cbfs media without having a handle to a non-CBFS_DEFAULT_MEDIA cbfs_media. In conjunction with cbfs_locate_file() one can locate and cbfs_read() a file without bringing the entire file through a potentially temporary buffer (non-memory-mappable cbfs media platforms). BUG=chrome-os-partner:29922 BRANCH=None TEST=Built. Original-Change-Id: Ib5d965334bce1267650fc23c9e9f496675cf8450 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205991 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 85200f28863e5ea8888322f5787dc6de9a2999f0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I25e3221beefd0155305ad63da6be9f47e756f7d0 Reviewed-on: http://review.coreboot.org/8181 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/8181 for details. -gerrit

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Patch merged into coreboot/master: b312b7f cbfs: add cbfs_locate_file()
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit b312b7f4660d6e32d08659ebb5fe0d3bb5635916 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 27 15:06:02 2014 -0500 cbfs: add cbfs_locate_file() cbfs_locate_file() can be used to locate the data within the cbfs file. Based on the offset and length of the file it can then be read into any address without bringing the contents into another buffer (platforms without memory-mapped access to entire contents of cbfs at once). BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and booted rush into romstage (stage load still works). Original-Change-Id: I2932f66478c74511ec1c876b09794d9a22a526b3 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206000 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 56c958facd379ca0eeebe1b689e3b80d5e692699) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0c4964132af615a069258c0eb37153bd84fbbfae Reviewed-on: http://review.coreboot.org/8180 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/8180 for details. -gerrit

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Patch merged into coreboot/master: 01f5396 cbfstool: Remove arch check for different stages
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit 01f5396bdce2cd69e91c54ef120b11e457ab2694 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 25 17:50:28 2014 -0700 cbfstool: Remove arch check for different stages Remove the arch check for each stage as the arch for different stages can be different based on the SoC. e.g.: Rush has arm32-based romstage whereas arm64-based ramstage BUG=None BRANCH=None TEST=Compiles successfully for nyan, link and rush Original-Change-Id: I561dab5a5d87c6b93b8d667857d5e181ff72e35d Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205761 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 6a6a87b65fcab5a7e8163258c7e8d704fa8d97c3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic412d60d8a72dac4f9807cae5d8c89499a157f96 Reviewed-on: http://review.coreboot.org/8179 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8179 for details. -gerrit

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New patch to review for coreboot: 50ca10d util: Add script and to extract drm_dp_helper form linux sources
by Alexandru Gagniuc 13 Jan '15

13 Jan '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8210 -gerrit commit 50ca10d60273d6c85e12d90fb786d91790c26a89 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 13 14:11:43 2015 -0600 util: Add script and to extract drm_dp_helper form linux sources <NOTFOTMERGE> Feel free to edit commit msg and merge if you really want this. This gets the job mostly done. There are still some minor details to work out, but I wanted to publish this in case there are any interested parties. </NOTFOTMERGE> There already is a version of the drm_dp_helper in the intel gma driver, but that one is a severely gilded version. Most importantly, it's missing the I2C over AUX helpers, which we plan to use for radeon native init. The semantic patch introduced in this allows extracting those helpers without removing too much functionality. It converts include directives to point to files in our path, and modifies the i2c message structure to match the one e use in coreboot. The result is pretty close to something that compiles out-of-the box, tough minor manual editing may still be needed (emphasis on minor). Change-Id: Ia8c9879595528b6fd63437fed3b555e9e47ecf7f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- .../drm_dp_helper/dp_helper.spatch | 191 +++++++++++++++++++++ .../drm_dp_helper/extract_dp_helper.sh | 30 ++++ util/linux_source_extractors/drm_dp_helper/moo.h | 16 ++ 3 files changed, 237 insertions(+) diff --git a/util/linux_source_extractors/drm_dp_helper/dp_helper.spatch b/util/linux_source_extractors/drm_dp_helper/dp_helper.spatch new file mode 100644 index 0000000..0a1b962 --- /dev/null +++ b/util/linux_source_extractors/drm_dp_helper/dp_helper.spatch @@ -0,0 +1,191 @@ +/* + * Convert drm_dp_helpers in linux from linux-centric to coreboot friendly. + * + * Note: You want to run the extract_dp_helper.sh script. It's much friendlier, + * and does almost everything for you. + */ + +/* We don't use these ever */ +@ remove_bad_funcs @ +identifier func =~ "drm_dp_aux_unregister|drm_dp_aux_register|drm_dp_i2c_functionality"; +@@ + +- func(...) +- { +- ... +- } + +@ remove_export_symbol @ +declarer name EXPORT_SYMBOL; +@@ + +- EXPORT_SYMBOL(...); + +/* Some functions are found in coreboot headers */ +@ convert_includes_to_coreboot @ +@@ + +( +- #include <linux/types.h> ++ #include <stdbool.h> ++ #include <stddef.h> ++ #include <stdint.h> ++ #include <unistd.h> +| +- #include <linux/delay.h> ++ #include <delay.h> +| +- #include <drm/drm_dp_helper.h> ++ #include "drm_dp_helper.h" +) + +/* The remaining linux includes, we don't give care about */ +@ kill_linux_includes @ +@@ + +( +- #include <linux/...> +| +- #include <drm/drmP.h> +) + +/* Hey, what do you know! We only use u8. */ +@ convert_to_stdint @ +typedef u8; +typedef uint8_t; +typedef uint32_t; +@@ + +( +- u8 ++ uint8_t +| +/* A character is not an integer!!! God damn programmers */ +- unsigned char ++ uint8_t +| +/* How big is a long? Is it 32-bits, is it 64? Fuck that! Use a better type */ +- unsigned long ++ uint32_t +) + +/* We don't use usleep_range() */ +@ usleep_to_delay @ +constant t1, t2; +@@ + +- usleep_range(t1, t2); ++ udelay(t1); + +@ remove_locks @ +expression lock; +identifier s, memb; +@@ + +( +- mutex_lock(lock); +| +- mutex_unlock(lock); +| +- mutex_init(lock); +| +struct s { +... +- struct mutex memb; +... +}; +) + +@ remove_superflous_i2c_structs @ +identifier s; +identifier memb; +@@ + +struct s { +... +- struct i2c_adapter memb; +... +}; + +/* + * This is bad. We might want to change this into the future, but for now, + * it allows us to easily integrate this helper into coreboot. + */ +@ change_dp_aux_context_type @ +identifier s, dev; +@@ + +struct s { +... +- struct device *dev; ++ void *parent; +... +}; + + +@ attribute_packed_fix @ +identifier s; +//name __packed; +@@ + +struct s { +... +} +- __packed ++ __attribute__((packed)) +; + +@ remove_bad_structs @ +identifier n; +@@ + +- static const struct i2c_algorithm n = { +- ... +- }; + +@ convert_to_coreboot_i2c_struct @ +identifier func, adapter; +identifier aux; +@@ + +func(..., +- struct i2c_adapter *adapter ++ struct drm_dp_aux *aux +,...) +{ +... +- struct drm_dp_aux *aux = adapter->algo_data; +... +} + +@ convert_to_coreboot_i2c_msg @ +identifier func, msgs; +expression i; +@@ + +func(..., +- struct i2c_msg *msgs ++ struct i2c_seg *msgs +,...) +{ +<... +( +- msgs[i].addr ++ msgs[i].chip +| +- msgs[i].flags & I2C_M_RD ++ msgs[i].read +) +...> +} + +/* So, this rule doesn't add the prototype. hint: FIXME */ +@ make_i2c_non_static @ +identifier func =~ "drm_dp_i2c_xfer"; +@@ + +- static +func(...) +{ +... +} diff --git a/util/linux_source_extractors/drm_dp_helper/extract_dp_helper.sh b/util/linux_source_extractors/drm_dp_helper/extract_dp_helper.sh new file mode 100644 index 0000000..323ac07 --- /dev/null +++ b/util/linux_source_extractors/drm_dp_helper/extract_dp_helper.sh @@ -0,0 +1,30 @@ +#! /bin/bash + +# +# Extract the drm_dp_helper.[ch] files from a linux tree +# and convert them to a format usable in userspace or coreboot. +# +# Usage +# sh extract_dp_helper.sh <path/to/linux/sources> +# +# It outputs the drm_dp_helper file in the working directory. +# + +DEST=$(pwd) +HEADER=drm_dp_helper.h +SOURCE=drm_dp_helper.c + +HOME=$(dirname "${BASH_SOURCE[0]}") + +SPATCH=spatch + +echo Hello + +cp $1/include/drm/$HEADER $DEST +cp $1/drivers/gpu/drm/$SOURCE $DEST + +$SPATCH -sp_file $HOME/dp_helper.spatch \ + --macro-file-builtins $HOME/moo.h \ + -in_place $DEST/$SOURCE $DEST/$HEADER + +echo $PWD diff --git a/util/linux_source_extractors/drm_dp_helper/moo.h b/util/linux_source_extractors/drm_dp_helper/moo.h new file mode 100644 index 0000000..6a4b11f --- /dev/null +++ b/util/linux_source_extractors/drm_dp_helper/moo.h @@ -0,0 +1,16 @@ +/* + * Empty macro file for our semantic patches. The default macro file is stupid. + * It's so stupid in fact, that it defines as nothing things we want to remove. + * That prevents us from renaming macros like "__packed". To make sure the + * semantic patch works as expected, we override the built-in macro file. + * + * The cow is here to make sure we don't provide a completely useless file. + */ + +#define __MOO \ + " (__) \n" \ + " (oo) \n" \ + " /------\/ \n" \ + " / | || \n" \ + " * /\---/\ \n" \ + " ~~ ~~ \n"

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Patch merged into coreboot/master: fa6bd71 vendorcode/intel: remove DebugDeadLoop() from fsptypes.h
by gerrit＠coreboot.org 13 Jan '15

13 Jan '15

the following patch was just integrated into master: commit fa6bd71bddca404e99e4ab119b890020c0fda998 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 11:34:36 2015 -0700 vendorcode/intel: remove DebugDeadLoop() from fsptypes.h When included for the CAR transition, this was causing the error: error: invalid storage class for function 'DebugDeadLoop' Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8193 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8193 for details. -gerrit

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New patch to review for coreboot: 1c63cdc drivers/i2c/w83795: Fix tautology from wrong return type
by Edward O'Callaghan 13 Jan '15

13 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8209 -gerrit commit 1c63cdc4df6f7fd8f6b66d0397b026ce3bb49563 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 14 02:14:21 2015 +1100 drivers/i2c/w83795: Fix tautology from wrong return type The correct type-signature of 'do_smbus_write_byte' is: int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) and so storing the return type in a 'u32' is inappropriate, leading to a tautological compare of 'ret < 0' and 'err < 0'. Change-Id: I65486df7156c70af84fa00c336142d9a45998620 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/i2c/w83795/w83795.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 569fe5a..397c22c 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -24,14 +24,14 @@ #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ #include "w83795.h" -static u32 w83795_set_bank(u8 bank) +static int w83795_set_bank(u8 bank) { return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); } static u8 w83795_read(u16 reg) { - u32 ret; + int ret; ret = w83795_set_bank(reg >> 8); if (ret < 0) { @@ -45,7 +45,7 @@ static u8 w83795_read(u16 reg) static u8 w83795_write(u16 reg, u8 value) { - u32 err; + int err; err = w83795_set_bank(reg >> 8); if (err < 0) {

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New patch to review for coreboot: 56d96b4 amd/pi/00730F01/Lib/amdlib.c: Integer overflow in loop construct
by Edward O'Callaghan 13 Jan '15

13 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8208 -gerrit commit 56d96b491ad559c42721a9eba4c595bf91f505b7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 14 02:22:01 2015 +1100 amd/pi/00730F01/Lib/amdlib.c: Integer overflow in loop construct Forward port fix in: commit 'cb0dd58 Integer overflow in loop construct'. Change-Id: Id03900d9132477b5dd90cedd8af3a265e6f9165a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/pi/00730F01/Lib/amdlib.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c index 5e85f6b..369daea 100644 --- a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c @@ -381,11 +381,17 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - UINTN Index; - for (Index = 31; Index >= 0; Index--){ - if (value & (1 << Index)) break; - } - return (UINT8) Index; + uint8_t bit = 31; + do { + if (value & (1 << 31)) + return bit; + + value <<= 1; + bit--; + + } while (value != 0); + + return 0xFF; /* Error code indicating no bit found */ } AMDLIB_OPTIMIZE

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coreboot-gerrit January 2015