the following patch was just integrated into master:
commit e71928ca072b5c136f6d62382182b0b213bd063f
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Aug 18 00:38:18 2014 +0200
macbook11: New mainboard (macbook21 clone)
Tested by marcus.
Change-Id: Ifce2018ef49619b36fb07e5345d70c358a0397e4
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6698
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info(a)gluglug.org.uk>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6698 for details.
-gerrit
the following patch was just integrated into master:
commit 6a3a8ce1a81578d4461c9d4de6d59a3154f6a8a4
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Aug 17 23:48:42 2014 +0200
azalia: Move shared variable to separate file
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6695
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6695 for details.
-gerrit
the following patch was just integrated into master:
commit b46f5891d297e2440bf2f0845cb9a45de2575a40
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Aug 17 23:53:14 2014 +0200
board-info: Output errors to stdout like make lint-stable expects
Change-Id: I7eb2283808cde86c79d6b770a176daee57a7f9f2
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6696
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6696 for details.
-gerrit
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6680
-gerrit
commit a1abfc9f58c2c217a96fa18ec54d5b5258fe6e37
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Fri Aug 15 12:25:28 2014 -0600
AMD Steppe Eagle: Add northbridge HT link ID to pci_ids.h
Add a #define for the HT northbridge link ID into the "known PCI
device IDs" table.
Change-Id: If0a32b2af5df6c20e0fb5af200c06d80fab3637a
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/include/device/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 4f15c37..061a11e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -287,6 +287,7 @@
#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600
#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400
#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536
+#define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6679
-gerrit
commit da2e3275e0f93f08a08ef9a6feb32c0c5dd4ba70
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Fri Aug 15 12:15:33 2014 -0600
AMD Steppe Eagle: Add CPU files for new SoC
Add the CPU files required to support the Steppe Eagle and Mullins
models of Family 16h SoC processors from AMD. This CPU is based on
the Jaguar core and is similar to Kabini.
Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/cpu/amd/agesa/00730F01/Kconfig | 69 +++++++++++++++
src/cpu/amd/agesa/00730F01/Makefile.inc | 29 +++++++
src/cpu/amd/agesa/00730F01/acpi/cpu.asl | 82 ++++++++++++++++++
src/cpu/amd/agesa/00730F01/chip_name.c | 24 ++++++
src/cpu/amd/agesa/00730F01/model_16_init.c | 133 +++++++++++++++++++++++++++++
src/cpu/amd/agesa/Kconfig | 2 +
src/cpu/amd/agesa/Makefile.inc | 1 +
src/include/cpu/x86/lapic_def.h | 4 +
8 files changed, 344 insertions(+)
diff --git a/src/cpu/amd/agesa/00730F01/Kconfig b/src/cpu/amd/agesa/00730F01/Kconfig
new file mode 100644
index 0000000..ccc44d6
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/Kconfig
@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config CPU_AMD_AGESA_00730F01
+ bool
+ select PCI_IO_CFG_EXT
+ select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_AGESA_00730F01
+
+config CPU_ADDR_BITS
+ int
+ default 40
+
+config CPU_SOCKET_TYPE
+ hex
+ default 0x10
+
+# DDR2 and REG
+config DIMM_SUPPORT
+ hex
+ default 0x0104
+
+config EXT_RT_TBL_SUPPORT
+ bool
+ default n
+
+config EXT_CONF_SUPPORT
+ bool
+ default n
+
+config CBB
+ hex
+ default 0x0
+
+config CDB
+ hex
+ default 0x18
+
+config XIP_ROM_BASE
+ hex
+ default 0xfff80000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x100000
+
+config HIGH_SCRATCH_MEMORY_SIZE
+ hex
+ # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
+ default 0xA1000
+
+endif
diff --git a/src/cpu/amd/agesa/00730F01/Makefile.inc b/src/cpu/amd/agesa/00730F01/Makefile.inc
new file mode 100644
index 0000000..fba2185
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/Makefile.inc
@@ -0,0 +1,29 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += chip_name.c
+ramstage-y += model_16_init.c
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl b/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
new file mode 100644
index 0000000..9d1a75b
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Processor Object
+ *
+ */
+Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+} /* End _PR scope */
diff --git a/src/cpu/amd/agesa/00730F01/chip_name.c b/src/cpu/amd/agesa/00730F01/chip_name.c
new file mode 100644
index 0000000..7a1c06c
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/chip_name.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations cpu_amd_agesa_00730F01_ops = {
+ CHIP_NAME("AMD CPU Family 16h")
+};
diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c
new file mode 100644
index 0000000..8053fd1
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/model_16_init.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+#include <arch/acpi.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <cpu/amd/agesa/s3_resume.h>
+#endif
+
+static void model_16_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Model 16 Init.\n");
+
+ u8 i;
+ msr_t msr;
+ int msrno;
+#if CONFIG_LOGICAL_CPUS
+ u32 siblings;
+#endif
+
+ //x86_enable_cache();
+ //amd_setup_mtrrs();
+ //x86_mtrr_check();
+ disable_cache ();
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+ // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
+ msr.lo = msr.hi = 0;
+ wrmsr (0x259, msr);
+ msr.lo = msr.hi = 0x1e1e1e1e;
+ wrmsr(0x250, msr);
+ wrmsr(0x258, msr);
+ for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr (msrno, msr);
+
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3)
+ restore_mtrr();
+#endif
+
+ x86_mtrr_check();
+ x86_enable_cache();
+
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < 6; i++) {
+ wrmsr(MCI_STATUS + (i * 4), msr);
+ }
+
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS
+ siblings = cpuid_ecx(0x80000008) & 0xff;
+
+ if (siblings > 0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1 << (33 - 32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+ /* DisableCf8ExtCfg */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.hi &= ~(1 << (46 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+
+
+ /* Write protect SMM space with SMMLOCK. */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_16_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x730f00 }, /* ML-A0, Guess, TODO: */
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_16 __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index fcba0cf..d288fef 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -25,6 +25,7 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY15
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
+ default y if CPU_AMD_AGESA_00730F01
default n
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
@@ -84,4 +85,5 @@ source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
source src/cpu/amd/agesa/family16kb/Kconfig
+source src/cpu/amd/agesa/00730F01/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index beba040..800f8e7 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
+subdirs-$(CONFIG_CPU_AMD_AGESA_00730F01) += 00730F01
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h
index f96b53b..2b1ca5a 100644
--- a/src/include/cpu/x86/lapic_def.h
+++ b/src/include/cpu/x86/lapic_def.h
@@ -6,8 +6,12 @@
#define LAPIC_BASE_MSR_ENABLE (1 << 11)
#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+#ifndef LOCAL_APIC_ADDR
#define LOCAL_APIC_ADDR 0xfee00000
+#endif
+#ifndef LAPIC_DEFAULT_BASE
#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
+#endif
#define LAPIC_ID 0x020
#define LAPIC_LVR 0x030
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6678
-gerrit
commit 618956328ff71d454537e86d799ac09a3c3fea1b
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Fri Aug 15 11:46:25 2014 -0600
AMD Steppe Eagle: Add northbridge files for new SoC family
Add the northbridge file for AMD's new Mullins and Steppe Eagle
processor family. Since the processor family name is not the
same across AMD's sales and marketing channels, I have elected
to use part of the processor ID as the family name. The intent
is to reduce confusion since the processor ID is the same for
both families. This northbridge support has only been validated
on the AMD Embedded variants ("Steppe Eagle").
Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/northbridge/amd/agesa/00730F01/Kconfig | 53 +
src/northbridge/amd/agesa/00730F01/Makefile.inc | 25 +
.../amd/agesa/00730F01/acpi/northbridge.asl | 100 ++
.../amd/agesa/00730F01/callouts_for_00730F01.c | 37 +
.../amd/agesa/00730F01/callouts_for_00730F01.h | 28 +
src/northbridge/amd/agesa/00730F01/chip.h | 28 +
src/northbridge/amd/agesa/00730F01/dimmSpd.c | 160 +++
src/northbridge/amd/agesa/00730F01/dimmSpd.h | 26 +
src/northbridge/amd/agesa/00730F01/northbridge.c | 1145 ++++++++++++++++++++
src/northbridge/amd/agesa/00730F01/northbridge.h | 26 +
src/northbridge/amd/agesa/Kconfig | 1 +
src/northbridge/amd/agesa/Makefile.inc | 1 +
src/northbridge/amd/agesa/common/Makefile.inc | 23 +
src/northbridge/amd/agesa/common/common.c | 83 ++
src/northbridge/amd/agesa/common/common.h | 34 +
src/northbridge/amd/agesa/def_callouts.c | 2 +-
src/northbridge/amd/agesa/def_callouts.h | 2 +-
17 files changed, 1772 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/agesa/00730F01/Kconfig b/src/northbridge/amd/agesa/00730F01/Kconfig
new file mode 100644
index 0000000..36bc0fc
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2014 Sage Electronic Engineering, LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+config NORTHBRIDGE_AMD_AGESA_00730F01
+ bool
+ select MMCONF_SUPPORT
+
+if NORTHBRIDGE_AMD_AGESA_00730F01
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xF8000000
+
+config MMCONF_BUS_NUMBER
+ int
+ default 64
+
+config VGA_BIOS_ID
+ string
+ default "1002,9850"
+ help
+ The default VGA BIOS PCI vendor/device ID should be set to the
+ result of the map_oprom_vendev() function in northbridge.c.
+
+config VGA_BIOS_FILE
+ string
+ default "3rdparty/northbridge/amd/00730F01/VBIOS.bin"
+
+endif
diff --git a/src/northbridge/amd/agesa/00730F01/Makefile.inc b/src/northbridge/amd/agesa/00730F01/Makefile.inc
new file mode 100644
index 0000000..b56b541
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/Makefile.inc
@@ -0,0 +1,25 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += callouts_for_00730F01.c
+romstage-y += dimmSpd.c
+
+ramstage-y += northbridge.c
+ramstage-y += callouts_for_00730F01.c
+ramstage-y += dimmSpd.c
diff --git a/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl b/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl
new file mode 100644
index 0000000..37aba9a
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
+Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
+{
+ Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+ Return(0x0B) /* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+ If(PMOD)
+ {
+ Return(APR0) /* APIC mode */
+ }
+ Return (PR0) /* PIC Mode */
+}
+
+Device(AMRT) {
+ Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Gpp 0 */
+Device(PBR4) {
+ Name(_ADR, 0x00020001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR4 */
+
+/* Gpp 1 */
+Device(PBR5) {
+ Name(_ADR, 0x00020002)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR5 */
+
+/* Gpp 2 */
+Device(PBR6) {
+ Name(_ADR, 0x00020003)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR6 */
+
+/* Gpp 3 */
+Device(PBR7) {
+ Name(_ADR, 0x00020004)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR7 */
+
+/* Gpp 4 */
+Device(PBR8) {
+ Name(_ADR, 0x00020005)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS8) } /* APIC mode */
+ Return (PS8) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR8 */
diff --git a/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.c b/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.c
new file mode 100644
index 0000000..91bf338
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#include "dimmSpd.h"
+#include "callouts_for_00730F01.h"
+#include "northbridge/amd/agesa/def_callouts.h"
+
+AGESA_STATUS ReadSpd_00730F01 (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
+ return Status;
+}
diff --git a/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.h b/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.h
new file mode 100644
index 0000000..4bf27f8
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CALLOUTS_AMD_AGESA_FAM16_0X30_H
+#define CALLOUTS_AMD_AGESA_FAM16_0X30_H
+
+#include "Porting.h"
+#include "AGESA.h"
+
+AGESA_STATUS ReadSpd_00730F01 (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+#endif /* CALLOUTS_AMD_AGESA_FAM16_0X30_H */
diff --git a/src/northbridge/amd/agesa/00730F01/chip.h b/src/northbridge/amd/agesa/00730F01/chip.h
new file mode 100644
index 0000000..0223d3b
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESA_00730F01_CHIP_H_
+#define _AGESA_00730F01_CHIP_H_
+
+struct northbridge_amd_agesa_00730F01_config
+{
+ u8 spdAddrLookup[1][1][2];
+};
+
+#endif
diff --git a/src/northbridge/amd/agesa/00730F01/dimmSpd.c b/src/northbridge/amd/agesa/00730F01/dimmSpd.c
new file mode 100644
index 0000000..3d14beb
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/dimmSpd.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "chip.h"
+
+
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ address |= 1; // set read bit
+
+ __outbyte (iobase + 0, 0xFF); // clear error status
+ __outbyte (iobase + 1, 0x1F); // clear error status
+ __outbyte (iobase + 3, offset); // offset in eeprom
+ __outbyte (iobase + 4, address); // slave address and read bit
+ __outbyte (iobase + 2, 0x48); // read byte command
+
+ // time limit to avoid hanging for unexpected error status (should never happen)
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = __inbyte (iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = __inbyte (iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ * this function is faster function readSmbusByteData
+ */
+
+static int readSmbusByte (int iobase, int address, char *buffer)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ __outbyte (iobase + 0, 0xFF); // clear error status
+ __outbyte (iobase + 2, 0x44); // read command
+
+ // time limit to avoid hanging for unexpected error status
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = __inbyte (iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = __inbyte (iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Optimization relies on autoincrement to avoid
+ * sending offset for every byte.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
+{
+ int index, error;
+
+ /* read the first byte using offset zero */
+ error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+ if (error) return error;
+
+ /* read the remaining bytes using auto-increment for speed */
+ for (index = 1; index < count; index++)
+ {
+ error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+ if (error) return error;
+ }
+
+ return 0;
+}
+
+static void writePmReg (int reg, int data)
+{
+ __outbyte (0xCD6, reg);
+ __outbyte (0xCD7, data);
+}
+
+static void setupFch (int ioBase)
+{
+ writePmReg (0x2D, ioBase >> 8);
+ writePmReg (0x2C, ioBase | 1);
+ __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+}
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+ int spdAddress, ioBase;
+ ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ ROMSTAGE_CONST struct northbridge_amd_agesa_00730F01_config *config = dev->chip_info;
+
+ if ((dev == 0) || (config == 0))
+ return AGESA_ERROR;
+
+ if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
+ return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
+ return AGESA_ERROR;
+ if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
+ return AGESA_ERROR;
+
+ spdAddress = config->spdAddrLookup
+ [info->SocketId] [info->MemChannelId] [info->DimmId];
+
+ if (spdAddress == 0) return AGESA_ERROR;
+ ioBase = 0xB00;
+ setupFch (ioBase);
+ return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+}
diff --git a/src/northbridge/amd/agesa/00730F01/dimmSpd.h b/src/northbridge/amd/agesa/00730F01/dimmSpd.h
new file mode 100644
index 0000000..667fe26
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/dimmSpd.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+AGESA_STATUS
+AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
+
+#endif
diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c
new file mode 100644
index 0000000..3df4ba1
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/northbridge.c
@@ -0,0 +1,1145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <lib.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+
+#include <Porting.h>
+#include <AGESA.h>
+#include <FieldAccessors.h>
+#include <Options.h>
+#include <Topology.h>
+#include <cpu/amd/amdfam16.h>
+#include <cpuRegisters.h>
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/agesawrapper_call.h>
+#include "northbridge.h"
+
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/mtrr.h>
+
+#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
+
+#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
+#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
+#endif
+
+typedef struct dram_base_mask {
+ u32 base; //[47:27] at [28:8]
+ u32 mask; //[47:27] at [28:8] and enable at bit 0
+} dram_base_mask_t;
+
+static unsigned node_nums;
+static unsigned sblink;
+static device_t __f0_dev[MAX_NODE_NUMS];
+static device_t __f1_dev[MAX_NODE_NUMS];
+static device_t __f2_dev[MAX_NODE_NUMS];
+static device_t __f4_dev[MAX_NODE_NUMS];
+static unsigned fx_devs = 0;
+
+static dram_base_mask_t get_dram_base_mask(u32 nodeid)
+{
+ device_t dev;
+ dram_base_mask_t d;
+ dev = __f1_dev[0];
+ u32 temp;
+ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
+ d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
+ temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+ d.mask |= temp<<21;
+ temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
+ d.mask |= (temp & 1); // enable bit
+ d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
+ temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+ d.base |= temp<<21;
+ return d;
+}
+
+static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+ u32 io_min, u32 io_max)
+{
+ u32 i;
+ u32 tempreg;
+ /* io range allocation */
+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
+ for (i=0; i<node_nums; i++)
+ pci_write_config32(__f1_dev[i], reg+4, tempreg);
+ tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+#if 0
+ // FIXME: can we use VGA reg instead?
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+ __func__, dev_path(dev), link);
+ tempreg |= PCI_IO_BASE_VGA_EN;
+ }
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+ tempreg |= PCI_IO_BASE_NO_ISA;
+ }
+#endif
+ for (i=0; i<node_nums; i++)
+ pci_write_config32(__f1_dev[i], reg, tempreg);
+}
+
+static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
+{
+ u32 i;
+ u32 tempreg;
+ /* io range allocation */
+ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
+ for (i=0; i<nodes; i++)
+ pci_write_config32(__f1_dev[i], reg+4, tempreg);
+ tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+ for (i=0; i<node_nums; i++)
+ pci_write_config32(__f1_dev[i], reg, tempreg);
+}
+
+static device_t get_node_pci(u32 nodeid, u32 fn)
+{
+#if MAX_NODE_NUMS + CONFIG_CDB >= 32
+ if ((CONFIG_CDB + nodeid) < 32) {
+ return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+ } else {
+ return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
+ }
+#else
+ return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+#endif
+}
+
+static void get_fx_devs(void)
+{
+ int i;
+ for (i = 0; i < MAX_NODE_NUMS; i++) {
+ __f0_dev[i] = get_node_pci(i, 0);
+ __f1_dev[i] = get_node_pci(i, 1);
+ __f2_dev[i] = get_node_pci(i, 2);
+ __f4_dev[i] = get_node_pci(i, 4);
+ if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+ fx_devs = i+1;
+ }
+ if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+ die("Cannot find 0:0x18.[0|1]\n");
+ }
+ printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+}
+
+static u32 f1_read_config32(unsigned reg)
+{
+ if (fx_devs == 0)
+ get_fx_devs();
+ return pci_read_config32(__f1_dev[0], reg);
+}
+
+static void f1_write_config32(unsigned reg, u32 value)
+{
+ int i;
+ if (fx_devs == 0)
+ get_fx_devs();
+ for(i = 0; i < fx_devs; i++) {
+ device_t dev;
+ dev = __f1_dev[i];
+ if (dev && dev->enabled) {
+ pci_write_config32(dev, reg, value);
+ }
+ }
+}
+
+static u32 amdfam16_nodeid(device_t dev)
+{
+#if MAX_NODE_NUMS == 64
+ unsigned busn;
+ busn = dev->bus->secondary;
+ if (busn != CONFIG_CBB) {
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
+ } else {
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+ }
+
+#else
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+#endif
+}
+
+static void set_vga_enable_reg(u32 nodeid, u32 linkn)
+{
+ u32 val;
+
+ val = 1 | (nodeid<<4) | (linkn<<12);
+ /* it will routing
+ * (1)mmio 0xa0000:0xbffff
+ * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
+ */
+ f1_write_config32(0xf4, val);
+
+}
+
+/**
+ * @return
+ * @retval 2 resoure does not exist, usable
+ * @retval 0 resource exists, not usable
+ * @retval 1 resource exist, resource has been allocated before
+ */
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+ unsigned goal_link)
+{
+ struct resource *res;
+ unsigned nodeid, link = 0;
+ int result;
+ res = 0;
+ for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
+ device_t dev;
+ dev = __f0_dev[nodeid];
+ if (!dev)
+ continue;
+ for (link = 0; !res && (link < 8); link++) {
+ res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
+ }
+ }
+ result = 2;
+ if (res) {
+ result = 0;
+ if ((goal_link == (link - 1)) &&
+ (goal_nodeid == (nodeid - 1)) &&
+ (res->flags <= 1)) {
+ result = 1;
+ }
+ }
+ return result;
+}
+
+static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+{
+ struct resource *resource;
+ u32 free_reg, reg;
+ resource = 0;
+ free_reg = 0;
+ for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+ int result;
+ result = reg_useable(reg, dev, nodeid, link);
+ if (result == 1) {
+ /* I have been allocated this one */
+ break;
+ }
+ else if (result > 1) {
+ /* I have a free register pair */
+ free_reg = reg;
+ }
+ }
+ if (reg > 0xd8) {
+ reg = free_reg; // if no free, the free_reg still be 0
+ }
+
+ resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+
+ return resource;
+}
+
+static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link)
+{
+ struct resource *resource;
+ u32 free_reg, reg;
+ resource = 0;
+ free_reg = 0;
+ for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
+ int result;
+ result = reg_useable(reg, dev, nodeid, link);
+ if (result == 1) {
+ /* I have been allocated this one */
+ break;
+ }
+ else if (result > 1) {
+ /* I have a free register pair */
+ free_reg = reg;
+ }
+ }
+ if (reg > 0xb8) {
+ reg = free_reg;
+ }
+
+ resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+ return resource;
+}
+
+static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
+{
+ struct resource *resource;
+
+ /* Initialize the io space constraints on the current bus */
+ resource = amdfam16_find_iopair(dev, nodeid, link);
+ if (resource) {
+ u32 align;
+ align = log2(HT_IO_HOST_ALIGN);
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = align;
+ resource->gran = align;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+ }
+
+ /* Initialize the prefetchable memory constraints on the current bus */
+ resource = amdfam16_find_mempair(dev, nodeid, link);
+ if (resource) {
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->limit = 0xffffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ resource->flags |= IORESOURCE_BRIDGE;
+ }
+
+ /* Initialize the memory constraints on the current bus */
+ resource = amdfam16_find_mempair(dev, nodeid, link);
+ if (resource) {
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->limit = 0xffffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+ }
+
+}
+
+static void read_resources(device_t dev)
+{
+ u32 nodeid;
+ struct bus *link;
+
+ nodeid = amdfam16_nodeid(dev);
+ for (link = dev->link_list; link; link = link->next) {
+ if (link->children) {
+ amdfam16_link_read_bases(dev, nodeid, link->link_num);
+ }
+ }
+}
+
+static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
+{
+ resource_t rbase, rend;
+ unsigned reg, link_num;
+ char buf[50];
+
+ /* Make certain the resource has actually been set */
+ if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+ return;
+ }
+
+ /* If I have already stored this resource don't worry about it */
+ if (resource->flags & IORESOURCE_STORED) {
+ return;
+ }
+
+ /* Only handle PCI memory and IO resources */
+ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+ return;
+
+ /* Ensure I am actually looking at a resource of function 1 */
+ if ((resource->index & 0xffff) < 0x1000) {
+ return;
+ }
+ /* Get the base address */
+ rbase = resource->base;
+
+ /* Get the limit (rounded up) */
+ rend = resource_end(resource);
+
+ /* Get the register and link */
+ reg = resource->index & 0xfff; // 4k
+ link_num = IOINDEX_LINK(resource->index);
+
+ if (resource->flags & IORESOURCE_IO) {
+ set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
+ }
+ else if (resource->flags & IORESOURCE_MEM) {
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8]
+ }
+ resource->flags |= IORESOURCE_STORED;
+ snprintf(buf, sizeof (buf), " <node %x link %x>",
+ nodeid, link_num);
+ report_resource_stored(dev, resource, buf);
+}
+
+/**
+ * I tried to reuse the resource allocation code in set_resource()
+ * but it is too difficult to deal with the resource allocation magic.
+ */
+
+static void create_vga_resource(device_t dev, unsigned nodeid)
+{
+ struct bus *link;
+
+ /* find out which link the VGA card is connected,
+ * we only deal with the 'first' vga card */
+ for (link = dev->link_list; link; link = link->next) {
+ if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
+ extern device_t vga_pri; // the primary vga device, defined in device.c
+ printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
+ link->secondary,link->subordinate);
+ /* We need to make sure the vga_pri is under the link */
+ if((vga_pri->bus->secondary >= link->secondary ) &&
+ (vga_pri->bus->secondary <= link->subordinate )
+ )
+#endif
+ break;
+ }
+ }
+
+ /* no VGA card installed */
+ if (link == NULL)
+ return;
+
+ printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
+ set_vga_enable_reg(nodeid, sblink);
+}
+
+static void set_resources(device_t dev)
+{
+ unsigned nodeid;
+ struct bus *bus;
+ struct resource *res;
+
+ /* Find the nodeid */
+ nodeid = amdfam16_nodeid(dev);
+
+ create_vga_resource(dev, nodeid); //TODO: do we need this?
+
+ /* Set each resource we have found */
+ for (res = dev->resource_list; res; res = res->next) {
+ set_resource(dev, res, nodeid);
+ }
+
+ for (bus = dev->link_list; bus; bus = bus->next) {
+ if (bus->children) {
+ assign_resources(bus);
+ }
+ }
+}
+
+static void northbridge_init(struct device *dev)
+{
+}
+#if 0 /* TODO: Check if needed. */
+static unsigned scan_chains(device_t dev, unsigned max)
+{
+ unsigned nodeid;
+ struct bus *link;
+ device_t io_hub = NULL;
+ u32 next_unitid = 0x18;
+ nodeid = amdfam16_nodeid(dev);
+ if (nodeid == 0) {
+ for (link = dev->link_list; link; link = link->next) {
+ //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */
+ if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
+ io_hub = link->children;
+ if (!io_hub || !io_hub->enabled) {
+ die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
+ }
+ /* Now that nothing is overlapping it is safe to scan the children. */
+ max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0);
+ }
+ }
+ }
+ return max;
+}
+#endif
+static struct device_operations northbridge_operations = {
+ .read_resources = read_resources,
+ .set_resources = set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ //.scan_bus = scan_chains, /* TODO: */
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver family16_northbridge __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT,
+};
+
+static const struct pci_driver family10_northbridge __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_10H_NB_HT,
+};
+
+struct chip_operations northbridge_amd_agesa_00730F01_ops = {
+ CHIP_NAME("AMD FAM16 Northbridge")
+ .enable_dev = 0,
+};
+
+static void domain_read_resources(device_t dev)
+{
+ unsigned reg;
+
+ /* Find the already assigned resource pairs */
+ get_fx_devs();
+ for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
+ u32 base, limit;
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x04);
+ /* Is this register allocated? */
+ if ((base & 3) != 0) {
+ unsigned nodeid, reg_link;
+ device_t reg_dev;
+ if (reg<0xc0) { // mmio
+ nodeid = (limit & 0xf) + (base&0x30);
+ } else { // io
+ nodeid = (limit & 0xf) + ((base>>4)&0x30);
+ }
+ reg_link = (limit >> 4) & 7;
+ reg_dev = __f0_dev[nodeid];
+ if (reg_dev) {
+ /* Reserve the resource */
+ struct resource *res;
+ res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+ if (res) {
+ res->flags = 1;
+ }
+ }
+ }
+ }
+ /* FIXME: do we need to check extend conf space?
+ I don't believe that much preset value */
+
+#if !CONFIG_PCI_64BIT_PREF_MEM
+ pci_domain_read_resources(dev);
+
+#else
+ struct bus *link;
+ struct resource *resource;
+ for (link=dev->link_list; link; link = link->next) {
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, 0|(link->link_num<<2));
+ resource->base = 0x400;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO;
+
+ /* Initialize the system wide prefetchable memory resources constraints */
+ resource = new_resource(dev, 1|(link->link_num<<2));
+ resource->limit = 0xfcffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, 2|(link->link_num<<2));
+ resource->limit = 0xfcffffffffULL;
+ resource->flags = IORESOURCE_MEM;
+ }
+#endif
+}
+
+static void domain_enable_resources(device_t dev)
+{
+ if (acpi_is_wakeup_s3())
+ AGESAWRAPPER(fchs3laterestore);
+
+ /* Must be called after PCI enumeration and resource allocation */
+ if (!acpi_is_wakeup_s3())
+ AGESAWRAPPER(amdinitmid);
+
+ printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
+}
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+struct hw_mem_hole_info {
+ unsigned hole_startk;
+ int node_id;
+};
+static struct hw_mem_hole_info get_hw_mem_hole_info(void)
+{
+ struct hw_mem_hole_info mem_hole;
+ int i;
+ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+ mem_hole.node_id = -1;
+ for (i = 0; i < node_nums; i++) {
+ dram_base_mask_t d;
+ u32 hole;
+ d = get_dram_base_mask(i);
+ if (!(d.mask & 1)) continue; // no memory on this node
+ hole = pci_read_config32(__f1_dev[i], 0xf0);
+ if (hole & 2) { // we find the hole
+ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+ mem_hole.node_id = i; // record the node No with hole
+ break; // only one hole
+ }
+ }
+
+ /* We need to double check if there is special set on base reg and limit reg
+ * are not continuous instead of hole, it will find out its hole_startk.
+ */
+ if (mem_hole.node_id == -1) {
+ resource_t limitk_pri = 0;
+ for (i=0; i<node_nums; i++) {
+ dram_base_mask_t d;
+ resource_t base_k, limit_k;
+ d = get_dram_base_mask(i);
+ if (!(d.base & 1)) continue;
+ base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+ if (base_k > 4 *1024 * 1024) break; // don't need to go to check
+ if (limitk_pri != base_k) { // we find the hole
+ mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
+ mem_hole.node_id = i;
+ break; //only one hole
+ }
+ limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
+ limitk_pri = limit_k;
+ }
+ }
+ return mem_hole;
+}
+#endif
+
+#define ONE_MB_SHIFT 20
+
+static void setup_uma_memory(void)
+{
+#if CONFIG_GFXUMA
+ uint32_t topmem = (uint32_t) bsp_topmem();
+ uint32_t sys_mem;
+
+ /* refer to UMA Size Consideration in Family16h BKDG. */
+ /* Please reference MemNGetUmaSizeOR () */
+ /*
+ * Total system memory UMASize
+ * >= 2G 512M
+ * >=1G 256M
+ * <1G 64M
+ */
+ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
+ if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
+ uma_memory_size = 512 << ONE_MB_SHIFT;
+ } else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
+ uma_memory_size = 256 << ONE_MB_SHIFT;
+ } else {
+ uma_memory_size = 64 << ONE_MB_SHIFT;
+ }
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
+
+ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
+
+ /* TODO: TOP_MEM2 */
+#endif
+}
+
+
+static void domain_set_resources(device_t dev)
+{
+#if CONFIG_PCI_64BIT_PREF_MEM
+ struct resource *io, *mem1, *mem2;
+ struct resource *res;
+#endif
+ unsigned long mmio_basek;
+ u32 pci_tolm;
+ u64 ramtop = 0;
+ int i, idx;
+ struct bus *link;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ struct hw_mem_hole_info mem_hole;
+ u32 reset_memhole = 1;
+#endif
+
+#if CONFIG_PCI_64BIT_PREF_MEM
+
+ for (link = dev->link_list; link; link = link->next) {
+ /* Now reallocate the pci resources memory with the
+ * highest addresses I can manage.
+ */
+ mem1 = find_resource(dev, 1|(link->link_num<<2));
+ mem2 = find_resource(dev, 2|(link->link_num<<2));
+
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
+
+ /* See if both resources have roughly the same limits */
+ if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+ ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+ {
+ /* If so place the one with the most stringent alignment first */
+ if (mem2->align > mem1->align) {
+ struct resource *tmp;
+ tmp = mem1;
+ mem1 = mem2;
+ mem2 = tmp;
+ }
+ /* Now place the memory as high up as it will go */
+ mem2->base = resource_max(mem2);
+ mem1->limit = mem2->base - 1;
+ mem1->base = resource_max(mem1);
+ }
+ else {
+ /* Place the resources as high up as they will go */
+ mem2->base = resource_max(mem2);
+ mem1->base = resource_max(mem1);
+ }
+
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
+ }
+
+ for (res = &dev->resource_list; res; res = res->next)
+ {
+ res->flags |= IORESOURCE_ASSIGNED;
+ res->flags |= IORESOURCE_STORED;
+ report_resource_stored(dev, res, "");
+ }
+#endif
+
+ pci_tolm = 0xffffffffUL;
+ for (link = dev->link_list; link; link = link->next) {
+ pci_tolm = find_pci_tolm(link);
+ }
+
+ // FIXME handle interleaved nodes. If you fix this here, please fix
+ // amdk8, too.
+ mmio_basek = pci_tolm >> 10;
+ /* Round mmio_basek to something the processor can support */
+ mmio_basek &= ~((1 << 6) -1);
+
+ // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+ // MMIO hole. If you fix this here, please fix amdk8, too.
+ /* Round the mmio hole to 64M */
+ mmio_basek &= ~((64*1024) - 1);
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ /* if the hw mem hole is already set in raminit stage, here we will compare
+ * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
+ * use hole_basek as mmio_basek and we don't need to reset hole.
+ * otherwise We reset the hole to the mmio_basek
+ */
+
+ mem_hole = get_hw_mem_hole_info();
+
+ // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
+ mmio_basek = mem_hole.hole_startk;
+ reset_memhole = 0;
+ }
+#endif
+
+ idx = 0x10;
+ for (i = 0; i < node_nums; i++) {
+ dram_base_mask_t d;
+ resource_t basek, limitk, sizek; // 4 1T
+
+ d = get_dram_base_mask(i);
+
+ if (!(d.mask & 1)) continue;
+ basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
+ limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ;
+
+ sizek = limitk - basek;
+
+ /* see if we need a hole from 0xa0000 to 0xbffff */
+ if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
+ ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
+ idx += 0x10;
+ basek = (8*64)+(16*16);
+ sizek = limitk - ((8*64)+(16*16));
+
+ }
+
+ //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
+
+ /* split the region to accommodate pci memory space */
+ if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if (basek <= mmio_basek) {
+ unsigned pre_sizek;
+ pre_sizek = mmio_basek - basek;
+ if (pre_sizek>0) {
+ ram_resource(dev, (idx | i), basek, pre_sizek);
+ idx += 0x10;
+ sizek -= pre_sizek;
+ if (!ramtop)
+ ramtop = mmio_basek * 1024;
+ }
+ basek = mmio_basek;
+ }
+ if ((basek + sizek) <= 4*1024*1024) {
+ sizek = 0;
+ }
+ else {
+ uint64_t topmem2 = bsp_topmem2();
+ basek = 4*1024*1024;
+ sizek = topmem2/1024 - basek;
+ }
+ }
+
+ ram_resource(dev, (idx | i), basek, sizek);
+ idx += 0x10;
+ printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+ i, mmio_basek, basek, limitk);
+ if (!ramtop)
+ ramtop = limitk * 1024;
+ }
+
+#if CONFIG_GFXUMA
+ set_top_of_ram(uma_memory_base);
+ uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
+#else
+ set_top_of_ram(ramtop);
+#endif
+
+ for(link = dev->link_list; link; link = link->next) {
+ if (link->children) {
+ assign_resources(link);
+ }
+ }
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = domain_read_resources,
+ .set_resources = domain_set_resources,
+ .enable_resources = domain_enable_resources,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void sysconf_init(device_t dev) // first node
+{
+ sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
+ node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
+}
+
+static void add_more_links(device_t dev, unsigned total_links)
+{
+ struct bus *link, *last = NULL;
+ int link_num;
+
+ for (link = dev->link_list; link; link = link->next)
+ last = link;
+
+ if (last) {
+ int links = total_links - last->link_num;
+ link_num = last->link_num;
+ if (links > 0) {
+ link = malloc(links*sizeof(*link));
+ if (!link)
+ die("Couldn't allocate more links!\n");
+ memset(link, 0, links*sizeof(*link));
+ last->next = link;
+ }
+ }
+ else {
+ link_num = -1;
+ link = malloc(total_links*sizeof(*link));
+ memset(link, 0, total_links*sizeof(*link));
+ dev->link_list = link;
+ }
+
+ for (link_num = link_num + 1; link_num < total_links; link_num++) {
+ link->link_num = link_num;
+ link->dev = dev;
+ link->next = link + 1;
+ last = link;
+ link = link->next;
+ }
+ last->next = NULL;
+}
+
+static u32 cpu_bus_scan(device_t dev, u32 max)
+{
+ struct bus *cpu_bus;
+ device_t dev_mc;
+#if CONFIG_CBB
+ device_t pci_domain;
+#endif
+ int i,j;
+ int coreid_bits;
+ int core_max = 0;
+ unsigned ApicIdCoreIdSize;
+ unsigned core_nums;
+ int siblings = 0;
+ unsigned int family;
+ u32 modules = 0;
+ VOID* modules_ptr = &modules;
+ BUILD_OPT_CFG* options = NULL;
+ int ioapic_count = 0;
+
+ // TODO Remove the printk's.
+ printk(BIOS_SPEW, "MullinsPI Debug: Grabbing the AMD Topology Information.\n");
+ AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options));
+ AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules));
+ modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1);
+ ASSERT(modules > 0);
+ ASSERT(options);
+ ioapic_count = (int)options->CfgPlatNumIoApics;
+ ASSERT(ioapic_count > 0);
+ printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
+ printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
+
+#if CONFIG_CBB
+ dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
+ if (dev_mc && dev_mc->bus) {
+ printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
+ pci_domain = dev_mc->bus->dev;
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
+ printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
+ dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+ printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
+ } else {
+ printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+ if (!dev_mc) {
+ dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ if (dev_mc && dev_mc->bus) {
+ printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
+ pci_domain = dev_mc->bus->dev;
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
+ if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
+ printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+ dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+ printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+ while (dev_mc) {
+ printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+ dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
+ printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+ dev_mc = dev_mc->sibling;
+ }
+ }
+ }
+ }
+ }
+#endif
+ dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+ if (!dev_mc) {
+ printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+ die("");
+ }
+ sysconf_init(dev_mc);
+#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
+ if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (pci_domain->link_list && !pci_domain->link_list->next) {
+ struct bus *new_link = new_link(pci_domain);
+ pci_domain->link_list->next = new_link;
+ new_link->link_num = 1;
+ new_link->dev = pci_domain;
+ new_link->children = 0;
+ printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
+ }
+ pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
+ }
+#endif
+
+ /* Get Max Number of cores(MNC) */
+ coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ core_max = 1 << (coreid_bits & 0x000F); //mnc
+
+ ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
+ if (ApicIdCoreIdSize) {
+ core_nums = (1 << ApicIdCoreIdSize) - 1;
+ } else {
+ core_nums = 3; //quad core
+ }
+
+ /* Find which cpus are present */
+ cpu_bus = dev->link_list;
+ for (i = 0; i < node_nums; i++) {
+ device_t cdb_dev;
+ unsigned busn, devn;
+ struct bus *pbus;
+
+ busn = CONFIG_CBB;
+ devn = CONFIG_CDB + i;
+ pbus = dev_mc->bus;
+#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
+ if (i >= 32) {
+ busn--;
+ devn -= 32;
+ pbus = pci_domain->link_list->next;
+ }
+#endif
+
+ /* Find the cpu's pci device */
+ cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+ if (!cdb_dev) {
+ /* If I am probing things in a weird order
+ * ensure all of the cpu's pci devices are found.
+ */
+ int fn;
+ for(fn = 0; fn <= 5; fn++) { //FBDIMM?
+ cdb_dev = pci_probe_dev(NULL, pbus,
+ PCI_DEVFN(devn, fn));
+ }
+ cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+ } else {
+ /* Ok, We need to set the links for that device.
+ * otherwise the device under it will not be scanned
+ */
+ int linknum;
+#if CONFIG_HT3_SUPPORT
+ linknum = 8;
+#else
+ linknum = 4;
+#endif
+ add_more_links(cdb_dev, linknum);
+ }
+
+ family = cpuid_eax(1);
+ family = (family >> 20) & 0xFF;
+ if (family == 1) { //f10
+ u32 dword;
+ cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
+ dword = pci_read_config32(cdb_dev, 0xe8);
+ siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
+ } else if (family == 7) {//f16
+ cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
+ if (cdb_dev && cdb_dev->enabled) {
+ siblings = pci_read_config32(cdb_dev, 0x84);
+ siblings &= 0xFF;
+ }
+ } else {
+ siblings = 0; //default one core
+ }
+ int enable_node = cdb_dev && cdb_dev->enabled;
+ printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
+
+ for (j = 0; j <= siblings; j++ ) {
+ u32 lapicid_start = 0;
+
+ /*
+ * APIC ID calucation is tightly coupled with AGESA v5 code.
+ * This calculation MUST match the assignment calculation done
+ * in LocalApicInitializationAtEarly() function.
+ * And reference GetLocalApicIdForCore()
+ *
+ * Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ *
+ * This is needed because many IO-APIC devices only have 4 bits
+ * for their APIC id and therefore must reside at 0..15
+ */
+ if ((node_nums * core_max) + ioapic_count >= 0x10) {
+ lapicid_start = (ioapic_count - 1) / core_max;
+ lapicid_start = (lapicid_start + 1) * core_max;
+ printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+ }
+ u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ i, j, apic_id);
+
+ device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
+ if (cpu)
+ amd_cpu_topology(cpu, i, j);
+ } //j
+ }
+ return max;
+}
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static void cpu_bus_read_resources(device_t dev)
+{
+#if CONFIG_MMCONF_SUPPORT
+ struct resource *resource = new_resource(dev, 0xc0010058);
+ resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+ resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+ struct resource *resource = find_resource(dev, 0xc0010058);
+ if (resource) {
+ report_resource_stored(dev, resource, " <mmconfig>");
+ }
+ pci_dev_set_resources(dev);
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_read_resources,
+ .set_resources = cpu_bus_set_resources,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = cpu_bus_scan,
+};
+
+static void root_complex_enable_dev(struct device *dev)
+{
+ static int done = 0;
+
+ /* Do not delay UMA setup, as a device on the PCI bus may evaluate
+ the global uma_memory variables already in its enable function. */
+ if (!done) {
+ setup_bsp_ramtop();
+ setup_uma_memory();
+ done = 1;
+ }
+
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_amd_agesa_00730F01_root_complex_ops = {
+ CHIP_NAME("AMD FAM16 Root Complex")
+ .enable_dev = root_complex_enable_dev,
+};
+
+/*********************************************************************
+ * Change the vendor / device IDs to match the generic VBIOS header. *
+ *********************************************************************/
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev;
+ new_vendev =
+ ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev;
+
+ if (vendev != new_vendev)
+ printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev);
+
+ return new_vendev;
+}
diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.h b/src/northbridge/amd/agesa/00730F01/northbridge.h
new file mode 100644
index 0000000..6fa8164
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM16H_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index d5c039f..6caff0f 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -37,5 +37,6 @@ source src/northbridge/amd/agesa/family14/Kconfig
source src/northbridge/amd/agesa/family15/Kconfig
source src/northbridge/amd/agesa/family15tn/Kconfig
source src/northbridge/amd/agesa/family16kb/Kconfig
+source src/northbridge/amd/agesa/00730F01/Kconfig
endif # NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 8f10664..f1be023 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01) += 00730F01
romstage-y += def_callouts.c
ramstage-y += def_callouts.c
diff --git a/src/northbridge/amd/agesa/common/Makefile.inc b/src/northbridge/amd/agesa/common/Makefile.inc
new file mode 100644
index 0000000..d3d8087
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/Makefile.inc
@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += ../../../../device/dram/ddr3.c
+romstage-y += common.c
+
+ramstage-y += common.c
diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c
new file mode 100644
index 0000000..91c58e3
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/common.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "common.h"
+#include <device/dram/ddr3.h>
+#include <string.h>
+#include <cbfs.h>
+
+AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ size_t spd_file_length;
+
+ if (info->MemChannelId > CONFIG_AGESA_DDR3_CHANNEL_MAX)
+ return AGESA_ERROR;
+ if (info->SocketId != 0)
+ return AGESA_ERROR;
+ if (info->DimmId != 0)
+ return AGESA_ERROR;
+
+ char *spd_file;
+
+ spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_SPD_BIN, &spd_file_length);
+ if (!spd_file)
+ die("file [spd.bin] not found in CBFS");
+
+ printk(BIOS_DEBUG, "\nCBFS SPD file length = 0x%x bytes\n", (unsigned int)spd_file_length);
+
+ if (CONFIG_MULTIPLE_DDR_SPD) {
+ struct multi_spd_info *spd_info = (struct multi_spd_info *)info->Buffer;
+ printk(BIOS_DEBUG, "Multiple DDR SPD: using offset %d\n", spd_info->offset);
+ if (spd_info->offset > (spd_file_length / spd_info->size))
+ printk(BIOS_EMERG, "Multiple SPD offset is greater than SPD length\n");
+ else {
+ spd_file += spd_info->offset * spd_info->size;
+ spd_file_length = spd_info->size;
+ }
+ }
+ memcpy((char*)info->Buffer, spd_file, spd_file_length);
+
+ u16 crc = spd_ddr3_calc_crc(info->Buffer, spd_file_length);
+ if (crc == 0){
+ printk(BIOS_EMERG, "Error: Unable to calculate CRC on SPD\n");
+ return AGESA_UNSUPPORTED;
+ }
+ if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
+ || (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
+ || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
+ printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
+ info->Buffer[SPD_CRC_LO] = crc & 0xff;
+ info->Buffer[SPD_CRC_HI] = crc >> 8;
+ u16 i;
+ printk(BIOS_SPEW, "\nDisplay the SPD");
+ for (i = 0; i < spd_file_length; i++) {
+ if((i % 16) == 0x00)
+ printk(BIOS_SPEW, "\n%02x: ",i);
+ printk(BIOS_SPEW, "%02x ", info->Buffer[i]);
+ }
+ printk(BIOS_SPEW, "\n");
+ }
+ return AGESA_SUCCESS;
+#else
+ return AGESA_UNSUPPORTED;
+#endif
+}
diff --git a/src/northbridge/amd/agesa/common/common.h b/src/northbridge/amd/agesa/common/common.h
new file mode 100644
index 0000000..f60091a
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/common.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESA_COMMON_H_
+#define _AGESA_COMMON_H_
+
+#define SPD_CRC_HI 127
+#define SPD_CRC_LO 126
+
+struct multi_spd_info {
+ u8 offset; // defines spd 0,1,...
+ u8 size; // defines spd size
+};
+
+AGESA_STATUS
+common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+#endif
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c
index 1184050..c8b74d4 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/northbridge/amd/agesa/def_callouts.c
@@ -103,7 +103,7 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
return Status;
}
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
/* FIXME: we would like GFX disable for fam14 too for headless systems. */
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
{
diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h
index cccce54..2d23f3e 100644
--- a/src/northbridge/amd/agesa/def_callouts.h
+++ b/src/northbridge/amd/agesa/def_callouts.h
@@ -24,7 +24,7 @@
#include "Porting.h"
#include "AGESA.h"
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6676
-gerrit
commit 803f05d127248c38ec87fdf1cb325ba904a395fe
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Wed Jul 16 11:25:21 2014 -0600
MullinsPI: Fletcher's Checksum computation routine
The AMD Platform Security Processor (PSP) requires a Fletcher's
Checksum at the end of the PSP directory. This code implements
a Fletcher's Checksum by reading bytes from stdin and writes the
bytes back to stdout with a checksum inserted into the byte stream
at the appropriate offset.
This utility is used on PSP binaries during coreboot build.
Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
util/fletcher/Makefile.inc | 8 +++
util/fletcher/fletcher.c | 122 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 130 insertions(+)
diff --git a/util/fletcher/Makefile.inc b/util/fletcher/Makefile.inc
new file mode 100644
index 0000000..2e9b79b
--- /dev/null
+++ b/util/fletcher/Makefile.inc
@@ -0,0 +1,8 @@
+fletcher_exe : fletcher.c
+ gcc fletcher.c -o fletcher
+
+fletcher : fletcher_exe
+
+clean:
+ @rm -f fletcher.o fletcher fletcher.exe
+
diff --git a/util/fletcher/fletcher.c b/util/fletcher/fletcher.c
new file mode 100644
index 0000000..dabe4b0
--- /dev/null
+++ b/util/fletcher/fletcher.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 1998-2006 The TCPDUMP project
+ * 2014 Sage Electronic Engineering, LLC
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code
+ * distributions retain the above copyright notice and this paragraph
+ * in its entirety, and (2) distributions including binary code include
+ * the above copyright notice and this paragraph in its entirety in
+ * the documentation or other materials provided with the distribution.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND
+ * WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
+ * LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE.
+ *
+ * Original code by Hannes Gredler <hannes(a)juniper.net>
+ * Rewritten for Fletcher32 by Bruce Griffith <Bruce.Griffith(a)se-eng.com>
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#define MAX_PSP_DIRECTORY_SIZE 512
+
+typedef unsigned int uint32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+
+/*
+ * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
+ * The checksum field of the passed PDU does not need to be reset to zero.
+ *
+ * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
+ * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
+ * alternative to cyclical redundancy checks because it provides error-
+ * detection properties similar to cyclical redundancy checks but at the
+ * cost of a simple summation technique. Its characteristics were first
+ * published in IEEE Transactions on Communications in January 1982. One
+ * version has been adopted by ISO for use in the class-4 transport layer
+ * of the network protocol.
+ *
+ * This program expects:
+ * stdin: The input file to compute a checksum for. The input file
+ * not be longer than 256 bytes.
+ * stdout: Copied from the input file with the Fletcher's Checksum
+ * inserted 8 bytes after the beginning of the file.
+ * stderr: Used to print out error messages.
+ */
+
+uint32_t fletcher32 (const uint16_t *pptr, int length)
+{
+
+ uint32_t c0;
+ uint32_t c1;
+ uint32_t checksum;
+ int index;
+
+ c0 = 0xFFFF;
+ c1 = 0xFFFF;
+
+ for (index = 0; index < length; index++) {
+ /*
+ * Ignore the contents of the checksum field.
+ */
+ c0 += *(pptr++);
+ c1 += c0;
+ if ((index % 360) == 0) {
+ c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow
+ c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow
+ }
+
+ }
+
+ c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow
+ c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow
+ checksum = (c1 << 16) | c0;
+
+ return checksum;
+}
+
+int main(int argc, char **argv)
+{
+ uint32_t checksum = 0xFFFFFFFF;
+ struct stat filestat = {};
+ int retcode = EINVAL;
+ size_t filesize = 0;
+
+ uint16_t buffer[MAX_PSP_DIRECTORY_SIZE / sizeof(uint16_t)];
+
+ retcode = fstat(fileno(stdin), &filestat);
+ filesize = filestat.st_size;
+ if (retcode < 0) {
+ perror("FLETCHER32");
+ return errno;
+ } else if (!((12 < filesize) && (filesize <= sizeof(buffer)))) {
+ fprintf(stderr, "FLETCHER32: input file is not valid for this program.\n");
+ return EINVAL;
+ }
+ retcode = read(fileno(stdin), (void *)buffer, filesize);
+ if (retcode < 0) {
+ perror("FLETCHER32");
+ return errno;
+ }
+
+ checksum = fletcher32(&buffer[2], filesize/2 - 2);
+ *((uint32_t *)& buffer[2]) = checksum;
+#ifdef DEBUG
+ fprintf(stderr, "Fletcher's Checksum: %x\n", checksum);
+#endif
+
+ retcode = write(fileno(stdout), buffer, filesize);
+ if (retcode < 0) {
+ perror("FLETCHER32");
+ return errno;
+ }
+
+ return 0;
+}